diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c
new file mode 100644
index 0000000..c915a89
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.c
@@ -0,0 +1,299 @@
+/** @file
+  Sample ACPI Platform Driver
+
+  Copyright (c) 2008 - 2011, Intel Corporation. All rights reserved.<BR>
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <PiDxe.h>
+
+#include <Protocol/AcpiTable.h>
+#include <Protocol/FirmwareVolume2.h>
+
+#include <Library/BaseLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_STATUS
+PlatformUpdateTables (
+  IN OUT EFI_ACPI_COMMON_HEADER       **Table
+  );
+
+VOID
+UpdateAcpiTable (
+  IN OUT EFI_ACPI_DESCRIPTION_HEADER      *TableHeader,
+  IN OUT EFI_STATUS                       *CommonCodeReturnStatus
+);
+
+/**
+  Locate the first instance of a protocol.  If the protocol requested is an
+  FV protocol, then it will return the first FV that contains the ACPI table
+  storage file.
+
+  @param  Instance      Return pointer to the first instance of the protocol
+
+  @return EFI_SUCCESS           The function completed successfully.
+  @return EFI_NOT_FOUND         The protocol could not be located.
+  @return EFI_OUT_OF_RESOURCES  There are not enough resources to find the protocol.
+
+**/
+EFI_STATUS
+LocateFvInstanceWithTables (
+  OUT EFI_FIRMWARE_VOLUME2_PROTOCOL **Instance
+  )
+{
+  EFI_STATUS                    Status;
+  EFI_HANDLE                    *HandleBuffer;
+  UINTN                         NumberOfHandles;
+  EFI_FV_FILETYPE               FileType;
+  UINT32                        FvStatus;
+  EFI_FV_FILE_ATTRIBUTES        Attributes;
+  UINTN                         Size;
+  UINTN                         Index;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL *FvInstance;
+
+  FvStatus = 0;
+
+  //
+  // Locate protocol.
+  //
+  Status = gBS->LocateHandleBuffer (
+                   ByProtocol,
+                   &gEfiFirmwareVolume2ProtocolGuid,
+                   NULL,
+                   &NumberOfHandles,
+                   &HandleBuffer
+                   );
+  if (EFI_ERROR (Status)) {
+    //
+    // Defined errors at this time are not found and out of resources.
+    //
+    return Status;
+  }
+
+
+
+  //
+  // Looking for FV with ACPI storage file
+  //
+
+  for (Index = 0; Index < NumberOfHandles; Index++) {
+    //
+    // Get the protocol on this handle
+    // This should not fail because of LocateHandleBuffer
+    //
+    Status = gBS->HandleProtocol (
+                     HandleBuffer[Index],
+                     &gEfiFirmwareVolume2ProtocolGuid,
+                     (VOID**) &FvInstance
+                     );
+    ASSERT_EFI_ERROR (Status);
+
+    //
+    // See if it has the ACPI storage file
+    //
+    Status = FvInstance->ReadFile (
+                           FvInstance,
+                           (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
+                           NULL,
+                           &Size,
+                           &FileType,
+                           &Attributes,
+                           &FvStatus
+                           );
+
+    //
+    // If we found it, then we are done
+    //
+    if (Status == EFI_SUCCESS) {
+      *Instance = FvInstance;
+      break;
+    }
+  }
+
+  //
+  // Our exit status is determined by the success of the previous operations
+  // If the protocol was found, Instance already points to it.
+  //
+
+  //
+  // Free any allocated buffers
+  //
+  gBS->FreePool (HandleBuffer);
+
+  return Status;
+}
+
+
+/**
+  This function calculates and updates an UINT8 checksum.
+
+  @param  Buffer          Pointer to buffer to checksum
+  @param  Size            Number of bytes to checksum
+
+**/
+VOID
+AcpiPlatformChecksum (
+  IN UINT8      *Buffer,
+  IN UINTN      Size
+  )
+{
+  UINTN ChecksumOffset;
+
+  ChecksumOffset = OFFSET_OF (EFI_ACPI_DESCRIPTION_HEADER, Checksum);
+
+  //
+  // Set checksum to 0 first
+  //
+  Buffer[ChecksumOffset] = 0;
+
+  //
+  // Update checksum value
+  //
+  Buffer[ChecksumOffset] = CalculateCheckSum8(Buffer, Size);
+}
+
+
+/**
+  Entrypoint of Acpi Platform driver.
+
+  @param  ImageHandle
+  @param  SystemTable
+
+  @return EFI_SUCCESS
+  @return EFI_LOAD_ERROR
+  @return EFI_OUT_OF_RESOURCES
+
+**/
+EFI_STATUS
+EFIAPI
+AcpiPlatformEntryPoint (
+  IN EFI_HANDLE         ImageHandle,
+  IN EFI_SYSTEM_TABLE   *SystemTable
+  )
+{
+  EFI_STATUS                     Status;
+  EFI_ACPI_TABLE_PROTOCOL        *AcpiTable;
+  EFI_FIRMWARE_VOLUME2_PROTOCOL  *FwVol;
+  INTN                           Instance;
+  EFI_ACPI_COMMON_HEADER         *CurrentTable;
+  UINTN                          TableHandle;
+  UINT32                         FvStatus;
+  UINTN                          TableSize;
+  UINTN                          Size;
+  EFI_STATUS                     TableStatus;
+
+  Instance     = 0;
+  CurrentTable = NULL;
+  TableHandle  = 0;
+
+  //
+  // Find the AcpiTable protocol
+  //
+  Status = gBS->LocateProtocol (&gEfiAcpiTableProtocolGuid, NULL, (VOID**)&AcpiTable);
+  if (EFI_ERROR (Status)) {
+    return EFI_ABORTED;
+  }
+
+  //
+  // Locate the firmware volume protocol
+  //
+  Status = LocateFvInstanceWithTables (&FwVol);
+  if (EFI_ERROR (Status)) {
+    return EFI_ABORTED;
+  }
+  //
+  // Read tables from the storage file.
+  //
+  while (Status == EFI_SUCCESS) {
+
+    Status = FwVol->ReadSection (
+                      FwVol,
+                      (EFI_GUID*)PcdGetPtr (PcdAcpiTableStorageFile),
+                      EFI_SECTION_RAW,
+                      Instance,
+                      (VOID**) &CurrentTable,
+                      &Size,
+                      &FvStatus
+                      );
+    if (!EFI_ERROR(Status)) {
+      //
+      // Add the table
+      //
+      TableStatus = PlatformUpdateTables (&CurrentTable);
+      if (TableStatus == EFI_SUCCESS) {
+        //
+        // Add the table
+        //
+        TableHandle = 0;
+        TableSize = ((EFI_ACPI_DESCRIPTION_HEADER *) CurrentTable)->Length;
+        ASSERT (Size >= TableSize);
+
+      //
+      // Checksum ACPI table
+      //
+      AcpiPlatformChecksum ((UINT8*)CurrentTable, TableSize);
+
+      //
+      // Install ACPI table
+      //
+      Status = AcpiTable->InstallAcpiTable (
+                            AcpiTable,
+                            CurrentTable,
+                            TableSize,
+                            &TableHandle
+                            );
+
+      //
+      // Free memory allocated by ReadSection
+      //
+      gBS->FreePool (CurrentTable);
+
+      if (EFI_ERROR(Status)) {
+        return EFI_ABORTED;
+      }
+
+      //
+      // Increment the instance
+      //
+      Instance++;
+      CurrentTable = NULL;
+    }
+  }
+  }
+return EFI_SUCCESS;
+}
+/**
+  This function will update any runtime platform specific information.
+  @param  Table     The table to update
+
+  @return EFI_SUCCESS           The function completed successfully.
+
+**/
+EFI_STATUS
+PlatformUpdateTables (
+  IN OUT EFI_ACPI_COMMON_HEADER       **Table
+  )
+{
+  EFI_STATUS                              Status;
+  EFI_ACPI_DESCRIPTION_HEADER             *TableHeader;
+
+  Status = EFI_SUCCESS;
+
+  TableHeader = (EFI_ACPI_DESCRIPTION_HEADER*) (*Table);
+
+  UpdateAcpiTable(TableHeader, &Status);
+
+  return Status;
+}
+
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni
new file mode 100644
index 0000000..1275549
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatform.uni
@@ -0,0 +1,22 @@
+// /** @file
+// Sample ACPI Platform Driver
+//
+// Sample ACPI Platform Driver
+//
+// Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+
+#string STR_MODULE_ABSTRACT             #language en-US "Sample ACPI Platform Driver"
+
+#string STR_MODULE_DESCRIPTION          #language en-US "Sample ACPI Platform Driver"
+
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
new file mode 100644
index 0000000..4caa7a4
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
@@ -0,0 +1,59 @@
+## @file
+#  Sample ACPI Platform Driver
+#
+#  Copyright (c) 2008 - 2014, Intel Corporation. All rights reserved.<BR>
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = AcpiPlatform
+  MODULE_UNI_FILE                = AcpiPlatform.uni
+  FILE_GUID                      = cb933912-df8f-4305-b1f9-7b44fa11395c
+  MODULE_TYPE                    = DXE_DRIVER
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = AcpiPlatformEntryPoint
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+#  VALID_ARCHITECTURES           = IA32 X64 IPF EBC
+#
+
+[Sources]
+  AcpiPlatform.c
+  UpdateAcpiTable.c
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  UefiLib
+  DxeServicesLib
+  PcdLib
+  BaseMemoryLib
+  DebugLib
+  UefiBootServicesTableLib
+  UefiDriverEntryPoint
+  HobLib
+
+[Protocols]
+  gEfiAcpiTableProtocolGuid                     ## CONSUMES
+[Guids]
+  gHisiEfiMemoryMapGuid
+[Pcd]
+  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile    ## CONSUMES
+
+[Depex]
+  gEfiAcpiTableProtocolGuid
+
+[UserExtensions.TianoCore."ExtraFiles"]
+  AcpiPlatformExtra.uni
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni
new file mode 100644
index 0000000..4c21968
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformExtra.uni
@@ -0,0 +1,20 @@
+// /** @file
+// AcpiPlatform Localized Strings and Content
+//
+// Copyright (c) 2013 - 2014, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// **/
+
+#string STR_PROPERTIES_MODULE_NAME
+#language en-US
+"ACPI Platform Sample DXE Driver"
+
+
diff --git a/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
new file mode 100644
index 0000000..702f959
--- /dev/null
+++ b/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
@@ -0,0 +1,127 @@
+
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <Library/UefiBootServicesTableLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/UefiLib.h>
+#include <IndustryStandard/Acpi61.h>
+#include <PlatformArch.h>
+#include <Library/OemMiscLib.h>
+#include <Library/AcpiNextLib.h>
+#include <Library/HobLib.h>
+#include <Library/HwMemInitLib.h>
+
+#define  MaxMemoryNode      10
+UINT8 MemoryNode = 0;
+
+EFI_STATUS
+RemoveInvalidMemoryNode (
+  IN OUT EFI_ACPI_DESCRIPTION_HEADER  *Table,
+  IN     UINTN                        MemoryNodeNum
+)
+{
+  UINT8                   *CurrPtr, *EndPtr, *NextValidPtr;
+  UINT32                  NeedRemoveLength;
+  if (MemoryNodeNum >= MaxMemoryNode)
+  {
+     DEBUG((EFI_D_ERROR, "There are no invalid memory node\n"));
+     return EFI_INVALID_PARAMETER;
+  }
+  CurrPtr = (UINT8*) &((EFI_ACPI_DESCRIPTION_HEADER*) (Table))[1];
+  CurrPtr = CurrPtr + 4 + 8; // revision + reserved
+  NextValidPtr = CurrPtr + ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) Table)->Memory[0].Length * MaxMemoryNode;
+  EndPtr = (UINT8*) (Table);
+  EndPtr = EndPtr + (Table)->Length;
+  NeedRemoveLength = ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) Table)->Memory[0].Length * (MaxMemoryNode - MemoryNodeNum);
+
+  CurrPtr = CurrPtr + ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) Table)->Memory[0].Length * MemoryNodeNum;
+  CopyMem (CurrPtr, NextValidPtr, (UINTN)EndPtr - (UINTN)NextValidPtr); //copy data to current ptr
+  (Table)->Length -= NeedRemoveLength;
+
+  return EFI_SUCCESS;
+}
+
+STATIC
+EFI_STATUS
+UpdateSrat (
+  IN OUT EFI_ACPI_DESCRIPTION_HEADER  *Table
+  )
+{
+  UINT8               Skt = 0;
+  UINT8               Ch = 0;
+  VOID*               HobList;
+  GBL_DATA           *Gbl_Data;
+  UINTN               Base;
+  UINTN               Size;
+  UINT8               NodeId;
+  UINT32              DieInterleaveEn;
+  UINT8               i;
+
+  DEBUG(( EFI_D_ERROR, "\nSRAT: Updating SRAT memory information!\n" ));
+
+  HobList = GetHobList();
+  Gbl_Data = (GBL_DATA*)GetNextGuidHob(&gHisiEfiMemoryMapGuid, HobList);
+  Gbl_Data = GET_GUID_HOB_DATA(Gbl_Data);
+  for(Skt = 0; Skt < MAX_SOCKET; Skt++){
+      for(Ch = 0; Ch < MAX_NUM_PER_TYPE; Ch++){
+          NodeId = Gbl_Data->NumaInfo[Skt][Ch].NodeId;
+          Base = Gbl_Data->NumaInfo[Skt][Ch].Base;
+          Size = Gbl_Data->NumaInfo[Skt][Ch].Length;
+          DieInterleaveEn = Gbl_Data->NumaInfo[Skt][Ch].DieInterleaveEn;
+          DEBUG((EFI_D_INFO,"Skt %d Ch: %d NodeId = %d, Base = 0x%lx, Size = 0x%lx, DieInterLeaveEn = %d\n",Skt,Ch,NodeId,Base,Size,DieInterleaveEn));
+          if (Size > 0)
+          {
+              ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) Table)->Memory[MemoryNode].ProximityDomain = NodeId;
+              ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) Table)->Memory[MemoryNode].AddressBaseLow = Base;
+              ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) Table)->Memory[MemoryNode].AddressBaseHigh = Base >> 32;
+              ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) Table)->Memory[MemoryNode].LengthLow = Size;
+              ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) Table)->Memory[MemoryNode].LengthHigh = Size >> 32;
+              MemoryNode = MemoryNode + 1;
+          }
+      }
+  }
+
+  //update gicc structure
+  if(DieInterleaveEn != 0)
+  {
+      DEBUG(( EFI_D_ERROR, "\nSRAT: Updating SRAT Gicc information!\n" ));
+      for (i = 0; i < 32; i ++)
+          ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) Table)->Gicc[i].ProximityDomain = 0;
+      for (i = 32; i < 64; i ++)
+          ((EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE *) Table)->Gicc[i].ProximityDomain = 2;
+  }
+
+  //remove invalid memory node
+  (VOID)RemoveInvalidMemoryNode (Table, MemoryNode);
+
+  return EFI_SUCCESS;
+
+}
+
+STATIC
+EFI_STATUS
+UpdateSlit (
+  IN OUT EFI_ACPI_DESCRIPTION_HEADER  *Table
+  )
+{
+  return  EFI_SUCCESS;
+}
+
+VOID
+UpdateAcpiTable (
+  IN OUT EFI_ACPI_DESCRIPTION_HEADER      *TableHeader,
+  IN OUT EFI_STATUS                       *CommonCodeReturnStatus
+)
+{
+  switch ((TableHeader)->Signature) {
+
+  case EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE:
+    *CommonCodeReturnStatus = UpdateSrat (TableHeader);
+    break;
+
+  case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE:
+    *CommonCodeReturnStatus = UpdateSlit (TableHeader);
+    break;
+  }
+  return;
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
new file mode 100644
index 0000000..4625191
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
@@ -0,0 +1,58 @@
+## @file
+#
+#  ACPI table data and ASL sources required to boot the platform.
+#
+#  Copyright (c) 2014, ARM Ltd. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = Hi1616AcpiTables
+  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
+  MODULE_TYPE                    = USER_DEFINED
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  Dsdt/DsdtHi1616.asl
+  Facs.aslc
+  Fadt.aslc
+  Gtdt.aslc
+  MadtHi1616.aslc
+  D05Mcfg.aslc
+  D05Iort.asl
+  D05Slit.aslc
+  D05Srat.aslc
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  ArmPlatformPkg/ArmPlatformPkg.dec
+  EmbeddedPkg/EmbeddedPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[FixedPcd]
+  gArmPlatformTokenSpaceGuid.PcdCoreCount
+  gArmTokenSpaceGuid.PcdGicDistributorBase
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
+
+  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
+  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl
new file mode 100644
index 0000000..61a3c33
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Iort.asl
@@ -0,0 +1,651 @@
+/*
+ * Intel ACPI Component Architecture
+ * iASL Compiler/Disassembler version 20151124-64
+ * Copyright (c) 2000 - 2015 Intel Corporation
+ *
+ * Template for [IORT] ACPI Table (static data table)
+ * Format: [ByteLength]  FieldName : HexFieldValue
+ */
+[0004]                          Signature : "IORT"    [IO Remapping Table]
+[0004]                       Table Length : 000002e4
+[0001]                           Revision : 00
+[0001]                           Checksum : BC
+[0006]                             Oem ID : "HISI  "
+[0008]                       Oem Table ID : "HIP07   "
+[0004]                       Oem Revision : 00000000
+[0004]                    Asl Compiler ID : "INTL"
+[0004]              Asl Compiler Revision : 20151124
+
+[0004]                         Node Count : 00000008
+[0004]                        Node Offset : 00000034
+[0004]                           Reserved : 00000000
+[0004]                   Optional Padding : 00 00 00 00
+
+/* ITS 0, for peri a */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000000
+//4c
+/* ITS 1, for peri b */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000001
+//64
+/* ITS 2, for dsa a */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000002
+//7c
+/* ITS 3, for dsa b */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000003
+//94
+/*Sec CPU ITS 0, for peri a */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000004
+//ac
+/* SEC CPU ITS 1, for peri b */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000005
+//c4
+/* SEC CPU ITS 2, for dsa a */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000006
+//dc
+/* SEC CPU ITS 3, for dsa b */
+[0001]                               Type : 00
+[0002]                             Length : 0018
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000000
+[0004]                     Mapping Offset : 00000000
+
+[0004]                           ItsCount : 00000001
+[0004]                        Identifiers : 00000007
+
+
+
+/* mbi-gen peri b, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI0"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 000120c7 //device id
+[0004]                   Output Reference : 0000004C
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen1 dsa a, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI1"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040800    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen mbi7 - RoCE named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI9"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040b1e
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                           Single Mapping : 1
+
+/* mbi-gen dsa a - usb named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI5"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040080    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen1 dsa a, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI2"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040900    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen1 pcie, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI3"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040000    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen1 pcie, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI4"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040040    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen1 alg a, i2c 0 named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI6"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040B0E    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/* mbi-gen1 alg a, i2c 2 named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI7"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00040B10    //device id
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
+
+/*1P NA PCIe2 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000002
+
+[0004]                         Input base : 00008000
+[0004]                           ID Count : 00000800
+[0004]                        Output Base : 00008000
+[0004]                   Output Reference : 00000064
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+/* 1P NB PCIe0 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000004
+
+[0004]                         Input base : 00008800
+[0004]                           ID Count : 00000800
+[0004]                        Output Base : 00008800
+[0004]                   Output Reference : 0000007c
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* 1P NB PCIe1 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000005
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000800
+[0004]                        Output Base : 00000000
+[0004]                   Output Reference : 0000007c
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* 1P NB PCIe2 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000006
+
+[0004]                         Input base : 0000c000
+[0004]                           ID Count : 00000800
+[0004]                        Output Base : 0000c000
+[0004]                   Output Reference : 0000007c
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+/* 1P NB PCIe3 */
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 00000007
+
+[0004]                         Input base : 00009000
+[0004]                           ID Count : 00000800
+[0004]                        Output Base : 00009000
+[0004]                   Output Reference : 0000007c
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+/* 2P NA PCIe2*/
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 0000000a
+
+[0004]                         Input base : 00001000
+[0004]                           ID Count : 00001000
+[0004]                        Output Base : 00001000
+[0004]                   Output Reference : 000000c4
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* 2P NB PCIe0*/
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 0000000c
+
+[0004]                         Input base : 00002000
+[0004]                           ID Count : 00001000
+[0004]                        Output Base : 00002000
+[0004]                   Output Reference : 000000dc
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+ /* 2P NB PCIe1*/
+[0001]                               Type : 02
+[0002]                             Length : 0034
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000020
+
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000001
+[0001]              Hints (decoded below) : 00
+                                Transient : 0
+                           Write Allocate : 0
+                            Read Allocate : 0
+                                 Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                                Coherency : 0
+                         Device Attribute : 0
+[0004]                      ATS Attribute : 00000000
+[0004]                 PCI Segment Number : 0000000d
+
+[0004]                         Input base : 00003000
+[0004]                           ID Count : 00001000
+[0004]                        Output Base : 00003000
+[0004]                   Output Reference : 000000dc
+[0004]              Flags (decoded below) : 00000000
+                           Single Mapping : 0
+
+/* mbi-gen1 P1 dsa a, named component */
+[0001]                               Type : 01
+[0002]                             Length : 0046
+[0001]                           Revision : 00
+[0004]                           Reserved : 00000000
+[0004]                      Mapping Count : 00000001
+[0004]                     Mapping Offset : 00000032
+
+[0004]                         Node Flags : 00000000
+[0008]                  Memory Properties : [IORT Memory Access Properties]
+[0004]                    Cache Coherency : 00000000
+[0001]              Hints (decoded below) : 00
+                               Transient : 0
+                          Write Allocate : 0
+                           Read Allocate : 0
+                                Override : 0
+[0002]                           Reserved : 0000
+[0001]       Memory Flags (decoded below) : 00
+                               Coherency : 0
+                        Device Attribute : 0
+[0001]                  Memory Size Limit : 00
+[0016]                        Device Name : "\_SB_.MBI8"
+[0004]                            Padding : 00 00 00 00
+
+[0004]                         Input base : 00000000
+[0004]                           ID Count : 00000001
+[0004]                        Output Base : 00044800  //device id
+[0004]                   Output Reference : 000000c4
+[0004]              Flags (decoded below) : 00000001
+                          Single Mapping : 1
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc
new file mode 100644
index 0000000..9255037
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Mcfg.aslc
@@ -0,0 +1,127 @@
+/*
+ * Copyright (c) 2016 Hisilicon Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ */
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1616Platform.h"
+
+#define ACPI_5_0_MCFG_VERSION  0x1
+
+#pragma pack(1)
+typedef struct
+{
+   UINT64 ullBaseAddress;
+   UINT16 usSegGroupNum;
+   UINT8  ucStartBusNum;
+   UINT8  ucEndBusNum;
+   UINT32 Reserved2;
+}EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE;
+
+typedef struct
+{
+   EFI_ACPI_DESCRIPTION_HEADER Header;
+   UINT64 Reserved1;
+}EFI_ACPI_5_0_MCFG_TABLE_CONFIG;
+
+typedef struct
+{
+   EFI_ACPI_5_0_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
+   EFI_ACPI_5_0_MCFG_CONFIG_STRUCTURE Config_Structure[8];
+}EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
+#pragma pack()
+
+EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
+{
+  {
+      {
+        EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+        sizeof (EFI_ACPI_5_0_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
+        ACPI_5_0_MCFG_VERSION,
+        0x00,                                                     // Checksum will be updated at runtime
+        {EFI_ACPI_ARM_OEM_ID},
+        EFI_ACPI_ARM_OEM_TABLE_ID,
+        EFI_ACPI_ARM_OEM_REVISION,
+        EFI_ACPI_ARM_CREATOR_ID,
+        EFI_ACPI_ARM_CREATOR_REVISION
+      },
+      0x0000000000000000,                                 //Reserved
+  },
+  {
+    //1p NA PCIe2
+    {
+      0xa0000000,                                         //Base Address
+      0x2,                                                //Segment Group Number
+      0x80,                                               //Start Bus Number
+      0x87,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //1p NB PCIe0
+    {
+      0x8a0000000,                                         //Base Address
+      0x4,                                                //Segment Group Number
+      0x88,                                               //Start Bus Number
+      0x8f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //1p NB PCIe1
+    {
+      0x8b0000000,                                         //Base Address
+      0x5,                                                //Segment Group Number
+      0x0,                                               //Start Bus Number
+      0x7,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //1p NB PCIe2
+    {
+      0x8a0000000,                                         //Base Address
+      0x6,                                                //Segment Group Number
+      0xc0,                                               //Start Bus Number
+      0xc7,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //1p NB PCIe3
+    {
+      0x8b0000000,                                         //Base Address
+      0x7,                                                //Segment Group Number
+      0x90,                                               //Start Bus Number
+      0x97,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //2P NA PCIe2
+    {
+      0x64000000000,                                      //Base Address
+      0xa,                                                //Segment Group Number
+      0x10,                                               //Start Bus Number
+      0x1f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //2P NB PCIe0
+    {
+      0x74000000000,                                      //Base Address
+      0xc,                                                //Segment Group Number
+      0x20,                                               //Start Bus Number
+      0x2f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+    //2P NB PCIe1
+    {
+      0x78000000000,                                       //Base Address
+      0xd,                                                //Segment Group Number
+      0x30,                                               //Start Bus Number
+      0x3f,                                               //End Bus Number
+      0x00000000,                                         //Reserved
+    },
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Mcfg;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc
new file mode 100644
index 0000000..2276240
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Slit.aslc
@@ -0,0 +1,64 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     Yi Li - yi.li@linaro.org
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1616Platform.h"
+
+#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000004
+
+#pragma pack(1)
+typedef struct {
+  UINT8   Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+} EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
+
+typedef struct {
+  EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER    Header;
+  EFI_ACPI_6_0_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE                NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
+
+} EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE;
+#pragma pack()
+
+//
+// System Locality Information Table
+// Please modify all values in Slit.h only.
+//
+EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
+  {
+    {
+      EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,
+      sizeof (EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE),
+      EFI_ACPI_6_0_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,
+      0x00,                                                     // Checksum will be updated at runtime
+      {EFI_ACPI_ARM_OEM_ID},
+      EFI_ACPI_ARM_OEM_TABLE_ID,
+      EFI_ACPI_ARM_OEM_REVISION,
+      EFI_ACPI_ARM_CREATOR_ID,
+      EFI_ACPI_ARM_CREATOR_REVISION,
+    },
+    //
+    // Beginning of SLIT specific fields
+    //
+    EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
+  },
+  {
+    {{0x0A, 0x10, 0x20, 0x21}}, //Locality   0
+    {{0x10, 0x0A, 0x19, 0x20}}, //Locality   1
+    {{0x20, 0x19, 0x0A, 0x10}}, //Locality   2
+    {{0x21, 0x20, 0x10, 0x0A}}, //Locality   3
+  },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Slit;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
new file mode 100644
index 0000000..e3eb6c1
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/D05Srat.aslc
@@ -0,0 +1,129 @@
+/*
+ * Copyright (c) 2013 Linaro Limited
+ *
+ * All rights reserved. This program and the accompanying materials
+ * are made available under the terms of the BSD License which accompanies
+ * this distribution, and is available at
+ * http://opensource.org/licenses/bsd-license.php
+ *
+ * Contributors:
+ *     Yi Li - yi.li@linaro.org
+ *
+ *  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*/
+
+#include <IndustryStandard/Acpi.h>
+#include "Hi1616Platform.h"
+#include <Library/AcpiLib.h>
+#include <Library/AcpiNextLib.h>
+
+
+//
+// Static Resource Affinity Table definition
+//
+EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
+  {
+    {EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
+    sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE),
+    EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
+    0x00,                                                     // Checksum will be updated at runtime
+    {EFI_ACPI_ARM_OEM_ID},
+    EFI_ACPI_ARM_OEM_TABLE_ID,
+    EFI_ACPI_ARM_OEM_REVISION,
+    EFI_ACPI_ARM_CREATOR_ID,
+    EFI_ACPI_ARM_CREATOR_REVISION},
+    /*Reserved*/
+    0x00000001,                                  // Reserved to be 1 for backward compatibility
+    EFI_ACPI_RESERVED_QWORD
+  },
+
+  //
+  //
+  // Memory Affinity
+  //
+  {
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+    EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
+  },
+
+  {
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000001,0x00000000),   //GICC Affinity Processor 0
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000001,0x00000001,0x00000000),   //GICC Affinity Processor 1
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000002,0x00000001,0x00000000),   //GICC Affinity Processor 2
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000003,0x00000001,0x00000000),   //GICC Affinity Processor 3
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000004,0x00000001,0x00000000),   //GICC Affinity Processor 4
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000005,0x00000001,0x00000000),   //GICC Affinity Processor 5
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000006,0x00000001,0x00000000),   //GICC Affinity Processor 6
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000007,0x00000001,0x00000000),   //GICC Affinity Processor 7
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000008,0x00000001,0x00000000),   //GICC Affinity Processor 8
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000009,0x00000001,0x00000000),   //GICC Affinity Processor 9
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000A,0x00000001,0x00000000),   //GICC Affinity Processor 10
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000B,0x00000001,0x00000000),   //GICC Affinity Processor 11
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000C,0x00000001,0x00000000),   //GICC Affinity Processor 12
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000D,0x00000001,0x00000000),   //GICC Affinity Processor 13
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000E,0x00000001,0x00000000),   //GICC Affinity Processor 14
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000000F,0x00000001,0x00000000),   //GICC Affinity Processor 15
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000),   //GICC Affinity Processor 16
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000),   //GICC Affinity Processor 17
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000),   //GICC Affinity Processor 18
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000),   //GICC Affinity Processor 19
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000),   //GICC Affinity Processor 20
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000),   //GICC Affinity Processor 21
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000),   //GICC Affinity Processor 22
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000),   //GICC Affinity Processor 23
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000018,0x00000001,0x00000000),   //GICC Affinity Processor 24
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000019,0x00000001,0x00000000),   //GICC Affinity Processor 25
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001A,0x00000001,0x00000000),   //GICC Affinity Processor 26
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001B,0x00000001,0x00000000),   //GICC Affinity Processor 27
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001C,0x00000001,0x00000000),   //GICC Affinity Processor 28
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001D,0x00000001,0x00000000),   //GICC Affinity Processor 29
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001E,0x00000001,0x00000000),   //GICC Affinity Processor 30
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000001F,0x00000001,0x00000000),   //GICC Affinity Processor 31
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000020,0x00000001,0x00000000),   //GICC Affinity Processor 32
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000021,0x00000001,0x00000000),   //GICC Affinity Processor 33
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000022,0x00000001,0x00000000),   //GICC Affinity Processor 34
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000023,0x00000001,0x00000000),   //GICC Affinity Processor 35
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000024,0x00000001,0x00000000),   //GICC Affinity Processor 36
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000025,0x00000001,0x00000000),   //GICC Affinity Processor 37
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000026,0x00000001,0x00000000),   //GICC Affinity Processor 38
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000027,0x00000001,0x00000000),   //GICC Affinity Processor 39
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000028,0x00000001,0x00000000),   //GICC Affinity Processor 40
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000029,0x00000001,0x00000000),   //GICC Affinity Processor 41
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002A,0x00000001,0x00000000),   //GICC Affinity Processor 42
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002B,0x00000001,0x00000000),   //GICC Affinity Processor 43
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002C,0x00000001,0x00000000),   //GICC Affinity Processor 44
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002D,0x00000001,0x00000000),   //GICC Affinity Processor 45
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002E,0x00000001,0x00000000),   //GICC Affinity Processor 46
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000002F,0x00000001,0x00000000),   //GICC Affinity Processor 47
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000),   //GICC Affinity Processor 48
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000),   //GICC Affinity Processor 49
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000),   //GICC Affinity Processor 50
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000),   //GICC Affinity Processor 51
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000),   //GICC Affinity Processor 52
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000),   //GICC Affinity Processor 53
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000),   //GICC Affinity Processor 54
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000),   //GICC Affinity Processor 55
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000),   //GICC Affinity Processor 56
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000),   //GICC Affinity Processor 57
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000),   //GICC Affinity Processor 58
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000),   //GICC Affinity Processor 59
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000),   //GICC Affinity Processor 60
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000),   //GICC Affinity Processor 61
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000),   //GICC Affinity Processor 62
+    EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000)    //GICC Affinity Processor 63
+  },
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Srat;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl
new file mode 100644
index 0000000..8c65ae8
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/CPU.asl
@@ -0,0 +1,280 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+    //
+    // A57x16 Processor declaration
+    //
+    Device(CPU0) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 0)
+    }
+    Device(CPU1) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 1)
+    }
+    Device(CPU2) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 2)
+    }
+    Device(CPU3) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 3)
+    }
+    Device(CPU4) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 4)
+    }
+    Device(CPU5) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 5)
+    }
+    Device(CPU6) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 6)
+    }
+    Device(CPU7) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 7)
+    }
+    Device(CPU8) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 8)
+    }
+    Device(CPU9) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 9)
+    }
+    Device(CP10) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 10)
+    }
+    Device(CP11) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 11)
+    }
+    Device(CP12) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 12)
+    }
+    Device(CP13) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 13)
+    }
+    Device(CP14) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 14)
+    }
+    Device(CP15) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 15)
+    }
+    Device(CP16) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 16)
+    }
+    Device(CP17) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 17)
+    }
+    Device(CP18) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 18)
+    }
+    Device(CP19) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 19)
+    }
+    Device(CP20) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 20)
+    }
+    Device(CP21) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 21)
+    }
+    Device(CP22) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 22)
+    }
+    Device(CP23) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 23)
+    }
+    Device(CP24) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 24)
+    }
+    Device(CP25) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 25)
+    }
+    Device(CP26) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 26)
+    }
+    Device(CP27) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 27)
+    }
+    Device(CP28) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 28)
+    }
+    Device(CP29) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 29)
+    }
+    Device(CP30) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 30)
+    }
+    Device(CP31) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 31)
+    }
+    Device(CP32) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 32)
+    }
+    Device(CP33) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 33)
+    }
+    Device(CP34) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 34)
+    }
+    Device(CP35) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 35)
+    }
+    Device(CP36) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 36)
+    }
+    Device(CP37) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 37)
+    }
+    Device(CP38) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 38)
+    }
+    Device(CP39) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 39)
+    }
+    Device(CP40) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 40)
+    }
+    Device(CP41) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 41)
+    }
+    Device(CP42) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 42)
+    }
+    Device(CP43) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 43)
+    }
+    Device(CP44) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 44)
+    }
+    Device(CP45) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 45)
+    }
+    Device(CP46) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 46)
+    }
+    Device(CP47) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 47)
+    }
+    Device(CP48) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 48)
+    }
+    Device(CP49) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 49)
+    }
+    Device(CP50) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 50)
+    }
+    Device(CP51) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 51)
+    }
+    Device(CP52) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 52)
+    }
+    Device(CP53) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 53)
+    }
+    Device(CP54) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 54)
+    }
+    Device(CP55) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 55)
+    }
+    Device(CP56) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 56)
+    }
+    Device(CP57) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 57)
+    }
+    Device(CP58) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 58)
+    }
+    Device(CP59) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 59)
+    }
+    Device(CP60) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 60)
+    }
+    Device(CP61) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 61)
+    }
+    Device(CP62) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 62)
+    }
+    Device(CP63) {
+      Name(_HID, "ACPI0007")
+      Name(_UID, 63)
+    }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl
new file mode 100644
index 0000000..a4c4760
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Com.asl
@@ -0,0 +1,37 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+  Device(COM0) {
+    Name(_HID, "ARMH0011")
+    Name(_CID, "PL011")
+    Name(_UID, Zero)
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0x602B0000, 0x1000)
+      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI0") { 807 }
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        //Package () {"clock-frequency", 200000000},
+        Package () {"interrupt-parent",Package() {\_SB.MBI0}},
+      }
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
new file mode 100644
index 0000000..3c33024
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Hns.asl
@@ -0,0 +1,1234 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  Device (MDIO)
+  {
+    OperationRegion(CLKR, SystemMemory, 0x60000550, 8)
+    Field(CLKR, DWordAcc, NoLock, Preserve) {
+      CLKE, 1,  // clock enable
+      , 31,
+      CLKD, 1,  // clode disable
+      , 31,
+    }
+    OperationRegion(RSTR, SystemMemory, 0x60000c40, 8)
+    Field(RSTR, DWordAcc, NoLock, Preserve) {
+      RSTE, 1,  // reset
+      , 31,
+      RSTD, 1,  // de-reset
+      , 31,
+    }
+
+    Name(_HID, "HISI0141")
+    Name (_CRS, ResourceTemplate (){
+      Memory32Fixed (ReadWrite, 0x603c0000 , 0x10000)
+            })
+
+    Method(_RST, 0, Serialized) {
+      Store (0x1, RSTE)
+      Sleep (10)
+      Store (0x1, CLKD)
+      Sleep (10)
+      Store (0x1, RSTD)
+      Sleep (10)
+      Store (0x1, CLKE)
+      Sleep (10)
+    }
+  }
+
+  Device (DSF0)
+  {
+    OperationRegion(H3SR, SystemMemory, 0xC0000184, 4)
+    Field(H3SR, DWordAcc, NoLock, Preserve) {
+          H3ST, 1,
+          , 31,  //RESERVED
+        }
+    OperationRegion(H4SR, SystemMemory, 0xC0000194, 4)
+    Field(H4SR, DWordAcc, NoLock, Preserve) {
+          H4ST, 1,
+          , 31,  //RESERVED
+        }
+    // DSAF RESET
+    OperationRegion(DRER, SystemMemory, 0xC0000A00, 8)
+    Field(DRER, DWordAcc, NoLock, Preserve) {
+          DRTE, 1,
+          , 31,  //RESERVED
+          DRTD, 1,
+          , 31,  //RESERVED
+        }
+    // NT RESET
+    OperationRegion(NRER, SystemMemory, 0xC0000A08, 8)
+    Field(NRER, DWordAcc, NoLock, Preserve) {
+          NRTE, 1,
+          , 31,  //RESERVED
+          NRTD, 1,
+          , 31,  //RESERVED
+        }
+    // XGE RESET
+    OperationRegion(XRER, SystemMemory, 0xC0000A10, 8)
+    Field(XRER, DWordAcc, NoLock, Preserve) {
+          XRTE, 31,
+          , 1,    //RESERVED
+          XRTD, 31,
+          , 1,    //RESERVED
+        }
+
+    // GE RESET
+    OperationRegion(GRTR, SystemMemory, 0xC0000A18, 16)
+    Field(GRTR, DWordAcc, NoLock, Preserve) {
+          GR0E, 30,
+          , 2,    //RESERVED
+          GR0D, 30,
+          , 2,    //RESERVED
+          GR1E, 18,
+          , 14,  //RESERVED
+          GR1D, 18,
+          , 14,  //RESERVED
+        }
+    // PPE RESET
+    OperationRegion(PRTR, SystemMemory, 0xC0000A48, 8)
+    Field(PRTR, DWordAcc, NoLock, Preserve) {
+          PRTE, 10,
+          , 22,  //RESERVED
+          PRTD, 10,
+          , 22,  //RESERVED
+        }
+
+    // RCB PPE COM RESET
+    OperationRegion(RRTR, SystemMemory, 0xC0000A88, 8)
+    Field(RRTR, DWordAcc, NoLock, Preserve) {
+          RRTE, 1,
+          , 31,  //RESERVED
+          RRTD, 1,
+          , 31,  //RESERVED
+        }
+
+    // DSAF Channel RESET
+    OperationRegion(DCRR, SystemMemory, 0xC0000AA8, 8)
+    Field(DCRR, DWordAcc, NoLock, Preserve) {
+        DCRE, 1,
+        , 31,  //RESERVED
+        DCRD, 1,
+      , 31,  //RESERVED
+    }
+
+    // RoCE RESET
+    OperationRegion(RKRR, SystemMemory, 0xC0000A50, 8)
+    Field(RKRR, DWordAcc, NoLock, Preserve) {
+          RKRE, 1,
+          , 31,  //RESERVED
+          RKRD, 1,
+          , 31,  //RESERVED
+        }
+
+    // RoCE Clock enable/disable
+    OperationRegion(RKCR, SystemMemory, 0xC0000328, 8)
+    Field(RKCR, DWordAcc, NoLock, Preserve) {
+          RCLE, 1,
+          , 31,  //RESERVED
+          RCLD, 1,
+          , 31,  //RESERVED
+        }
+
+    // Hilink access sel cfg reg
+    OperationRegion(HSER, SystemMemory, 0xC2240008, 0x4)
+    Field(HSER, DWordAcc, NoLock, Preserve) {
+          HSEL, 2,  // hilink_access_sel & hilink_access_wr_pul
+          , 30,    // RESERVED
+        }
+
+    // Serdes
+    OperationRegion(H4LR, SystemMemory, 0xC2208100, 0x1000)
+    Field(H4LR, DWordAcc, NoLock, Preserve) {
+          H4L0, 16,    // port0
+          , 16,    //RESERVED
+          Offset (0x400),
+          H4L1, 16,    // port1
+          , 16,    //RESERVED
+          Offset (0x800),
+          H4L2, 16,    // port2
+          , 16,    //RESERVED
+          Offset (0xc00),
+          H4L3, 16,    // port3
+          , 16,    //RESERVED
+        }
+    OperationRegion(H3LR, SystemMemory, 0xC2208900, 0x800)
+    Field(H3LR, DWordAcc, NoLock, Preserve) {
+          H3L2, 16,    // port4
+          , 16,    //RESERVED
+          Offset (0x400),
+          H3L3, 16,    // port5
+          , 16,    //RESERVED
+        }
+                Name (_HID, "HISI00B2")
+                Name (_CCA, 1) // Cache-coherent controller
+                Name (_CRS, ResourceTemplate (){
+                        Memory32Fixed (ReadWrite, 0xc5000000 , 0x890000)
+                        Memory32Fixed (ReadWrite, 0xc7000000 , 0x60000)
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+        {
+          576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+          589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+        }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+        {
+          960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+          976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+          992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+          1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+          1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+          1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+          1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+          1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+          1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+          1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+          1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+          1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+        }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI1")
+        {
+          1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+          1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+          1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+          1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+          1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+          1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+          1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+          1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+          1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+          1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+          1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+          1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+        }
+                })
+                Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"mode", "6port-16rss"},
+        Package () {"buf-size", 4096},
+        Package () {"desc-num", 1024},
+        Package () {"interrupt-parent", Package() {\_SB.MBI1}},
+                        }
+                })
+
+    //reset XGE port
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XRST, 2, Serialized) {
+      ShiftLeft (0x2082082, Arg0, Local0)
+      Or (Local0, 0x1, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset XGE core
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XCRT, 2, Serialized) {
+      ShiftLeft (0x2080, Arg0, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset GE port
+    //Arg0 : GE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(GRST, 2, Serialized) {
+      If (LLessEqual (Arg0, 5)) {
+        //Service port
+        ShiftLeft (0x2082082, Arg0, Local0)
+        ShiftLeft (0x1, Arg0, Local1)
+
+        If (LEqual (Arg1, 0)) {
+          Store(Local1, GR1E)
+          Store(Local0, GR0E)
+        } Else  {
+          Store(Local0, GR0D)
+          Store(Local1, GR1D)
+        }
+      }
+    }
+
+    //reset PPE port
+    //Arg0 : PPE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(PRST, 2, Serialized) {
+      ShiftLeft (0x1, Arg0, Local0)
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, PRTE)
+      } Else  {
+        Store(Local0, PRTD)
+      }
+    }
+
+    //reset DSAF channels
+    //Arg0 : mask
+    //Arg1 : 0 reset, 1 de-reset
+    Method(DCRT, 2, Serialized) {
+      If (LEqual (Arg1, 0)) {
+        Store(Arg0, DCRE)
+      } Else  {
+        Store(Arg0, DCRD)
+      }
+    }
+
+    //reset RoCE
+    //Arg0 : 0 reset, 1 de-reset
+    Method(RRST, 1, Serialized) {
+      If (LEqual (Arg0, 0)) {
+        Store(0x1, RKRE)
+      } Else  {
+        Store(0x1, RCLD)
+        Store(0x1, RKRD)
+        sleep(20)
+        Store(0x1, RCLE)
+      }
+    }
+
+    // Set Serdes Loopback
+    //Arg0 : port
+    //Arg1 : 0 disable, 1 enable
+    Method(SRLP, 2, Serialized) {
+      ShiftLeft (Arg1, 10, Local0)
+      Switch (ToInteger(Arg0))
+      {
+        case (0x0){
+          Store (0, HSEL)
+          Store (H4L0, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L0)
+        }
+        case (0x1){
+          Store (0, HSEL)
+          Store (H4L1, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L1)
+        }
+        case (0x2){
+          Store (0, HSEL)
+          Store (H4L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L2)
+        }
+        case (0x3){
+          Store (0, HSEL)
+          Store (H4L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L3)
+        }
+        case (0x4){
+          Store (3, HSEL)
+          Store (H3L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L2)
+        }
+        case (0x5){
+          Store (3, HSEL)
+          Store (H3L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L3)
+        }
+      }
+    }
+
+    //Reset
+    //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:ge; 6:dchan; 7:RoCE)
+    //Arg1 : port
+    //Arg2 : 0 disable, 1 enable
+    Method(DRST, 3, Serialized)
+    {
+      Switch (ToInteger(Arg0))
+      {
+        //DSAF reset
+        case (0x1)
+        {
+          Store (Arg2, Local0)
+          If (LEqual (Local0, 0))
+          {
+            Store (0x1, DRTE)
+            Store (0x1, NRTE)
+            Sleep (10)
+            Store (0x1, RRTE)
+          }
+          Else
+          {
+            Store (0x1, DRTD)
+            Store (0x1, NRTD)
+            Sleep (10)
+            Store (0x1, RRTD)
+          }
+        }
+        //Reset PPE port
+        case (0x2)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          PRST (Local0, Local1)
+        }
+
+        //Reset XGE core
+        case (0x3)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XCRT (Local0, Local1)
+        }
+        //Reset XGE port
+        case (0x4)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XRST (Local0, Local1)
+        }
+
+        //Reset GE port
+        case (0x5)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          GRST (Local0, Local1)
+        }
+
+        //Reset DSAF Channels
+        case (0x6)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          DCRT (Local0, Local1)
+        }
+
+        //Reset RoCE
+        case (0x7)
+        {
+          // Discarding Arg1 as it is always 0
+          Store (Arg2, Local0)
+          RRST (Local0)
+        }
+      }
+    }
+
+    // _DSM Device Specific Method
+    //
+    // Arg0: UUID Unique function identifier
+    // Arg1: Integer Revision Level
+    // Arg2: Integer Function Index
+    //   0 : Return Supported Functions bit mask
+    //   1 : Reset Sequence
+    //    Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge; 6:dchan; 7:RoCE)
+    //    Arg3[1] : port index in dsaf
+    //    Arg3[2] : 0 reset, 1 cancle reset
+    //   2 : Set Serdes Loopback
+    //    Arg3[0] : port
+    //    Arg3[1] : 0 disable, 1 enable
+    //   3 : LED op set
+    //    Arg3[0] : op type
+    //    Arg3[1] : port
+    //    Arg3[2] : para
+    //   4 : Get port type (GE or XGE)
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 GE, 1 XGE
+    //   5 : Get sfp status
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 no sfp, 1 have sfp
+    // Arg3: Package Parameters
+    Method (_DSM, 4, Serialized)
+    {
+      If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+      {
+        If (LEqual (Arg1, 0x00))
+        {
+          Switch (ToInteger(Arg2))
+          {
+            case (0x0)
+            {
+              Return (Buffer () {0x3F})
+            }
+
+            //Reset Sequence
+            case (0x1)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              Store (DeRefOf (Index (Arg3, 2)), Local2)
+              DRST (Local0, Local1, Local2)
+            }
+
+            //Set Serdes Loopback
+            case (0x2)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              SRLP (Local0, Local1)
+            }
+
+            //LED op set
+            case (0x3)
+            {
+
+            }
+
+            // Get port type (GE or XGE)
+            case (0x4)
+            {
+              Store (0, Local1)
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              If (LLessEqual (Local0, 3))
+              {
+                // mac0: Hilink4 Lane0
+                // mac1: Hilink4 Lane1
+                // mac2: Hilink4 Lane2
+                // mac3: Hilink4 Lane3
+                Store (H4ST, Local1)
+              }
+              ElseIf (LLessEqual (Local0, 5))
+              {
+                // mac4: Hilink3 Lane2
+                // mac5: Hilink3 Lane3
+                Store (H3ST, Local1)
+              }
+
+              Return (Local1)
+            }
+
+            //Get sfp status
+            case (0x5)
+            {
+
+            }
+          }
+        }
+      }
+      Return (Buffer() {0x00})
+    }
+    Device (PRT0)
+    {
+      Name (_ADR, 0x0)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 0},
+                Package () {"media-type", "fiber"},
+                        }
+                })
+    }
+    Device (PRT1)
+    {
+      Name (_ADR, 0x1)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 1},
+                Package () {"media-type", "fiber"},
+                        }
+                })
+    }
+
+    Device (PRT2)
+    {
+      Name (_ADR, 0x2)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 2},
+                Package () {"media-type", "fiber"},
+                        }
+                })
+    }
+    Device (PRT3)
+    {
+      Name (_ADR, 0x3)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 3},
+                Package () {"media-type", "fiber"},
+                        }
+                })
+    }
+
+    Device (PRT4)
+    {
+      Name (_ADR, 0x4)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 4},
+                                Package () {"phy-mode", "sgmii"},
+                Package () {"phy-addr", 0},
+                Package () {"mdio-node", Package (){\_SB.MDIO}},
+                Package () {"media-type", "copper"},
+                        }
+                })
+    }
+    Device (PRT5)
+    {
+      Name (_ADR, 0x5)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 5},
+                                Package () {"phy-mode", "sgmii"},
+                Package () {"phy-addr", 1},
+                Package () {"mdio-node", Package (){\_SB.MDIO}},
+                Package () {"media-type", "copper"},
+                        }
+                })
+    }
+  }
+  Device (ETH4) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 4},
+      }
+    })
+  }
+  Device (ETH5) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 5},
+      }
+    })
+  }
+  Device (ETH0) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 0},
+      }
+    })
+  }
+  Device (ETH1) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 1},
+      }
+    })
+  }
+
+   Device (ETH2) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 2},
+      }
+    })
+  }
+  Device (ETH3) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF0}},
+        Package () {"port-idx-in-ae", 3},
+      }
+    })
+  }
+
+  Device (ROCE) {
+    Name(_HID, "HISI00D1")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"eth-handle", Package () {\_SB.ETH0, \_SB.ETH1, 0, 0, \_SB.ETH4, \_SB.ETH5}},
+        Package () {"dsaf-handle", Package (){\_SB.DSF0}},
+        Package () {"node-guid", Package () { 0x00, 0x9A, 0xCD, 0x00, 0x00, 0x01, 0x02, 0x03 }}, // 8-bytes
+        Package () {"interrupt-parent", Package() {\_SB.MBI9}},
+        Package () {"interrupt-names", Package() {"hns-roce-comp-0",
+                                                  "hns-roce-comp-1",
+                                                  "hns-roce-comp-2",
+                                                  "hns-roce-comp-3",
+                                                  "hns-roce-comp-4",
+                                                  "hns-roce-comp-5",
+                                                  "hns-roce-comp-6",
+                                                  "hns-roce-comp-7",
+                                                  "hns-roce-comp-8",
+                                                  "hns-roce-comp-9",
+                                                  "hns-roce-comp-10",
+                                                  "hns-roce-comp-11",
+                                                  "hns-roce-comp-12",
+                                                  "hns-roce-comp-13",
+                                                  "hns-roce-comp-14",
+                                                  "hns-roce-comp-15",
+                                                  "hns-roce-comp-16",
+                                                  "hns-roce-comp-17",
+                                                  "hns-roce-comp-18",
+                                                  "hns-roce-comp-19",
+                                                  "hns-roce-comp-20",
+                                                  "hns-roce-comp-21",
+                                                  "hns-roce-comp-22",
+                                                  "hns-roce-comp-23",
+                                                  "hns-roce-comp-24",
+                                                  "hns-roce-comp-25",
+                                                  "hns-roce-comp-26",
+                                                  "hns-roce-comp-27",
+                                                  "hns-roce-comp-28",
+                                                  "hns-roce-comp-29",
+                                                  "hns-roce-comp-30",
+                                                  "hns-roce-comp-31",
+                                                  "hns-roce-async",
+                                                  "hns-roce-common"}},
+      }
+    })
+    Name (_CRS, ResourceTemplate (){
+      Memory32Fixed (ReadWrite, 0xc4000000 , 0x100000)
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI9")
+        {
+          722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+          734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+          746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+        }
+   })
+ }
+
+/* for p1 */
+  Device (DSF1)
+  {
+
+    OperationRegion(H3SR, SystemMemory, 0x400C0000184, 4)
+    Field(H3SR, DWordAcc, NoLock, Preserve) {
+          H3ST, 1,
+          , 31,  //RESERVED
+        }
+    OperationRegion(H4SR, SystemMemory, 0x400C0000194, 4)
+    Field(H4SR, DWordAcc, NoLock, Preserve) {
+          H4ST, 1,
+          , 31,  //RESERVED
+        }
+    // DSAF RESET
+    OperationRegion(DRER, SystemMemory, 0x400C0000A00, 8)
+    Field(DRER, DWordAcc, NoLock, Preserve) {
+          DRTE, 1,
+          , 31,  //RESERVED
+          DRTD, 1,
+          , 31,  //RESERVED
+        }
+    // NT RESET
+    OperationRegion(NRER, SystemMemory, 0x400C0000A08, 8)
+    Field(NRER, DWordAcc, NoLock, Preserve) {
+          NRTE, 1,
+          , 31,  //RESERVED
+          NRTD, 1,
+          , 31,  //RESERVED
+        }
+    // XGE RESET
+    OperationRegion(XRER, SystemMemory, 0x400C0000A10, 8)
+    Field(XRER, DWordAcc, NoLock, Preserve) {
+          XRTE, 31,
+          , 1,    //RESERVED
+          XRTD, 31,
+          , 1,    //RESERVED
+        }
+
+    // GE RESET
+    OperationRegion(GRTR, SystemMemory, 0x400C0000A18, 16)
+    Field(GRTR, DWordAcc, NoLock, Preserve) {
+          GR0E, 30,
+          , 2,    //RESERVED
+          GR0D, 30,
+          , 2,    //RESERVED
+          GR1E, 18,
+          , 14,  //RESERVED
+          GR1D, 18,
+          , 14,  //RESERVED
+        }
+    // PPE RESET
+    OperationRegion(PRTR, SystemMemory, 0x400C0000A48, 8)
+    Field(PRTR, DWordAcc, NoLock, Preserve) {
+          PRTE, 10,
+          , 22,  //RESERVED
+          PRTD, 10,
+          , 22,  //RESERVED
+        }
+
+    // RCB PPE COM RESET
+    OperationRegion(RRTR, SystemMemory, 0x400C0000A88, 8)
+    Field(RRTR, DWordAcc, NoLock, Preserve) {
+          RRTE, 1,
+          , 31,  //RESERVED
+          RRTD, 1,
+          , 31,  //RESERVED
+        }
+
+    // RCB_2X COM RESET
+    OperationRegion(RBTR, SystemMemory, 0x400C0000AC0, 8)
+    Field(RBTR, DWordAcc, NoLock, Preserve) {
+          RBTE, 1,
+          , 31,  //RESERVED
+          RBTD, 1,
+          , 31,  //RESERVED
+        }
+
+    // Hilink access sel cfg reg
+    OperationRegion(HSER, SystemMemory, 0x400C2240008, 0x4)
+    Field(HSER, DWordAcc, NoLock, Preserve) {
+          HSEL, 2,  // hilink_access_sel & hilink_access_wr_pul
+          , 30,    // RESERVED
+        }
+
+    // Serdes
+    OperationRegion(H4LR, SystemMemory, 0x400C2208100, 0x1000)
+    Field(H4LR, DWordAcc, NoLock, Preserve) {
+          H4L0, 16,    // port0
+          , 16,    //RESERVED
+          Offset (0x400),
+          H4L1, 16,    // port1
+          , 16,    //RESERVED
+          Offset (0x800),
+          H4L2, 16,    // port2
+          , 16,    //RESERVED
+          Offset (0xc00),
+          H4L3, 16,    // port3
+          , 16,    //RESERVED
+        }
+    OperationRegion(H3LR, SystemMemory, 0x400C2208900, 0x800)
+    Field(H3LR, DWordAcc, NoLock, Preserve) {
+          H3L2, 16,    // port4
+          , 16,    //RESERVED
+          Offset (0x400),
+          H3L3, 16,    // port5
+          , 16,    //RESERVED
+        }
+
+                Name (_HID, "HISI00B2")
+                Name (_CCA, 1) // Cache-coherent controller
+                Name (_CRS, ResourceTemplate (){
+                  QwordMemory (
+                    ResourceProducer,
+                    PosDecode,
+                    MinFixed,
+                    MaxFixed,
+                    NonCacheable,
+                    ReadWrite,
+                    0x0, // Granularity
+                    0x400c5000000, // Min Base Address
+                    0x400c588ffff, // Max Base Address
+                    0x0, // Translate
+                    0x890000 // Length
+                  )
+                  QwordMemory (
+                    ResourceProducer,
+                    PosDecode,
+                    MinFixed,
+                    MaxFixed,
+                    NonCacheable,
+                    ReadWrite,
+                    0x0, // Granularity
+                    0x400c7000000, // Min Base Address
+                    0x400c705ffff, // Max Base Address
+                    0x0, // Translate
+                    0x60000 // Length
+                  )
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
+        {
+          576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+          589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+        }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
+        {
+          960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+          976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+          992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+          1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+          1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+          1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+          1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+          1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+          1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+          1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+          1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+          1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+        }
+      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI8")
+        {
+          1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+          1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+          1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+          1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+          1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+          1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+          1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+          1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+          1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+          1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+          1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+          1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+        }
+                })
+                Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"mode", "6port-16rss"},
+        Package () {"buf-size", 4096},
+        Package () {"desc-num", 1024},
+        Package () {"interrupt-parent", Package() {\_SB.MBI8}},
+                        }
+                })
+
+    //reset XGE port
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XRST, 2, Serialized) {
+      ShiftLeft (0x2082082, Arg0, Local0)
+      Or (Local0, 0x1, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset XGE core
+    //Arg0 : XGE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(XCRT, 2, Serialized) {
+      ShiftLeft (0x2080, Arg0, Local0)
+
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, XRTE)
+      } Else  {
+        Store(Local0, XRTD)
+      }
+    }
+
+    //reset GE port
+    //Arg0 : GE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(GRST, 2, Serialized) {
+      If (LLessEqual (Arg0, 5)) {
+        //Service port
+        ShiftLeft (0x2082082, Arg0, Local0)
+        ShiftLeft (0x1, Arg0, Local1)
+
+        If (LEqual (Arg1, 0)) {
+          Store(Local1, GR1E)
+          Store(Local0, GR0E)
+        } Else  {
+          Store(Local0, GR0D)
+          Store(Local1, GR1D)
+        }
+      }
+    }
+
+    //reset PPE port
+    //Arg0 : PPE port index in dsaf
+    //Arg1 : 0 reset, 1 cancle reset
+    Method(PRST, 2, Serialized) {
+      ShiftLeft (0x1, Arg0, Local0)
+      If (LEqual (Arg1, 0)) {
+        Store(Local0, PRTE)
+      } Else  {
+        Store(Local0, PRTD)
+      }
+    }
+
+    // Set Serdes Loopback
+    //Arg0 : port
+    //Arg1 : 0 disable, 1 enable
+    Method(SRLP, 2, Serialized) {
+      ShiftLeft (Arg1, 10, Local0)
+      Switch (ToInteger(Arg0))
+      {
+        case (0x0){
+          Store (0, HSEL)
+          Store (H4L0, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L0)
+        }
+        case (0x1){
+          Store (0, HSEL)
+          Store (H4L1, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L1)
+        }
+        case (0x2){
+          Store (0, HSEL)
+          Store (H4L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L2)
+        }
+        case (0x3){
+          Store (0, HSEL)
+          Store (H4L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H4L3)
+        }
+        case (0x4){
+          Store (3, HSEL)
+          Store (H3L2, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L2)
+        }
+        case (0x5){
+          Store (3, HSEL)
+          Store (H3L3, Local1)
+          And (Local1, 0xfffffbff, Local1)
+          Or (Local0, Local1, Local0)
+          Store (Local0, H3L3)
+        }
+      }
+    }
+
+    //Reset
+    //Arg0 : reset type (1: dsaf; 2: ppe; 3:XGE core; 4:XGE; 5:G3)
+    //Arg1 : port
+    //Arg2 : 0 disable, 1 enable
+    Method(DRST, 3, Serialized)
+    {
+      Switch (ToInteger(Arg0))
+      {
+        //DSAF reset
+        case (0x1)
+        {
+          Store (Arg2, Local0)
+          If (LEqual (Local0, 0))
+          {
+            Store (0x1, DRTE)
+            Store (0x1, NRTE)
+            Sleep (10)
+            Store (0x1, RRTE)
+            Store (0x1, RBTE)
+          }
+          Else
+          {
+            Store (0x1, DRTD)
+            Store (0x1, NRTD)
+            Sleep (10)
+            Store (0x1, RRTD)
+            Store (0x1, RBTD)
+          }
+        }
+        //Reset PPE port
+        case (0x2)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          PRST (Local0, Local1)
+        }
+
+        //Reset XGE core
+        case (0x3)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XCRT (Local0, Local1)
+        }
+        //Reset XGE port
+        case (0x4)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          XRST (Local0, Local1)
+        }
+
+        //Reset GE port
+        case (0x5)
+        {
+          Store (Arg1, Local0)
+          Store (Arg2, Local1)
+          GRST (Local0, Local1)
+        }
+      }
+    }
+
+    // _DSM Device Specific Method
+    //
+    // Arg0: UUID Unique function identifier
+    // Arg1: Integer Revision Level
+    // Arg2: Integer Function Index
+    //   0 : Return Supported Functions bit mask
+    //   1 : Reset Sequence
+    //    Arg3[0] : reset type (1:dsaf; 2:ppe; 3:xge core; 4:xge; 5: ge)
+    //    Arg3[1] : port index in dsaf
+    //    Arg3[2] : 0 reset, 1 cancle reset
+    //   2 : Set Serdes Loopback
+    //    Arg3[0] : port
+    //    Arg3[1] : 0 disable, 1 enable
+    //   3 : LED op set
+    //    Arg3[0] : op type
+    //    Arg3[1] : port
+    //    Arg3[2] : para
+    //   4 : Get port type (GE or XGE)
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 GE, 1 XGE
+    //   5 : Get sfp status
+    //    Arg3[0] : port index in dsaf
+    //    Return : 0 no sfp, 1 have sfp
+    // Arg3: Package Parameters
+    Method (_DSM, 4, Serialized)
+    {
+      If (LEqual(Arg0,ToUUID("1A85AA1A-E293-415E-8E28-8D690A0F820A")))
+      {
+        If (LEqual (Arg1, 0x00))
+        {
+          Switch (ToInteger(Arg2))
+          {
+            case (0x0)
+            {
+              Return (Buffer () {0x3F})
+            }
+
+            //Reset Sequence
+            case (0x1)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              Store (DeRefOf (Index (Arg3, 2)), Local2)
+              DRST (Local0, Local1, Local2)
+            }
+
+            //Set Serdes Loopback
+            case (0x2)
+            {
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              Store (DeRefOf (Index (Arg3, 1)), Local1)
+              SRLP (Local0, Local1)
+            }
+
+            //LED op set
+            case (0x3)
+            {
+
+            }
+
+            // Get port type (GE or XGE)
+            case (0x4)
+            {
+              Store (0, Local1)
+              Store (DeRefOf (Index (Arg3, 0)), Local0)
+              If (LLessEqual (Local0, 3))
+              {
+                // mac0: Hilink4 Lane0
+                // mac1: Hilink4 Lane1
+                // mac2: Hilink4 Lane2
+                // mac3: Hilink4 Lane3
+                Store (H4ST, Local1)
+              }
+              ElseIf (LLessEqual (Local0, 5))
+              {
+                // mac4: Hilink3 Lane2
+                // mac5: Hilink3 Lane3
+                Store (H3ST, Local1)
+              }
+
+              Return (Local1)
+            }
+
+            //Get sfp status
+            case (0x5)
+            {
+
+            }
+          }
+        }
+      }
+      Return (Buffer() {0x00})
+    }
+
+    Device (PRT6)
+    {
+      Name (_ADR, 0x6)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 0},
+                Package () {"media-type", "fiber"},
+                        }
+                })
+    }
+   Device (PRT7)
+    {
+      Name (_ADR, 0x7)
+      Name (_DSD, Package () {
+                        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+            Package () {
+                Package () {"reg", 1},
+                Package () {"media-type", "fiber"},
+                        }
+                })
+    }
+  }
+
+  Device (ETH6) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF1}},
+        Package () {"port-idx-in-ae", 0},
+      }
+    })
+  }
+  Device (ETH7) {
+    Name(_HID, "HISI00C2")
+    Name (_CCA, 1) // Cache-coherent controller
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"local-mac-address", Package () { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }}, // 6-bytes
+        Package () {"ae-handle", Package (){\_SB.DSF1}},
+        Package () {"port-idx-in-ae", 1},
+      }
+    })
+  }
+
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl
new file mode 100644
index 0000000..6850f68
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05I2c.asl
@@ -0,0 +1,58 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+Scope(_SB)
+{
+  Device(I2C0) {
+    Name(_HID, "APMC0D0F")
+    Name(_CID, "APMC0D0F")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xd00e0000, 0x10000)
+      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI6") { 705 }
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"clock-frequency", 100000},
+        Package () {"i2c-sda-falling-time-ns", 913},
+        Package () {"i2c-scl-falling-time-ns", 303},
+        Package () {"i2c-sda-hold-time-ns", 0x9c2},
+        Package () {"interrut-parent",Package() {\_SB.MBI6}},
+      }
+    })
+  }
+
+  Device(I2C2) {
+    Name(_HID, "APMC0D0F")
+    Name(_CID, "APMC0D0F")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xd0100000, 0x10000)
+      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI7") { 707 }
+    })
+    Name (_DSD, Package () {
+      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+      Package () {
+        Package () {"clock-frequency", 100000},
+        Package () {"i2c-sda-falling-time-ns", 913},
+        Package () {"i2c-scl-falling-time-ns", 303},
+        Package () {"i2c-sda-hold-time-ns", 0x9c2},
+        Package () {"interrut-parent",Package() {\_SB.MBI6}},
+      }
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl
new file mode 100644
index 0000000..5b08119
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Mbig.asl
@@ -0,0 +1,460 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+  // Mbi-gen peri a subsys
+  /*Device(MBI0) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0x40080000, 0x10000)
+    })
+
+  Name(_PRS, ResourceTemplate() {
+    Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) { 807 }
+  })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 2}
+        }
+   })
+  }*/
+
+  // Mbi-gen peri b intc
+  Device(MBI0) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0x60080000, 0x10000)
+    })
+
+  Name(_PRS, ResourceTemplate() {
+    Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,) { 807 }
+  })
+
+  Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 1}
+        }
+   })
+  }
+
+  Device(MBI1) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+
+  Name(_PRS, ResourceTemplate() {
+    Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+        {
+          576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+          589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+        }
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+        {
+          960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+          976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+          992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+          1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+          1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+          1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+          1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+          1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+          1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+          1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+          1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+          1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+        }
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+        {
+          1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+          1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+          1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+          1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+          1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+          1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+          1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+          1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+          1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+          1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+          1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+          1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+        }
+  })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 409}
+        }
+   })
+  }
+
+  // Mbi-gen sas0
+  Device(MBI2) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+
+  Name(_PRS, ResourceTemplate() {
+        Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
+                  {
+      64,65,66,67,68,
+      69,70,71,72,73,
+      75,76,77,78,79,
+      80,81,82,83,84,
+      85,86,87,88,89,
+      90,91,92,93,94,
+      95,96,97,98,99,
+      100,101,102,103,104,
+      105,106,107,108,109,
+      110,111,112,113,114,
+      115,116,117,118,119,
+      120,121,122,123,124,
+      125,126,127,128,129,
+      130,131,132,133,134,
+      135,136,137,138,139,
+      140,141,142,143,144,
+      145,146,147,148,149,
+      150,151,152,153,154,
+      155,156,157,158,159,
+      160,
+      }
+
+        Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0,,)
+                  {
+      601,602,603,604,
+      605,606,607,608,609,
+      610,611,612,613,614,
+      615,616,617,618,619,
+      620,621,622,623,624,
+      625,626,627,628,629,
+      630,631,632,
+      }
+          })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 128}
+        }
+   })
+  }
+
+ Device(MBI3) {          // Mbi-gen sas1 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+    })
+
+  Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
+                  {
+      64,65,66,67,68,
+      69,70,71,72,73,
+      75,76,77,78,79,
+      80,81,82,83,84,
+      85,86,87,88,89,
+      90,91,92,93,94,
+      95,96,97,98,99,
+      100,101,102,103,104,
+      105,106,107,108,109,
+      110,111,112,113,114,
+      115,116,117,118,119,
+      120,121,122,123,124,
+      125,126,127,128,129,
+      130,131,132,133,134,
+      135,136,137,138,139,
+      140,141,142,143,144,
+      145,146,147,148,149,
+      150,151,152,153,154,
+      155,156,157,158,159,
+      160,
+      }
+
+        Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+                  {
+         576,577,578,579,580,
+      581,582,583,584,585,
+      586,587,588,589,590,
+      591,592,593,594,595,
+      596,597,598,599,600,
+      601,602,603,604,605,
+      606,607,
+      }
+          })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 128}
+        }
+   })
+  }
+ Device(MBI4) {          // Mbi-gen sas2 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+    })
+
+  Name(_PRS, ResourceTemplate() {
+      Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0, ,)
+                  {
+      192,193,194,195,196,
+      197,198,199,200,201,
+      202,203,204,205,206,
+      207,208,209,210,211,
+      212,213,214,215,216,
+      217,218,219,220,221,
+      222,223,224,225,226,
+      227,228,229,230,231,
+      232,233,234,235,236,
+      237,238,239,240,241,
+      242,243,244,245,246,
+      247,248,249,250,251,
+      252,253,254,255,256,
+      257,258,259,260,261,
+      262,263,264,265,266,
+      267,268,269,270,271,
+      272,273,274,275,276,
+      277,278,279,280,281,
+      282,283,284,285,286,
+      287,
+      }
+
+                  Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+                  {
+      608,609,610,611,
+      612,613,614,615,616,
+      617,618,619,620,621,
+      622,623,624,625,626,
+      627,628,629,630,631,
+      632,633,634,635,636,
+      637,638,639,
+      }
+          })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 128}
+        }
+   })
+  }
+
+  Device(MBI5) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xa0080000, 0x10000)
+    })
+
+  Name(_PRS, ResourceTemplate() {
+    Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) {640,641,}
+  })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 2}
+        }
+   })
+  }
+
+  Device(MBI6) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xd0080000, 0x10000)
+    })
+
+  Name(_PRS, ResourceTemplate() {
+    Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 705 }
+  })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 1}
+        }
+   })
+  }
+
+  Device(MBI7) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xd0080000, 0x10000)
+    })
+
+  Name(_PRS, ResourceTemplate() {
+    Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive, 0,,) { 707 }
+  })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 1}
+        }
+   })
+  }
+
+  Device(MBI8) {
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+     //Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+         QwordMemory (
+  ResourceProducer,
+  PosDecode,
+  MinFixed,
+  MaxFixed,
+  NonCacheable,
+  ReadWrite,
+  0x0, // Granularity
+  0x400c0080000, // Min Base Address
+  0x400c008ffff, // Max Base Address
+  0x0, // Translate
+  0x10000 // Length
+  )
+
+    })
+
+  Name(_PRS, ResourceTemplate() {
+    Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+        {
+          576, 577, 578, 579, 580, 581, 582, 583, 584, 585, 586, 587, 588,
+          589, 590, 591, 592, 593, 594, 595, 596, 597, 598, 599, 600,
+        }
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+        {
+          960, 961, 962, 963, 964, 965, 966, 967, 968, 969, 970, 971, 972, 973, 974, 975,
+          976, 977, 978, 979, 980, 981, 982, 983, 984, 985, 986, 987, 988, 989, 990, 991,
+          992, 993, 994, 995, 996, 997, 998, 999, 1000, 1001, 1002, 1003, 1004, 1005, 1006, 1007,
+          1008, 1009, 1010, 1011, 1012, 1013, 1014, 1015, 1016, 1017, 1018, 1019, 1020, 1021, 1022, 1023,
+          1024, 1025, 1026, 1027, 1028, 1029, 1030, 1031, 1032, 1033, 1034, 1035, 1036, 1037, 1038, 1039,
+          1040, 1041, 1042, 1043, 1044, 1045, 1046, 1047, 1048, 1049, 1050, 1051, 1052, 1053, 1054, 1055,
+          1056, 1057, 1058, 1059, 1060, 1061, 1062, 1063, 1064, 1065, 1066, 1067, 1068, 1069, 1070, 1071,
+          1072, 1073, 1074, 1075, 1076, 1077, 1078, 1079, 1080, 1081, 1082, 1083, 1084, 1085, 1086, 1087,
+          1088, 1089, 1090, 1091, 1092, 1093, 1094, 1095, 1096, 1097, 1098, 1099, 1100, 1101, 1102, 1103,
+          1104, 1105, 1106, 1107, 1108, 1109, 1110, 1111, 1112, 1113, 1114, 1115, 1116, 1117, 1118, 1119,
+          1120, 1121, 1122, 1123, 1124, 1125, 1126, 1127, 1128, 1129, 1130, 1131, 1132, 1133, 1134, 1135,
+          1136, 1137, 1138, 1139, 1140, 1141, 1142, 1143, 1144, 1145, 1146, 1147, 1148, 1149, 1150, 1151,
+        }
+      Interrupt (ResourceProducer, Edge, ActiveHigh, Exclusive, 0, ,)
+        {
+          1152, 1153, 1154, 1155, 1156, 1157, 1158, 1159, 1160, 1161, 1162, 1163, 1164, 1165, 1166, 1167,
+          1168, 1169, 1170, 1171, 1172, 1173, 1174, 1175, 1176, 1177, 1178, 1179, 1180, 1181, 1182, 1183,
+          1184, 1185, 1186, 1187, 1188, 1189, 1190, 1191, 1192, 1193, 1194, 1195, 1196, 1197, 1198, 1199,
+          1200, 1201, 1202, 1203, 1204, 1205, 1206, 1207, 1208, 1209, 1210, 1211, 1212, 1213, 1214, 1215,
+          1216, 1217, 1218, 1219, 1220, 1221, 1222, 1223, 1224, 1225, 1226, 1227, 1228, 1229, 1230, 1231,
+          1232, 1233, 1234, 1235, 1236, 1237, 1238, 1239, 1240, 1241, 1242, 1243, 1244, 1245, 1246, 1247,
+          1248, 1249, 1250, 1251, 1252, 1253, 1254, 1255, 1256, 1257, 1258, 1259, 1260, 1261, 1262, 1263,
+          1264, 1265, 1266, 1267, 1268, 1269, 1270, 1271, 1272, 1273, 1274, 1275, 1276, 1277, 1278, 1279,
+          1280, 1281, 1282, 1283, 1284, 1285, 1286, 1287, 1288, 1289, 1290, 1291, 1292, 1293, 1294, 1295,
+          1296, 1297, 1298, 1299, 1300, 1301, 1302, 1303, 1304, 1305, 1306, 1307, 1308, 1309, 1310, 1311,
+          1312, 1313, 1314, 1315, 1316, 1317, 1318, 1319, 1320, 1321, 1322, 1323, 1324, 1325, 1326, 1327,
+          1328, 1329, 1330, 1331, 1332, 1333, 1334, 1335, 1336, 1337, 1338, 1339, 1340, 1341, 1342, 1343,
+        }
+  })
+
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 409}
+        }
+   })
+  }
+/*
+  Device(MBI4) {          // Mbi-gen dsa1 dbg0 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 9}
+        }
+   })
+  }
+
+  Device(MBI5) {          // Mbi-gen dsa2 dbg1 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 9}
+        }
+   })
+  }
+
+  Device(MBI6) {          // Mbi-gen dsa sas0 intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+   Name(_DSD, Package () {
+        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+        Package ()
+        {
+          Package () {"num-pins", 128}
+        }
+   })
+  }
+*/
+  Device(MBI9) {          // Mbi-gen roce intc
+    Name(_HID, "HISI0152")
+    Name(_CID, "MBIGen")
+    Name(_CRS, ResourceTemplate() {
+      Memory32Fixed(ReadWrite, 0xc0080000, 0x10000)
+    })
+  Name (_PRS, ResourceTemplate (){
+       Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive,,,)
+         {
+           722, 723, 724, 725, 726, 727, 728, 729, 730, 731, 732, 733,
+           734, 735, 736, 737, 738, 739, 740, 741, 742, 743, 744, 745,
+           746, 747, 748, 749, 750, 751, 752, 753, 785, 754,
+         }
+    })
+  }
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
new file mode 100644
index 0000000..ff3b5f5
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Pci.asl
@@ -0,0 +1,436 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+  // 1P NA PCIe2
+  Device (PCI2)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 2) // Segment of this Root complex
+    Name(_BBN, 0x80) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x80, // AddressMinimum - Minimum Bus Number
+          0x87, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x8 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xa8800000, // Min Base Address
+          0xaffeffff, // Max Base Address
+          0x0, // Translate
+          0x77f0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0xafff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+
+  } // Device(PCI2)
+  // 1p NB PCIe0
+  Device (PCI4)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 4) // Segment of this Root complex
+    Name(_BBN, 0x88) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x88, // AddressMinimum - Minimum Bus Number
+          0x8f, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x8 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xa9000000, // Min Base Address
+          0xabfeffff, // Max Base Address
+          0x800000000, // Translate
+          0x2ff0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x8abff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0x0)
+    }
+
+  } // Device(PCI4)
+
+  // 1P NB PCI1
+  Device (PCI5)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 5) // Segment of this Root complex
+    Name(_BBN, 0x0) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x0, // AddressMinimum - Minimum Bus Number
+          0x7, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x8 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xb0800000, // Min Base Address
+          0xb7feffff, // Max Base Address
+          0x800000000, // Translate
+          0x77f0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x8b7ff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0x0)
+    }
+  } // Device(PCI5)
+
+  // 1P NB PCIe2
+  Device (PCI6)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0x6) // Segment of this Root complex
+    Name(_BBN, 0xc0) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0xc0, // AddressMinimum - Minimum Bus Number
+          0xc7, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x8 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xac900000, // Min Base Address
+          0xaffeffff, // Max Base Address
+          0x800000000, // Translate
+          0x36f0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x8afff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0x0)
+    }
+  } // Device(PCI6)
+  // 1P NB PCIe3
+  Device (PCI7)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0x7) // Segment of this Root complex
+    Name(_BBN, 0x90) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x90, // AddressMinimum - Minimum Bus Number
+          0x97, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x8 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0xb9800000, // Min Base Address
+          0xbffeffff, // Max Base Address
+          0x800000000, // Translate
+          0x67f0000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x8bfff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0x0)
+    }
+  } // Device(PCI7)
+  // 2P NA PCIe2
+  Device (PCIa)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0xa) // Segment of this Root complex
+    Name(_BBN, 0x10) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x10, // AddressMinimum - Minimum Bus Number
+          0x1f, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x10 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x20000000, // Min Base Address
+          0xefffffff, // Max Base Address
+          0x65000000000, // Translate
+          0xd0000000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x67fffff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0xf)
+    }
+  } // Device(PCIa)
+  // 2P NB PCIe0
+  Device (PCIc)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0xc) // Segment of this Root complex
+    Name(_BBN, 0x20) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x20, // AddressMinimum - Minimum Bus Number
+          0x2f, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x10 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x30000000, // Min Base Address
+          0xefffffff, // Max Base Address
+          0x75000000000, // Translate
+          0xc0000000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x77fffff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0x0)
+    }
+  } // Device(PCIc)
+
+  //2P NB PCIe1
+  Device (PCId)
+  {
+    Name (_HID, "PNP0A08") // PCI Express Root Bridge
+    Name (_CID, "PNP0A03") // Compatible PCI Root Bridge
+    Name(_SEG, 0xd) // Segment of this Root complex
+    Name(_BBN, 0x30) // Base Bus Number
+    Name(_CCA, 1)
+    Method (_CRS, 0, Serialized) { // Root complex resources
+      Name (RBUF, ResourceTemplate () {
+        WordBusNumber ( // Bus numbers assigned to this root
+          ResourceProducer, MinFixed, MaxFixed, PosDecode,
+          0, // AddressGranularity
+          0x30, // AddressMinimum - Minimum Bus Number
+          0x3f, // AddressMaximum - Maximum Bus Number
+          0, // AddressTranslation - Set to 0
+          0x10 // RangeLength - Number of Busses
+        )
+        QWordMemory ( // 64-bit BAR Windows
+          ResourceProducer,
+          PosDecode,
+          MinFixed,
+          MaxFixed,
+          Cacheable,
+          ReadWrite,
+          0x0, // Granularity
+          0x40000000, // Min Base Address
+          0xefffffff, // Max Base Address
+          0x79000000000, // Translate
+          0xB0000000 // Length
+        )
+        QWordIO (
+          ResourceProducer,
+          MinFixed,
+          MaxFixed,
+          PosDecode,
+          EntireRange,
+          0x0, // Granularity
+          0x0, // Min Base Address
+          0xffff, // Max Base Address
+          0x7bfffff0000, // Translate
+          0x10000 // Length
+        )
+      }) // Name(RBUF)
+      Return (RBUF)
+    } // Method(_CRS)
+    Method (_STA, 0x0, NotSerialized)
+    {
+      Return (0x0)
+    }
+  } // Device(PCId)
+}
+
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
new file mode 100644
index 0000000..546595b
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Sas.asl
@@ -0,0 +1,247 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+Scope(_SB)
+{
+    Device(SAS0) {
+          Name(_HID, "HISI0162")
+    Name(_CCA, 1)
+          Name(_CRS, ResourceTemplate() {
+                  Memory32Fixed(ReadWrite, 0xC3000000, 0x10000)
+                  Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+                  {
+      64,65,66,67,68,
+      69,70,71,72,73,
+      75,76,77,78,79,
+      80,81,82,83,84,
+      85,86,87,88,89,
+      90,91,92,93,94,
+      95,96,97,98,99,
+      100,101,102,103,104,
+      105,106,107,108,109,
+      110,111,112,113,114,
+      115,116,117,118,119,
+      120,121,122,123,124,
+      125,126,127,128,129,
+      130,131,132,133,134,
+      135,136,137,138,139,
+      140,141,142,143,144,
+      145,146,147,148,149,
+      150,151,152,153,154,
+      155,156,157,158,159,
+      160,
+      }
+
+                  Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
+                  {
+      601,602,603,604,
+      605,606,607,608,609,
+      610,611,612,613,614,
+      615,616,617,618,619,
+      620,621,622,623,624,
+      625,626,627,628,629,
+      630,631,632,
+      }
+          })
+
+          Name (_DSD, Package () {
+              ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+              Package () {
+                  Package () {"interrupt-parent",Package() {\_SB.MBI2}},
+      Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 0x00}},
+      Package () {"queue-count", 16},
+      Package () {"phy-count", 8},
+              }
+          })
+
+    OperationRegion (CTL, SystemMemory, 0xC0000000, 0x10000)
+    Field (CTL, AnyAcc, NoLock, Preserve)
+    {
+      Offset (0x338),
+      CLK, 32,
+      CLKD, 32,
+      Offset (0xa60),
+      RST, 32,
+      DRST, 32,
+      Offset (0x5a30),
+      STS, 32,
+    }
+
+    Method (_RST, 0x0, Serialized)
+    {
+      Store(0x7ffff, RST)
+      Store(0x7ffff, CLKD)
+      Sleep(1)
+      Store(0x7ffff, DRST)
+      Store(0x7ffff, CLK)
+      Sleep(1)
+    }
+    }
+
+    Device(SAS1) {
+          Name(_HID, "HISI0162")
+    Name(_CCA, 1)
+          Name(_CRS, ResourceTemplate() {
+                  Memory32Fixed(ReadWrite, 0xA2000000, 0x10000)
+
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+                  {
+      64,65,66,67,68,
+      69,70,71,72,73,
+      75,76,77,78,79,
+      80,81,82,83,84,
+      85,86,87,88,89,
+      90,91,92,93,94,
+      95,96,97,98,99,
+      100,101,102,103,104,
+      105,106,107,108,109,
+      110,111,112,113,114,
+      115,116,117,118,119,
+      120,121,122,123,124,
+      125,126,127,128,129,
+      130,131,132,133,134,
+      135,136,137,138,139,
+      140,141,142,143,144,
+      145,146,147,148,149,
+      150,151,152,153,154,
+      155,156,157,158,159,
+      160,
+      }
+
+                  Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
+                  {
+         576,577,578,579,580,
+      581,582,583,584,585,
+      586,587,588,589,590,
+      591,592,593,594,595,
+      596,597,598,599,600,
+      601,602,603,604,605,
+      606,607,
+      }
+          })
+
+          Name (_DSD, Package () {
+              ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+              Package () {
+                  Package () {"interrupt-parent",Package() {\_SB.MBI3}},
+                  Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+                  Package () {"queue-count", 16},
+                  Package () {"phy-count", 8},
+                  Package () {"hip06-sas-v2-quirk-amt", 1},
+              }
+          })
+
+    OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
+    Field (CTL, AnyAcc, NoLock, Preserve)
+    {
+      Offset (0x318),
+      CLK, 32,
+      CLKD, 32,
+      Offset (0xa18),
+      RST, 32,
+      DRST, 32,
+      Offset (0x5a0c),
+      STS, 32,
+    }
+
+    Method (_RST, 0x0, Serialized)
+    {
+      Store(0x7ffff, RST)
+      Store(0x7ffff, CLKD)
+      Sleep(1)
+      Store(0x7ffff, DRST)
+      Store(0x7ffff, CLK)
+      Sleep(1)
+    }
+    }
+
+    Device(SAS2) {
+          Name(_HID, "HISI0162")
+    Name(_CCA, 1)
+          Name(_CRS, ResourceTemplate() {
+                  Memory32Fixed(ReadWrite, 0xA3000000, 0x10000)
+
+      Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
+                  {
+      192,193,194,195,196,
+      197,198,199,200,201,
+      202,203,204,205,206,
+      207,208,209,210,211,
+      212,213,214,215,216,
+      217,218,219,220,221,
+      222,223,224,225,226,
+      227,228,229,230,231,
+      232,233,234,235,236,
+      237,238,239,240,241,
+      242,243,244,245,246,
+      247,248,249,250,251,
+      252,253,254,255,256,
+      257,258,259,260,261,
+      262,263,264,265,266,
+      267,268,269,270,271,
+      272,273,274,275,276,
+      277,278,279,280,281,
+      282,283,284,285,286,
+      287,
+      }
+
+                  Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
+                  {
+      608,609,610,611,
+      612,613,614,615,616,
+      617,618,619,620,621,
+      622,623,624,625,626,
+      627,628,629,630,631,
+      632,633,634,635,636,
+      637,638,639,
+      }
+          })
+
+          Name (_DSD, Package () {
+              ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+              Package () {
+                  Package () {"interrupt-parent",Package() {\_SB.MBI4}},
+      Package (2) {"sas-addr", Package() {50, 01, 88, 20, 16, 00, 00, 00}},
+      Package () {"queue-count", 16},
+      Package () {"phy-count", 8},
+              }
+          })
+
+    OperationRegion (CTL, SystemMemory, 0xA0000000, 0x10000)
+    Field (CTL, AnyAcc, NoLock, Preserve)
+    {
+      Offset (0x3a8),
+      CLK, 32,
+      CLKD, 32,
+      Offset (0xae0),
+      RST, 32,
+      DRST, 32,
+      Offset (0x5a70),
+      STS, 32,
+    }
+
+    Method (_RST, 0x0, Serialized)
+    {
+      Store(0x7ffff, RST)
+      Store(0x7ffff, CLKD)
+      Sleep(1)
+      Store(0x7ffff, DRST)
+      Store(0x7ffff, CLK)
+      Sleep(1)
+    }
+    }
+
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl
new file mode 100644
index 0000000..ae494a0
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/D05Usb.asl
@@ -0,0 +1,136 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+//#include "ArmPlatform.h"
+Scope(_SB)
+{
+  Device (USB0)
+        {
+            Name (_HID, "PNP0D20")  // _HID: Hardware ID
+            Name (_CID, "HISI0D2" /* EHCI USB Controller without debug */)  // _CID: Compatible ID
+            Name (_CCA, One)  // _CCA: Cache Coherency Attribute
+            Method (_CRS, 0, Serialized)  // _CRS: Current Resource Settings
+            {
+                Name (RBUF, ResourceTemplate ()
+                {
+                    Memory32Fixed (ReadWrite,
+                        0xa7020000,         // Address Base
+                        0x00010000,         // Address Length
+                        )
+                    Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, 0, "\\_SB.MBI5")
+                    {
+                        641,
+                    }
+                })
+                Return (RBUF) /* \_SB_.USB0._CRS.RBUF */
+            }
+
+     Name (_DSD, Package () {
+              ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
+              Package ()
+              {
+                  Package () {"interrupt-parent",Package() {\_SB.MBI5}}
+              }
+     })
+
+            Device (RHUB)
+            {
+                Name (_ADR, Zero)  // _ADR: Address
+                Device (PRT1)
+                {
+                    Name (_ADR, One)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        0xFF,
+                        Zero,
+                        Zero,
+                        Zero
+                    })
+                    Name (_PLD, Package (0x01)  // _PLD: Physical Location of Device
+                    {
+                        ToPLD (
+                            PLD_Revision       = 0x1,
+                            PLD_IgnoreColor    = 0x1,
+                            PLD_Red            = 0x0,
+                            PLD_Green          = 0x0,
+                            PLD_Blue           = 0x0,
+                            PLD_Width          = 0x0,
+                            PLD_Height         = 0x0,
+                            PLD_UserVisible    = 0x1,
+                            PLD_Dock           = 0x0,
+                            PLD_Lid            = 0x0,
+                            PLD_Panel          = "UNKNOWN",
+                            PLD_VerticalPosition = "UPPER",
+                            PLD_HorizontalPosition = "LEFT",
+                            PLD_Shape          = "UNKNOWN",
+                            PLD_GroupOrientation = 0x0,
+                            PLD_GroupToken     = 0x0,
+                            PLD_GroupPosition  = 0x0,
+                            PLD_Bay            = 0x0,
+                            PLD_Ejectable      = 0x0,
+                            PLD_EjectRequired  = 0x0,
+                            PLD_CabinetNumber  = 0x0,
+                            PLD_CardCageNumber = 0x0,
+                            PLD_Reference      = 0x0,
+                            PLD_Rotation       = 0x0,
+                            PLD_Order          = 0x0,
+                            PLD_VerticalOffset = 0x0,
+                            PLD_HorizontalOffset = 0x0)
+
+                    })
+                }
+
+                Device (PRT2)
+                {
+                    Name (_ADR, 0x02)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        Zero,
+                        0xFF,
+                        Zero,
+                        Zero
+                    })
+                }
+
+                Device (PRT3)
+                {
+                    Name (_ADR, 0x03)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        Zero,
+                        0xFF,
+                        Zero,
+                        Zero
+                    })
+                }
+
+                Device (PRT4)
+                {
+                    Name (_ADR, 0x04)  // _ADR: Address
+                    Name (_UPC, Package (0x04)  // _UPC: USB Port Capabilities
+                    {
+                        Zero,
+                        0xFF,
+                        Zero,
+                        Zero
+                    })
+                }
+            }
+        }
+}
+
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl
new file mode 100644
index 0000000..c0418bb
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/DsdtHi1616.asl
@@ -0,0 +1,31 @@
+/** @file
+  Differentiated System Description Table Fields (DSDT)
+
+  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
+  Copyright (c) 2015, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
+    This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+
+**/
+
+#include "Hi1616Platform.h"
+
+DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI  ", "HIP07   ", EFI_ACPI_ARM_OEM_REVISION) {
+     //include ("Lpc.asl")
+     include ("D05Mbig.asl")
+     include ("Com.asl")
+     include ("CPU.asl")
+     include ("D05I2c.asl")
+     include ("D05Usb.asl")
+     include ("D05Hns.asl")
+     include ("D05Sas.asl")
+     include ("D05Pci.asl")
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl
new file mode 100644
index 0000000..0965afc
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Dsdt/Lpc.asl
@@ -0,0 +1,25 @@
+/** @file
+*
+*  Copyright (c) 2016 Hisilicon Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+//
+// LPC
+//
+
+Device (LPC0)
+{
+  Name(_HID, "HISI0191")  // HiSi LPC
+  Name (_CRS, ResourceTemplate () {
+    Memory32Fixed (ReadWrite, 0xa01b0000, 0x1000)
+  })
+}
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc
new file mode 100644
index 0000000..72cc66c
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Facs.aslc
@@ -0,0 +1,67 @@
+/** @file
+*  Firmware ACPI Control Structure (FACS)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
+  EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32  Signature
+  sizeof (EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE),  // UINT32  Length
+  0xA152,                                                 // UINT32  HardwareSignature
+  0,                                                      // UINT32  FirmwareWakingVector
+  0,                                                      // UINT32  GlobalLock
+  0,                                                      // UINT32  Flags
+  0,                                                      // UINT64  XFirmwareWakingVector
+  EFI_ACPI_5_0_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,   // UINT8   Version;
+    { EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved0[0]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved0[1]
+      EFI_ACPI_RESERVED_BYTE },                           // UINT8   Reserved0[2]
+  0,                                                      // UINT32  OspmFlags  "Platform firmware must
+                                                          //                    initialize this field to zero."
+    { EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[0]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[1]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[2]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[3]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[4]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[5]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[6]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[7]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[8]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[9]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[10]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[11]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[12]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[13]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[14]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[15]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[16]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[17]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[18]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[19]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[20]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[21]
+      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[22]
+      EFI_ACPI_RESERVED_BYTE },                           // UINT8   Reserved1[23]
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Facs;
+
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc
new file mode 100644
index 0000000..33a79ab
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Fadt.aslc
@@ -0,0 +1,91 @@
+/** @file
+*  Fixed ACPI Description Table (FADT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1616Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <IndustryStandard/Acpi.h>
+
+EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
+  ARM_ACPI_HEADER (
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE,
+    EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
+  ),
+  0,                                                                        // UINT32     FirmwareCtrl
+  0,                                                                        // UINT32     Dsdt
+  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0
+  EFI_ACPI_5_0_PM_PROFILE_UNSPECIFIED,                                      // UINT8      PreferredPmProfile
+  0,                                                                        // UINT16     SciInt
+  0,                                                                        // UINT32     SmiCmd
+  0,                                                                        // UINT8      AcpiEnable
+  0,                                                                        // UINT8      AcpiDisable
+  0,                                                                        // UINT8      S4BiosReq
+  0,                                                                        // UINT8      PstateCnt
+  0,                                                                        // UINT32     Pm1aEvtBlk
+  0,                                                                        // UINT32     Pm1bEvtBlk
+  0,                                                                        // UINT32     Pm1aCntBlk
+  0,                                                                        // UINT32     Pm1bCntBlk
+  0,                                                                        // UINT32     Pm2CntBlk
+  0,                                                                        // UINT32     PmTmrBlk
+  0,                                                                        // UINT32     Gpe0Blk
+  0,                                                                        // UINT32     Gpe1Blk
+  0,                                                                        // UINT8      Pm1EvtLen
+  0,                                                                        // UINT8      Pm1CntLen
+  0,                                                                        // UINT8      Pm2CntLen
+  0,                                                                        // UINT8      PmTmrLen
+  0,                                                                        // UINT8      Gpe0BlkLen
+  0,                                                                        // UINT8      Gpe1BlkLen
+  0,                                                                        // UINT8      Gpe1Base
+  0,                                                                        // UINT8      CstCnt
+  0,                                                                        // UINT16     PLvl2Lat
+  0,                                                                        // UINT16     PLvl3Lat
+  0,                                                                        // UINT16     FlushSize
+  0,                                                                        // UINT16     FlushStride
+  0,                                                                        // UINT8      DutyOffset
+  0,                                                                        // UINT8      DutyWidth
+  0,                                                                        // UINT8      DayAlrm
+  0,                                                                        // UINT8      MonAlrm
+  0,                                                                        // UINT8      Century
+  0,                                                                        // UINT16     IaPcBootArch
+  0,                                                                        // UINT8      Reserved1
+  EFI_ACPI_5_0_HW_REDUCED_ACPI | EFI_ACPI_5_0_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  ResetReg
+  0,                                                                        // UINT8      ResetValue
+  EFI_ACPI_5_1_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags
+  EFI_ACPI_5_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,                 // UINT8      MinorRevision
+  0,                                                                        // UINT64     XFirmwareCtrl
+  0,                                                                        // UINT64     XDsdt
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk
+  NULL_GAS,                                                                 // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepControlReg
+  NULL_GAS                                                                  // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc
new file mode 100644
index 0000000..40183c8
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Gtdt.aslc
@@ -0,0 +1,96 @@
+/** @file
+*  Generic Timer Description Table (GTDT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1616Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+
+#define GTDT_GLOBAL_FLAGS_MAPPED      EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_MEMORY_MAPPED_BLOCK_PRESENT
+#define GTDT_GLOBAL_FLAGS_NOT_MAPPED  0
+#define GTDT_GLOBAL_FLAGS_EDGE        EFI_ACPI_5_0_GTDT_GLOBAL_FLAG_INTERRUPT_MODE
+#define GTDT_GLOBAL_FLAGS_LEVEL       0
+
+// Note: We could have a build flag that switches between memory mapped/non-memory mapped timer
+#ifdef SYSTEM_TIMER_BASE_ADDRESS
+  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+#else
+  #define GTDT_GLOBAL_FLAGS             (GTDT_GLOBAL_FLAGS_NOT_MAPPED | GTDT_GLOBAL_FLAGS_LEVEL)
+  #define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF
+#endif
+
+#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
+#define GTDT_TIMER_LEVEL_TRIGGERED  0
+#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_5_0_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
+#define GTDT_TIMER_ACTIVE_HIGH      0
+
+#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
+
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
+  EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdogs[HI1616_WATCHDOG_COUNT];
+} EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES;
+
+#pragma pack ()
+
+EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
+  {
+    ARM_ACPI_HEADER(
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLES,
+      EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
+    ),
+    SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
+    0,                                            // UINT32  Reserved
+    FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags
+    FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32  VirtualTimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  VirtualTimerFlags
+    FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV
+    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags
+    0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress
+#ifdef notyet
+    PV660_WATCHDOG_COUNT,                          // UINT32  PlatformTimerCount
+    sizeof (EFI_ACPI_5_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
+  },
+  {
+    EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+        //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 93, 0),
+        0, 0, 0, 0),
+    EFI_ACPI_5_1_SBSA_GENERIC_WATCHDOG_STRUCTURE_INIT(
+        //FixedPcdGet32 (PcdGenericWatchdogRefreshBase), FixedPcdGet32 (PcdGenericWatchdogControlBase), 94, EFI_ACPI_5_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER)
+        0, 0, 0, 0)
+  }
+#else /* !notyet */
+  0, 0
+  }
+#endif
+  };
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Gtdt;
+
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
new file mode 100644
index 0000000..3f214a4
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
@@ -0,0 +1,48 @@
+/** @file
+*
+*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+
+#ifndef _HI1610_PLATFORM_H_
+#define _HI1610_PLATFORM_H_
+
+//
+// ACPI table information used to initialize tables.
+//
+#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
+#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long
+#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
+#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32('I','N','T','L')
+#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+
+// A macro to initialise the common header part of EFI ACPI tables as defined by
+// EFI_ACPI_DESCRIPTION_HEADER structure.
+#define ARM_ACPI_HEADER(Signature, Type, Revision) {              \
+    Signature,                      /* UINT32  Signature */       \
+    sizeof (Type),                  /* UINT32  Length */          \
+    Revision,                       /* UINT8   Revision */        \
+    0,                              /* UINT8   Checksum */        \
+    { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
+    EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+    EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
+    EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
+    EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+  }
+
+#define HI1616_WATCHDOG_COUNT  2
+
+#endif
diff --git a/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
new file mode 100644
index 0000000..fd85f0d
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/D05AcpiTables/MadtHi1616.aslc
@@ -0,0 +1,282 @@
+/** @file
+*  Multiple APIC Description Table (MADT)
+*
+*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
+*
+**/
+
+#include "Hi1616Platform.h"
+
+#include <Library/AcpiLib.h>
+#include <Library/ArmLib.h>
+#include <Library/PcdLib.h>
+#include <IndustryStandard/Acpi.h>
+#include <Library/AcpiNextLib.h>
+
+// Differs from Juno, we have another affinity level beyond cluster and core
+// 0x20000 is only for socket 0
+#define PLATFORM_GET_MPID_TA(ClusterId, CoreId)   (0x10000 | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TB(ClusterId, CoreId)   (0x30000 | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId)   (0x50000 | ((ClusterId) << 8) | (CoreId))
+#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId)   (0x70000 | ((ClusterId) << 8) | (CoreId))
+
+//
+// Multiple APIC Description Table
+//
+#pragma pack (1)
+
+typedef struct {
+  EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
+  EFI_ACPI_5_1_GIC_STRUCTURE                            GicInterfaces[64];
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
+  EFI_ACPI_6_0_GIC_ITS_STRUCTURE                      GicITS[8];
+} EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE;
+
+#pragma pack ()
+
+EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
+  {
+    ARM_ACPI_HEADER (
+      EFI_ACPI_1_0_APIC_SIGNATURE,
+      EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE,
+      EFI_ACPI_1_0_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
+    ),
+    //
+    // MADT specific fields
+    //
+    0, // LocalApicAddress
+    0, // Flags
+  },
+  {
+    // Format: EFI_ACPI_5_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
+    //                                          GsivId, GicRBase, Mpidr)
+    // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
+    //       ACPI v5.1).
+    //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
+    //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        0, 0, PLATFORM_GET_MPID_TA(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x100000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        1, 1, PLATFORM_GET_MPID_TA(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x140000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        2, 2, PLATFORM_GET_MPID_TA(0, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x180000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        3, 3, PLATFORM_GET_MPID_TA(0, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x1C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        4, 4, PLATFORM_GET_MPID_TA(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x200000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        5, 5, PLATFORM_GET_MPID_TA(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x240000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        6, 6, PLATFORM_GET_MPID_TA(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x280000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        7, 7, PLATFORM_GET_MPID_TA(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x2C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        8, 8, PLATFORM_GET_MPID_TA(2, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x300000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        9, 9, PLATFORM_GET_MPID_TA(2, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x340000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        10, 10, PLATFORM_GET_MPID_TA(2, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x380000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        11, 11, PLATFORM_GET_MPID_TA(2, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x3C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        12, 12, PLATFORM_GET_MPID_TA(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x400000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        13, 13, PLATFORM_GET_MPID_TA(3, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x440000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        14, 14, PLATFORM_GET_MPID_TA(3, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x480000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        15, 15, PLATFORM_GET_MPID_TA(3, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x4C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        16, 16, PLATFORM_GET_MPID_TB(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x100000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        17, 17, PLATFORM_GET_MPID_TB(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x140000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        18, 18, PLATFORM_GET_MPID_TB(0, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x180000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        19, 19, PLATFORM_GET_MPID_TB(0, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x1C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        20, 20, PLATFORM_GET_MPID_TB(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x200000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        21, 21, PLATFORM_GET_MPID_TB(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000 + 0x20000000 + 0x240000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        22, 22, PLATFORM_GET_MPID_TB(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x280000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        23, 23, PLATFORM_GET_MPID_TB(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x2C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        24, 24, PLATFORM_GET_MPID_TB(2, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x300000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        25, 25, PLATFORM_GET_MPID_TB(2, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x340000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        26, 26, PLATFORM_GET_MPID_TB(2, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x380000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        27, 27, PLATFORM_GET_MPID_TB(2, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x3C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        28, 28, PLATFORM_GET_MPID_TB(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x400000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        29, 29, PLATFORM_GET_MPID_TB(3, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x440000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        30, 30, PLATFORM_GET_MPID_TB(3, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x480000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        31, 31, PLATFORM_GET_MPID_TB(3, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4D000000  + 0x20000000 + 0x4C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        32, 32, PLATFORM_GET_MPID_TA_2(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x100000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        33, 33, PLATFORM_GET_MPID_TA_2(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x140000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        34, 34, PLATFORM_GET_MPID_TA_2(0, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x180000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        35, 35, PLATFORM_GET_MPID_TA_2(0, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x1C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        36, 36, PLATFORM_GET_MPID_TA_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x200000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        37, 37, PLATFORM_GET_MPID_TA_2(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x240000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        38, 38, PLATFORM_GET_MPID_TA_2(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x280000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        39, 39, PLATFORM_GET_MPID_TA_2(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x2C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        40, 40, PLATFORM_GET_MPID_TA_2(2, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x300000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        41, 41, PLATFORM_GET_MPID_TA_2(2, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x340000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        42, 42, PLATFORM_GET_MPID_TA_2(2, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x380000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        43, 43, PLATFORM_GET_MPID_TA_2(2, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x3C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        44, 44, PLATFORM_GET_MPID_TA_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x400000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        45, 45, PLATFORM_GET_MPID_TA_2(3, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x440000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        46, 46, PLATFORM_GET_MPID_TA_2(3, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x480000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        47, 47, PLATFORM_GET_MPID_TA_2(3, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x4C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        48, 48, PLATFORM_GET_MPID_TB_2(0, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x100000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        49, 49, PLATFORM_GET_MPID_TB_2(0, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x140000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        50, 50, PLATFORM_GET_MPID_TB_2(0, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x180000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        51, 51, PLATFORM_GET_MPID_TB_2(0, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x1C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        52, 52, PLATFORM_GET_MPID_TB_2(1, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x200000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        53, 53, PLATFORM_GET_MPID_TB_2(1, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000 + 0x20000000 + 0x240000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        54, 54, PLATFORM_GET_MPID_TB_2(1, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x280000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        55, 55, PLATFORM_GET_MPID_TB_2(1, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x2C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        56, 56, PLATFORM_GET_MPID_TB_2(2, 0),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x300000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        57, 57, PLATFORM_GET_MPID_TB_2(2, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x340000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        58, 58, PLATFORM_GET_MPID_TB_2(2, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x380000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        59, 59, PLATFORM_GET_MPID_TB_2(2, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x3C0000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        60, 60, PLATFORM_GET_MPID_TB_2(3, 0), EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x400000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        61, 61, PLATFORM_GET_MPID_TB_2(3, 1),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x440000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        62, 62, PLATFORM_GET_MPID_TB_2(3, 2),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x480000 /* GicRBase */),
+    EFI_ACPI_5_1_GICC_STRUCTURE_INIT(
+        63, 63, PLATFORM_GET_MPID_TB_2(3, 3),  EFI_ACPI_5_0_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
+        FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x20000, FixedPcdGet32 (PcdGicInterruptInterfaceBase) + 0x10000, 25, 0x4004D000000  + 0x20000000 + 0x4C0000 /* GicRBase */),
+  },
+
+  EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, 0x4D000000, 0, 0x4),
+  {
+    EFI_ACPI_6_0_GIC_ITS_INIT(0,0x4C000000), //peri a
+    EFI_ACPI_6_0_GIC_ITS_INIT(1,0x6C000000), //peri b
+    EFI_ACPI_6_0_GIC_ITS_INIT(2,0xC6000000), //dsa a
+    EFI_ACPI_6_0_GIC_ITS_INIT(3,0x8C6000000), //dsa b
+    EFI_ACPI_6_0_GIC_ITS_INIT(4,0x4004C000000), //P1 peri a
+    EFI_ACPI_6_0_GIC_ITS_INIT(5,0x4006C000000), //P1 peri b
+    EFI_ACPI_6_0_GIC_ITS_INIT(6,0x400C6000000), //P1 dsa a
+    EFI_ACPI_6_0_GIC_ITS_INIT(7,0x408C6000000), //P1 dsa b
+  }
+};
+
+//
+// Reference the table being generated to prevent the optimizer from removing the
+// data structure from the executable
+//
+VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h
new file mode 100644
index 0000000..4bc1c91
--- /dev/null
+++ b/Chips/Hisilicon/Hi1616/Include/Library/SerdesLib.h
@@ -0,0 +1,78 @@
+#ifndef _SERDES_LIB_H_
+#define _SERDES_LIB_H_
+
+typedef enum hilink0_mode_type
+{
+    EM_HILINK0_HCCS1_8LANE = 0,
+    EM_HILINK0_PCIE1_8LANE = 2,
+    EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE = 3,
+    EM_HILINK0_SAS2_8LANE = 4,
+    EM_HILINK0_HCCS1_8LANE_16,
+    EM_HILINK0_HCCS1_8LANE_32,
+    EM_HILINK0_HCCS1_8LANE_5000,
+}hilink0_mode_type_e;
+
+typedef enum hilink1_mode_type
+{
+    EM_HILINK1_SAS2_1LANE = 0,
+    EM_HILINK1_HCCS0_8LANE = 1,
+    EM_HILINK1_PCIE0_8LANE = 2,
+    EM_HILINK1_HCCS0_8LANE_16,
+    EM_HILINK1_HCCS0_8LANE_32,
+    EM_HILINK1_HCCS0_8LANE_5000,
+}hilink1_mode_type_e;
+
+typedef enum hilink2_mode_type
+{
+    EM_HILINK2_PCIE2_8LANE = 0,
+    EM_HILINK2_HCCS2_8LANE = 1,
+    EM_HILINK2_SAS0_8LANE = 2,
+    EM_HILINK2_HCCS2_8LANE_16,
+    EM_HILINK2_HCCS2_8LANE_32,
+    EM_HILINK2_HCCS2_8LANE_5000,
+}hilink2_mode_type_e;
+
+typedef enum hilink5_mode_type
+{
+    EM_HILINK5_PCIE3_4LANE = 0,
+    EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE = 1,
+    EM_HILINK5_SAS1_4LANE = 2,
+
+}hilink5_mode_type_e;
+
+
+typedef struct serdes_param
+{
+    hilink0_mode_type_e hilink0_mode;
+    hilink1_mode_type_e hilink1_mode;
+    hilink2_mode_type_e hilink2_mode;
+    UINT32 hilink3_mode;
+    UINT32 hilink4_mode;
+    hilink5_mode_type_e hilink5_mode;
+    UINT32 hilink6_mode;
+    UINT32 use_ssc;
+    //board_type_e board_type;
+}serdes_param_t;
+
+#define SERDES_INVALID_MACRO_ID  0xFFFFFFFF
+#define SERDES_INVALID_LANE_NUM  0xFFFFFFFF
+#define SERDES_INVALID_RATE_MODE  0xFFFFFFFF
+
+typedef struct {
+    UINT32 MacroId;
+    UINT32 DsNum;
+    UINT32 DsCfg;
+} SERDES_POLARITY_INVERT;
+
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId);
+extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
+extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
+UINT32 GetEthType(UINT8 EthChannel);
+void serdes_enable_ctle_dfe(UINT32 nimbus_id, UINT32 macro, UINT32 lane, UINT32 lane_mode);
+
+EFI_STATUS
+EfiSerdesInitWrap (VOID);
+INT32 SerdesReset(UINT32 SiclId, UINT32 Macro);
+VOID SerdesLoadFirmware(UINT32 SiclId, UINT32 Macro);
+
+#endif
diff --git a/Chips/Hisilicon/HisiPkg.dec b/Chips/Hisilicon/HisiPkg.dec
index b76cd72..96af3cc 100644
--- a/Chips/Hisilicon/HisiPkg.dec
+++ b/Chips/Hisilicon/HisiPkg.dec
@@ -104,7 +104,10 @@
   gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x0|UINT64|0x40000008
   gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base|0x0|UINT64|0x40000009
   gHisiTokenSpaceGuid.PcdTrustedFirmwareMagicNum|0x5A5A5A5A|UINT32|0x4000000a
+  gHisiTokenSpaceGuid.PcdIsMPBoot|0|UINT32|0x4000000b
+  gHisiTokenSpaceGuid.PcdSocketMask|1|UINT32|0x4000001b
 
+  gHisiTokenSpaceGuid.PcdMacAddress|0x0|UINT64|0x4000000c
   gHisiTokenSpaceGuid.PcdNumaEnable|0|UINT32|0x4000000d
 
   gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x0|UINT64|0x10000038
diff --git a/Chips/Hisilicon/Include/Library/AcpiNextLib.h b/Chips/Hisilicon/Include/Library/AcpiNextLib.h
index 639b702..5a810ec 100644
--- a/Chips/Hisilicon/Include/Library/AcpiNextLib.h
+++ b/Chips/Hisilicon/Include/Library/AcpiNextLib.h
@@ -32,14 +32,14 @@
      GicRBase, GicRlength \
   }
 
-#define EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE_INIT(                                              \
+#define EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE_INIT(                                              \
     ProximityDomain, ACPIProcessorUID, Flags, ClockDomain)                                      \
   {                                                                                             \
     3, sizeof (EFI_ACPI_5_1_GICC_AFFINITY_STRUCTURE),ProximityDomain ,                          \
      ACPIProcessorUID,  Flags,  ClockDomain                                                     \
   }
 
-#define EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE_INIT(                                              \
+#define EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE_INIT(                                              \
     ProximityDomain, AddressBaseLow, AddressBaseHigh, LengthLow, LengthHigh, Flags)               \
   {                                                                                               \
     1, sizeof (EFI_ACPI_5_0_MEMORY_AFFINITY_STRUCTURE),ProximityDomain , EFI_ACPI_RESERVED_WORD,  \
@@ -47,6 +47,21 @@
     EFI_ACPI_RESERVED_QWORD                                                                       \
   }
 
+#pragma pack(1)
+//
+// Define the number of each table type.
+// This is where the table layout is modified.
+//
+#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT  64
+#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT                10
 
+
+typedef struct {
+  EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER          Header;
+  EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE                      Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
+  EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE                        Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
+} EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
+
+#pragma pack()
 #endif
 
diff --git a/Chips/Hisilicon/Include/Library/OemMiscLib.h b/Chips/Hisilicon/Include/Library/OemMiscLib.h
index 19d92e0..6f18c0f 100644
--- a/Chips/Hisilicon/Include/Library/OemMiscLib.h
+++ b/Chips/Hisilicon/Include/Library/OemMiscLib.h
@@ -44,6 +44,7 @@ BOOLEAN OemIsMpBoot();
 UINT32 OemIsWarmBoot();
 
 VOID OemBiosSwitch(UINT32 Master);
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID);
 
 extern EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM];
 EFI_HII_HANDLE EFIAPI OemGetPackages ();
diff --git a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
index 4327406..7867fd0 100644
--- a/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
+++ b/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
@@ -41,6 +41,7 @@
   TimerLib
   I2CLib
   PcdLib
+  CpldIoLib
 
 [FixedPcd]
 
diff --git a/Platforms/Hisilicon/D05/D05.dsc b/Platforms/Hisilicon/D05/D05.dsc
new file mode 100644
index 0000000..1452696
--- /dev/null
+++ b/Platforms/Hisilicon/D05/D05.dsc
@@ -0,0 +1,672 @@
+#
+#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+
+################################################################################
+#
+# Defines Section - statements that will be processed to create a Makefile.
+#
+################################################################################
+[Defines]
+  PLATFORM_NAME                  = D05
+  PLATFORM_GUID                  = D0D445F1-B2CA-4101-9986-1B23525CBEA6
+  PLATFORM_VERSION               = 0.1
+  DSC_SPECIFICATION              = 0x00010005
+  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
+  SUPPORTED_ARCHITECTURES        = AARCH64
+  BUILD_TARGETS                  = DEBUG|RELEASE
+  SKUID_IDENTIFIER               = DEFAULT
+  FLASH_DEFINITION               = OpenPlatformPkg/Platforms/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
+  DEFINE EDK2_SKIP_PEICORE=0
+  DEFINE INCLUDE_TFTP_COMMAND=1
+
+!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.dsc.inc
+
+[LibraryClasses.common]
+  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
+  ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf
+
+  ArmPlatformSysConfigLib|ArmPlatformPkg/ArmVExpressPkg/Library/ArmVExpressSysConfigLib/ArmVExpressSysConfigLib.inf
+  NorFlashPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/NorFlashArmVExpressLib/NorFlashArmVExpressLib.inf
+  LcdPlatformLib|ArmPlatformPkg/ArmVExpressPkg/Library/PL111LcdArmVExpressLib/PL111LcdArmVExpressLib.inf
+
+
+  I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLib.inf
+  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+
+  IpmiCmdLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
+
+  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
+  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
+  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
+
+
+
+!ifdef $(FDT_ENABLE)
+  #FDTUpdateLib
+  FdtUpdateLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/FdtUpdateLib/FdtUpdateLib.inf
+!endif #$(FDT_ENABLE)
+
+  CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
+
+  SerdesLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/Hi1616Serdes/Hi1616SerdesLib.inf
+
+  EfiTimeBaseLib|OpenPlatformPkg/Library/EfiTimeBaseLib/EfiTimeBaseLib.inf
+  RealTimeClockLib|OpenPlatformPkg/Chips/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.inf
+
+  OemMiscLib|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
+  OemAddressMapLib|OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Library/OemAddressMapD05/OemAddressMapD05.inf
+  PlatformSysCtrlLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1616/Library/PlatformSysCtrlLibHi1616/PlatformSysCtrlLibHi1616.inf
+
+  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+  PlatformBdsLib|OpenPlatformPkg/Chips/Hisilicon/Library/PlatformIntelBdsLib/PlatformIntelBdsLib.inf
+  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
+
+  # USB Requirements
+  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+
+  LpcLib|OpenPlatformPkg/Chips/Hisilicon/Binary/Hi1610/Library/LpcLib/LpcLib.inf
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+[LibraryClasses.common.SEC]
+  ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLibSec.inf
+
+
+[LibraryClasses.common.DXE_RUNTIME_DRIVER]
+  I2CLib|OpenPlatformPkg/Chips/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
+  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+
+[BuildOptions]
+  GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM -I$(WORKSPACE)/OpenPlatformPkg/Chips/Hisilicon/Hi1616/Include
+
+################################################################################
+#
+# Pcd Section - list of all EDK II PCD Entries defined by this Platform
+#
+################################################################################
+
+[PcdsFeatureFlag.common]
+
+!if $(EDK2_SKIP_PEICORE) == 1
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryInitializeInSec|TRUE
+  gArmPlatformTokenSpaceGuid.PcdSendSgiToBringUpSecondaryCores|TRUE
+!endif
+
+  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
+  #  It could be set FALSE to save size.
+  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
+  gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+
+[PcdsFixedAtBuild.common]
+  gArmPlatformTokenSpaceGuid.PcdFirmwareVendor|"ARM Versatile Express"
+  gEmbeddedTokenSpaceGuid.PcdEmbeddedPrompt|"D05"
+
+  gArmPlatformTokenSpaceGuid.PcdCoreCount|8
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
+
+  # Stacks for MPCores in Secure World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecStackBase|0xE1000000
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecPrimaryStackSize|0x10000
+
+  # Stacks for MPCores in Monitor Mode
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresSecMonStackBase|0xE100FF00
+  gArmPlatformTokenSpaceGuid.PcdCPUCoreSecMonStackSize|0x100
+
+  # Stacks for MPCores in Normal World
+  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xE1000000
+  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0xFF00
+
+  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
+
+
+  gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
+
+
+  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
+  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
+
+  gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
+
+
+  #
+  # ARM Pcds
+  #
+  gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000040000000
+
+  #
+  # ARM PrimeCell
+  #
+
+
+  gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
+
+
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask|0x94 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
+                                                # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
+  gHisiTokenSpaceGuid.PcdPcieRootBridgeMask2P|0x0494 # bit0:HB0RB0,bit1:HB0RB1,bit2:HB0RB2,bit3:HB0RB3,bit4:HB0RB4,bit5:HB0RB5,bit6:HB0RB6,bit7:HB0RB7
+                                                # bit8:HB1RB0,bit9:HB1RB1,bit10:HB1RB2,bit11:HB1RB3,bit12:HB1RB4,bit13:HB1RB5,bit14:HB1RB6,bit14:HB1RB15
+
+  ## SP805 Watchdog - Motherboard Watchdog
+  gArmPlatformTokenSpaceGuid.PcdSP805WatchdogBase|0x601e0000
+
+  ## Serial Terminal
+  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x602B0000
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
+
+  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000
+
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
+  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
+
+
+  gHisiTokenSpaceGuid.PcdM3SmmuBaseAddress|0xa0040000
+  gHisiTokenSpaceGuid.PcdPcieSmmuBaseAddress|0xb0040000
+  gHisiTokenSpaceGuid.PcdDsaSmmuBaseAddress|0xc0040000
+  gHisiTokenSpaceGuid.PcdAlgSmmuBaseAddress|0xd0040000
+
+
+  gHisiTokenSpaceGuid.PcdIsMPBoot|1
+  gHisiTokenSpaceGuid.PcdSocketMask|0x3
+  gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D05 UEFI 16.08 RC1"
+
+  gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
+
+  gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"1.12"
+
+  gHisiTokenSpaceGuid.PcdSystemProductName|L"D05"
+  gHisiTokenSpaceGuid.PcdSystemVersion|L"Estuary"
+  gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D05"
+  gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
+
+  gHisiTokenSpaceGuid.PcdCPUInfo|L"Hi1616"
+
+  #
+  # ARM PL390 General Interrupt Controller
+  #
+
+  gArmTokenSpaceGuid.PcdGicDistributorBase|0x4D000000
+  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0x4D100000
+  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
+
+  #
+  # ARM OS Loader
+  #
+  # Versatile Express machine type (ARM VERSATILE EXPRESS = 2272) required for ARM Linux:
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDescription|L"Linux from SATA"
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootDevicePath|L"EFI\GRUB2\grubaa64.efi"
+  gArmPlatformTokenSpaceGuid.PcdDefaultBootArgument|""
+
+  # Use the serial console (ConIn & ConOut) and the Graphic driver (ConOut)
+  gArmPlatformTokenSpaceGuid.PcdDefaultConOutPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi();VenHw(407B4008-BF5B-11DF-9547-CF16E0D72085)"
+  gArmPlatformTokenSpaceGuid.PcdDefaultConInPaths|L"VenHw(D3987D4B-971A-435F-8CAF-4967EB627241)/Uart(115200,8,N,1)/VenPcAnsi()"
+
+  #
+  # ARM Architectual Timer Frequency
+  #
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|50000000
+
+
+  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
+  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
+
+  gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x40010000
+  gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
+
+  gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x78000000
+
+  gHisiTokenSpaceGuid.PcdSFCCFGBaseAddress|0xA6000000
+  gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0xA4000000
+
+
+  gOpenPlatformTokenSpaceGuid.PcdRamDiskMaxSize|128
+
+
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x40000000
+
+
+  gHisiTokenSpaceGuid.PcdMdioSubctrlAddress|0x60000000
+
+  ## DTB address at spi flash
+  gHisiTokenSpaceGuid.FdtFileAddress|0xA47A0000
+
+  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
+
+  gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
+
+  gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
+
+  gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
+
+  gHisiTokenSpaceGuid.PcdNORFlashBase|0x70000000
+  gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
+
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
+  gHisiTokenSpaceGuid.PcdNumaEnable|1
+  gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000
+
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress|0x40000000000
+
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress|0xA0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress|0xA0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress|0xA0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress|0xA0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress|0x8A0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress|0x8B0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize|0x8000000
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress|0x8A0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress|0x8B0000000
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress|0x400A0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress|0x400A0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress|0x64000000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize|0x400000000
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress|0x400A0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress|0x74000000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize|0x400000000
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress|0x78000000000
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize|0x400000000
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress|0x408A0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize|0x10000000
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress|0x408A0000000
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize|0x10000000
+
+  gHisiTokenSpaceGuid.PciHb0Rb0Base|0xa0090000
+  gHisiTokenSpaceGuid.PciHb0Rb1Base|0xa0200000
+  gHisiTokenSpaceGuid.PciHb0Rb2Base|0xa00a0000
+  gHisiTokenSpaceGuid.PciHb0Rb3Base|0xa00b0000
+  gHisiTokenSpaceGuid.PciHb0Rb4Base|0x8a0090000
+  gHisiTokenSpaceGuid.PciHb0Rb5Base|0x8a0200000
+  gHisiTokenSpaceGuid.PciHb0Rb6Base|0x8a00a0000
+  gHisiTokenSpaceGuid.PciHb0Rb7Base|0x8a00b0000
+  gHisiTokenSpaceGuid.PciHb1Rb0Base|0x600a0090000
+  gHisiTokenSpaceGuid.PciHb1Rb1Base|0x600a0200000
+  gHisiTokenSpaceGuid.PciHb1Rb2Base|0x600a00a0000
+  gHisiTokenSpaceGuid.PciHb1Rb3Base|0x600a00b0000
+  gHisiTokenSpaceGuid.PciHb1Rb4Base|0x700a0090000
+  gHisiTokenSpaceGuid.PciHb1Rb5Base|0x700a0200000
+  gHisiTokenSpaceGuid.PciHb1Rb6Base|0x700a00a0000
+  gHisiTokenSpaceGuid.PciHb1Rb7Base|0x700a00b0000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress|0xa8400000
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress|0xa9400000
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress|0xa8800000
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize|0x77effff
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress|0xab400000
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress|0xa9000000
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize|0x2feffff
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress|0xb0800000
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize|0x77effff
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress|0xac900000
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize|0x36effff
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress|0xb9800000
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize|0x67effff
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress|0x400a8400000
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress|0x400a9400000
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress|0x20000000
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize|0xcfffffff
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress|0x400ab400000
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress|0x30000000
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize|0xbfffffff
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress|0x40000000
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize|0xafffffff
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress|0x408aa400000
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize|0xbeffff
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress|0x408ab400000
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize|0xbeffff
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase|0xA8400000
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase|0xA9400000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase|0xA8800000
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase|0xAB400000
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase|0x8A9000000
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase|0x8B0800000
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase|0x8AC900000
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase|0x8B9800000
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase|0x400A8400000
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase|0x400A9400000
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase|0x65020000000
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase|0x400AB400000
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase|0x75030000000
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase|0x79040000000
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase|0x408AA400000
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase|0x408AB400000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase|0xa8ff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase|0xa9ff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase|0xafff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase|0xabff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase|0x8abff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase|0x8b7ff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase|0x8afff0000
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase|0x8bfff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase|0x400a8ff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase|0x400a9ff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase|0x67fffff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase|0x400abff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase|0x77fffff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase|0x7bfffff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase|0x408aaff0000
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase|0x408abff0000
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoBase|0
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoBase|0
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoSize|0xffff #64K
+
+  gHisiTokenSpaceGuid.Pcdsoctype|0x1616
+  ## SP804 DualTimer
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerFrequencyInMHz|200
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicInterruptNum|0xb0
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPeriodicBase|0x40060000
+  ## TODO: need to confirm the base for Performance and Metronome base for PV660
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerPerformanceBase|0x40060000
+  gArmPlatformTokenSpaceGuid.PcdSP804TimerMetronomeBase|0x40060000
+
+################################################################################
+#
+# Components Section - list of all EDK II Modules needed by this Platform
+#
+################################################################################
+[Components.common]
+
+  #
+  # SEC
+  #
+
+  #
+  # PEI Phase modules
+  #
+!if $(EDK2_SKIP_PEICORE) == 1
+  ArmPlatformPkg/PrePi/PeiMPCore.inf {
+    <LibraryClasses>
+      ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf
+      ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
+  }
+  ArmPlatformPkg/PrePi/PeiUniCore.inf {
+    <LibraryClasses>
+      ArmPlatformLib|OpenPlatformPkg/Chips/Hisilicon/Library/ArmPlatformLibPv660/ArmPlatformLib.inf
+      ArmPlatformGlobalVariableLib|ArmPlatformPkg/Library/ArmPlatformGlobalVariableLib/PrePi/PrePiArmPlatformGlobalVariableLib.inf
+  }
+!else
+  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  MdeModulePkg/Core/Pei/PeiMain.inf
+  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
+
+  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
+  ArmPkg/Drivers/CpuPei/CpuPei.inf
+  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+
+  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+    <LibraryClasses>
+      NULL|IntelFrameworkModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+  }
+!endif
+
+  #
+  # DXE
+  #
+  MdeModulePkg/Core/Dxe/DxeMain.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
+  }
+  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
+
+  #
+  # Architectural Protocols
+  #
+  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
+
+  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  MdeModulePkg/Universal/Variable/EmuRuntimeDxe/EmuVariableRuntimeDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
+    <LibraryClasses>
+      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
+  }
+  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
+  EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
+    <LibraryClasses>
+      CpldIoLib|OpenPlatformPkg/Chips/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf
+  }
+  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Simple TextIn/TextOut for UEFI Terminal
+  EmbeddedPkg/SimpleTextInOutSerial/SimpleTextInOutSerial.inf
+
+  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+
+  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+  IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+  #
+  #ACPI
+  #
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+
+  OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  # Usb Support
+  #
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
+  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
+
+  #
+  #network
+  #
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
+
+  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+
+  OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
+  MdeModulePkg/Application/HelloWorld/HelloWorld.inf
+  #
+  # Bds
+  #
+  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
+
+  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+
+!ifdef $(FDT_ENABLE)
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
+
+  #PCIe Support
+  OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+  OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf {
+    <LibraryClasses>
+      NULL|OpenPlatformPkg/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
+  }
+
+  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
+  OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
+
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+
+
+  OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+  #
+  # Memory test
+  #
+  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+
+  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  ShellPkg/Application/Shell/Shell.inf {
+    <LibraryClasses>
+      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
+      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
+      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
+      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
+      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
+!ifdef $(INCLUDE_DP)
+      NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
+!endif #$(INCLUDE_DP)
+!ifdef $(INCLUDE_TFTP_COMMAND)
+      NULL|ShellPkg/Library/UefiShellTftpCommandLib/UefiShellTftpCommandLib.inf
+!endif #$(INCLUDE_TFTP_COMMAND)
+
+    <PcdsFixedAtBuild>
+      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
+      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
+  }
diff --git a/Platforms/Hisilicon/D05/D05.fdf b/Platforms/Hisilicon/D05/D05.fdf
new file mode 100644
index 0000000..170f2b3
--- /dev/null
+++ b/Platforms/Hisilicon/D05/D05.fdf
@@ -0,0 +1,354 @@
+#
+#  Copyright (c) 2011, 2012, ARM Limited. All rights reserved.
+#  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#  Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution.  The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+
+[DEFINES]
+
+################################################################################
+#
+# FD Section
+# The [FD] Section is made up of the definition statements and a
+# description of what goes into  the Flash Device Image.  Each FD section
+# defines one flash "device" image.  A flash device image may be one of
+# the following: Removable media bootable image (like a boot floppy
+# image,) an Option ROM image (that would be "flashed" into an add-in
+# card,) a System "Flash"  image (that would be burned into a system's
+# flash) or an Update ("Capsule") image that will be used to update and
+# existing system flash.
+#
+################################################################################
+[FD.D05]
+
+BaseAddress   = 0xA4800000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
+
+Size          = 0x00300000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
+ErasePolarity = 1
+
+# This one is tricky, it must be: BlockSize * NumBlocks = Size
+BlockSize     = 0x00010000
+NumBlocks     = 0x30
+
+################################################################################
+#
+# Following are lists of FD Region layout which correspond to the locations of different
+# images within the flash device.
+#
+# Regions must be defined in ascending order and may not overlap.
+#
+# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
+# the pipe "|" character, followed by the size of the region, also in hex with the leading
+# "0x" characters. Like:
+# Offset|Size
+# PcdOffsetCName|PcdSizeCName
+# RegionType <FV, DATA, or FILE>
+#
+################################################################################
+
+0x00000000|0x00040000
+gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Sec/FVMAIN_SEC.Fv
+
+0x00040000|0x00240000
+gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+FV = FVMAIN_COMPACT
+
+0x00280000|0x00020000
+gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/bl1.bin
+0x002A0000|0x00020000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/fip.bin
+
+0x002D0000|0x0000E000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+DATA = {
+  ## This is the EFI_FIRMWARE_VOLUME_HEADER
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
+  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
+  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
+  # FvLength: 0x20000
+  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
+  #Signature "_FVH"       #Attributes
+  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
+  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
+  0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
+  #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
+  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
+  #Blockmap[1]: End
+  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+  ## This is the VARIABLE_STORE_HEADER gEfiVariableGuid
+  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
+  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
+  #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
+  0xB8, 0xdF, 0x00, 0x00,
+  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
+  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002DE000|0x00002000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+#NV_FTW_WORKING
+DATA = {
+  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
+  0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
+  0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
+  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
+  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
+  # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
+  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+}
+
+0x002E0000|0x00010000
+gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+
+0x002F0000|0x00010000
+FILE = OpenPlatformPkg/Platforms/Hisilicon/Binary/D03/CustomData.Fv
+
+################################################################################
+#
+# FV Section
+#
+# [FV] section is used to define what components or modules are placed within a flash
+# device file.  This section also defines order the components and modules are positioned
+# within the image.  The [FV] section consists of define statements, set statements and
+# module statements.
+#
+################################################################################
+
+[FV.FvMain]
+BlockSize          = 0x40
+NumBlocks          = 0         # This FV gets compressed so make it just big enough
+FvAlignment        = 16        # FV alignment and FV attributes setting.
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+  APRIORI DXE {
+    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+  }
+
+  INF MdeModulePkg/Core/Dxe/DxeMain.inf
+  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/IoInitDxe/IoInitDxe.inf
+  #
+  # PI DXE Drivers producing Architectural Protocols (EFI Services)
+  #
+  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/SFC/SfcDxeDriver.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/OemNicConfig2PHi1610/OemNicConfig2P.inf
+
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+
+  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
+  INF EmbeddedPkg/EmbeddedMonotonicCounter/EmbeddedMonotonicCounter.inf
+
+  INF EmbeddedPkg/ResetRuntimeDxe/ResetRuntimeDxe.inf
+  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
+  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
+
+  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
+
+  #
+  # Multiple Console IO support
+  #
+  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
+  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
+  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
+  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
+  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
+
+  # Simple TextIn/TextOut for UEFI Terminal
+
+  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
+  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
+
+  INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
+
+  #
+  # FAT filesystem + GPT/MBR partitioning
+  #
+  INF OpenPlatformPkg/Drivers/Block/ramdisk/ramdisk.inf
+  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
+  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
+  INF FatBinPkg/EnhancedFatDxe/Fat.inf
+  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
+
+  #
+  # Usb Support
+  #
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VirtualEhciPciIo/VirtualEhciPciIo.inf
+  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/OhciDxe/OhciDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
+  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
+
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+
+  #
+  #ACPI
+  #
+  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  INF RuleOverride=ACPITABLE OpenPlatformPkg/Chips/Hisilicon/Hi1616/D05AcpiTables/AcpiTablesHi1616.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+
+  #
+  #Network
+  #
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac0/SnpPV600DxeMac0.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac1/SnpPV600DxeMac1.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac4/SnpPV600DxeMac4.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Net/SnpPV660DxeMac5/SnpPV600DxeMac5.inf
+
+  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
+  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
+  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
+  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
+  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
+
+!ifdef $(FDT_ENABLE)
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/UpdateFdtDxe/UpdateFdtDxe.inf
+!endif #$(FDT_ENABLE)
+
+  #
+  # PCI Support
+  #
+  INF OpenPlatformPkg/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitDxe.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/D03/Drivers/PciPlatform/PciPlatform.inf
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/PciHostBridgeDxe/PciHostBridgeDxe.inf
+  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/ReportPciePlugDidVidToBmc/ReportPciePlugDidVidToBmc.inf
+  # VGA Driver
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sm750Dxe/UefiSmi.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Sas/SasDxeDriver.inf
+  #
+  # UEFI application (Shell Embedded Boot Loader)
+  #
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Ebl/Ebl.inf
+
+  #
+  # Build Shell from latest source code instead of prebuilt binary
+  #
+  INF ShellPkg/Application/Shell/Shell.inf
+
+  #
+  # Bds
+  #
+  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
+
+  INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
+  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+  INF IntelFrameworkModulePkg/Universal/BdsDxe/BdsDxe.inf
+
+
+[FV.FVMAIN_COMPACT]
+FvAlignment        = 16
+ERASE_POLARITY     = 1
+MEMORY_MAPPED      = TRUE
+STICKY_WRITE       = TRUE
+LOCK_CAP           = TRUE
+LOCK_STATUS        = TRUE
+WRITE_DISABLED_CAP = TRUE
+WRITE_ENABLED_CAP  = TRUE
+WRITE_STATUS       = TRUE
+WRITE_LOCK_CAP     = TRUE
+WRITE_LOCK_STATUS  = TRUE
+READ_DISABLED_CAP  = TRUE
+READ_ENABLED_CAP   = TRUE
+READ_STATUS        = TRUE
+READ_LOCK_CAP      = TRUE
+READ_LOCK_STATUS   = TRUE
+
+!if $(EDK2_SKIP_PEICORE) == 1
+  INF ArmPlatformPkg/PrePi/PeiMPCore.inf
+!else
+  APRIORI PEI {
+    INF  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  }
+  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
+  INF MdeModulePkg/Core/Pei/PeiMain.inf
+  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
+
+  INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+
+  INF OpenPlatformPkg/Chips/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/Binary/D05/MemoryInitPei/MemoryInitPeim.inf
+  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+  INF OpenPlatformPkg/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
+
+  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+!endif
+
+  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+      SECTION FV_IMAGE = FVMAIN
+    }
+  }
+
+
+!include OpenPlatformPkg/Chips/Hisilicon/Pv660/Pv660.fdf.inc
+
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c
new file mode 100644
index 0000000..c4f2e97
--- /dev/null
+++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.c
@@ -0,0 +1,106 @@
+/** @file
+*
+*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2016, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+
+#include <Uefi.h>
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/PcdLib.h>
+#include <Library/IoLib.h>
+#include <Library/CacheMaintenanceLib.h>
+
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+
+#include <Library/OemMiscLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/ArmLib.h>
+
+#define PERI_SUBCTRL_BASE                               (0x40000000)
+#define MDIO_SUBCTRL_BASE                               (0x60000000)
+#define PCIE2_SUBCTRL_BASE                              (0xA0000000)
+#define PCIE0_SUBCTRL_BASE                              (0xB0000000)
+#define ALG_BASE                                        (0xD0000000)
+
+#define SC_BROADCAST_EN_REG                             (0x16220)
+#define SC_BROADCAST_SCL1_ADDR0_REG                     (0x16230)
+#define SC_BROADCAST_SCL1_ADDR1_REG                     (0x16234)
+#define SC_BROADCAST_SCL2_ADDR0_REG                     (0x16238)
+#define SC_BROADCAST_SCL2_ADDR1_REG                     (0x1623C)
+#define SC_BROADCAST_SCL3_ADDR0_REG                     (0x16240)
+#define SC_BROADCAST_SCL3_ADDR1_REG                     (0x16244)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG                 (0x1000)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG         (0x1010)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG         (0x1014)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG         (0x1018)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG         (0x101C)
+#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG                  (0x1200)
+#define SC_ITS_M3_INT_MUX_SEL_REG                       (0x21F0)
+#define SC_TM_CLKEN0_REG                                (0x2050)
+
+#define SC_TM_CLKEN0_REG_VALUE                          (0x3)
+#define SC_BROADCAST_EN_REG_VALUE                       (0x7)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0              (0x0)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1              (0x40016260)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2              (0x60016260)
+#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3              (0x400)
+#define SC_ITS_M3_INT_MUX_SEL_REG_VALUE                 (0x7)
+#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0           (0x0)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0          (0x27)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1          (0x2F)
+#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2          (0x77)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0  (0x178033)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0  (0x17003c)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0  (0x15003d)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1  (0x170035)
+#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0  (0x16003e)
+
+void QResetAp(VOID)
+{
+    MmioWrite64(FixedPcdGet64(PcdMailBoxAddress), 0x0);
+    (void)WriteBackInvalidateDataCacheRange((VOID *) FixedPcdGet64(PcdMailBoxAddress), 8);
+    ArmDataSynchronizationBarrier ();
+    ArmInstructionSynchronizationBarrier ();
+
+    //SCCL A
+    if (!PcdGet64 (PcdTrustedFirmwareEnable))
+    {
+        StartupAp();
+    }
+}
+
+
+EFI_STATUS
+EFIAPI
+EarlyConfigEntry (
+  IN       EFI_PEI_FILE_HANDLE  FileHandle,
+  IN CONST EFI_PEI_SERVICES     **PeiServices
+  )
+{
+    DEBUG((EFI_D_INFO,"SMMU CONFIG........."));
+    (VOID)SmmuConfigForBios();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"AP CONFIG........."));
+    (VOID)QResetAp();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    DEBUG((EFI_D_INFO,"MN CONFIG........."));
+    (VOID)MN_CONFIG();
+    DEBUG((EFI_D_INFO,"Done\n"));
+
+    return EFI_SUCCESS;
+}
+
diff --git a/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
new file mode 100644
index 0000000..3e1331d
--- /dev/null
+++ b/Platforms/Hisilicon/D05/EarlyConfigPeim/EarlyConfigPeimD05.inf
@@ -0,0 +1,55 @@
+#/** @file
+#
+#    Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2016, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = EarlyConfigPeimD05
+  FILE_GUID                      = A181AD33-E64A-4084-A54A-A69DF1FB0ABF
+  MODULE_TYPE                    = PEIM
+  VERSION_STRING                 = 1.0
+  ENTRY_POINT                    = EarlyConfigEntry
+
+[Sources.common]
+  EarlyConfigPeimD05.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+
+  ArmPkg/ArmPkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PeimEntryPoint
+  PcdLib
+  DebugLib
+  IoLib
+  CacheMaintenanceLib
+
+  PlatformSysCtrlLib
+  ArmLib
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdMailBoxAddress
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
+
+[Depex]
+## As we will clean mailbox in this module, need to wait memory init complete
+  gEfiPeiMemoryDiscoveredPpiGuid
+
+[BuildOptions]
+
diff --git a/Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/BoardFeatureD05.c
new file mode 100644
index 0000000..b94d9af
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/BoardFeatureD05.c
@@ -0,0 +1,58 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+
+#include <PlatformArch.h>
+#include <Library/HwMemInitLib.h>
+#include <Library/CpldIoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/I2CLib.h>
+#include <Library/OemMemConfigLib.h>
+
+/*
+SOCKET 0  TB DDRC0  DIMM0  J11  I2C1  0xA8  0x54
+                    DIMM1  J12  I2C1  0xAA  0x55
+          TB DDRC1  DIMM0  J14  I2C0  0xA8  0x54
+                    DIMM1  J15  I2C0  0xAA  0x55
+          TA DDRC0  DIMM0  J5   I2C1  0xA0  0x50
+                    DIMM1  J6   I2C1  0xA2  0x51
+          TA DDRC1  DIMM0  J8   I2C0  0xA0  0x50
+                    DIMM1  J9   I2C0  0xA2  0x51
+SOCKET 1  TB DDRC0  DIMM0  J23  I2C1  0xA8  0x54
+                    DIMM1  J24  I2C1  0xAA  0x55
+          TB DDRC1  DIMM0  J26  I2C0  0xA8  0x54
+                    DIMM1  J27  I2C0  0xAA  0x55
+          TA DDRC0  DIMM0  J17  I2C1  0xA0  0x50
+                    DIMM1  J18  I2C1  0xA2  0x51
+          TA DDRC1  DIMM0  J20  I2C0  0xA0  0x50
+                    DIMM1  J21  I2C0  0xA2  0x51
+
+
+*/
+I2C_SLAVE_ADDR  DimmSpdAddr[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
+    {{{I2C_PORT1,0x54},{I2C_PORT1,0x55},{I2C_INVALIDPORT,0xFF}},          //(CH0)skt0 TB DDRC0 [DIMM0 DIMM1]=[J11 J12]
+     {{I2C_PORT0,0x54},{I2C_PORT0,0x55},{I2C_INVALIDPORT,0xFF}},          //(CH1)skt0 TB DDRC1 [DIMM0 DIMM1]=[J14 J15]
+     {{I2C_PORT1,0x50},{I2C_PORT1,0x51},{I2C_INVALIDPORT,0xFF}},          //(CH2)skt0 TA DDRC0 [DIMM0 DIMM1]=[J5 J6]
+     {{I2C_PORT0,0x50},{I2C_PORT0,0x51},{I2C_INVALIDPORT,0xFF}}},         //(CH3)skt0 TA DDRC1 [DIMM0 DIMM1]=[J8 J9]
+
+    {{{I2C_PORT1,0x54},{I2C_PORT1,0x55},{I2C_INVALIDPORT,0xFF}},          //(CH0)skt0 TB DDRC0 [DIMM0 DIMM1]=[J11 J12]
+     {{I2C_PORT0,0x54},{I2C_PORT0,0x55},{I2C_INVALIDPORT,0xFF}},          //(CH1)skt0 TB DDRC1 [DIMM0 DIMM1]=[J14 J15]
+     {{I2C_PORT1,0x50},{I2C_PORT1,0x51},{I2C_INVALIDPORT,0xFF}},          //(CH2)skt0 TA DDRC0 [DIMM0 DIMM1]=[J5 J6]
+     {{I2C_PORT0,0x50},{I2C_PORT0,0x51},{I2C_INVALIDPORT,0xFF}}},         //(CH3)skt0 TA DDRC1 [DIMM0 DIMM1]=[J8 J9]
+};
+
diff --git a/Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/OemMemConfigLibD05.c b/Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/OemMemConfigLibD05.c
new file mode 100644
index 0000000..f2d91a1
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/OemMemConfigLibD05.c
@@ -0,0 +1,65 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/CpldIoLib.h>
+#include <Library/OemMemConfigLib.h>
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/SerialPortLib.h>
+
+UINT32 OemGetCurrentBiosChannel(VOID)
+{
+    return 0;
+}
+
+UINT32 OemGetDefaultSetupData(VOID *Setup)
+{
+    return 0;
+}
+
+VOID
+OemRecordMarginResult(
+    pGBL_DATA           pGblData,
+    struct rankMargin   resultsRxDq[],
+    struct rankMargin   resultsTxDq[],
+    struct rankMargin   resultsRxVref[],
+    struct rankMargin   resultsTxVref[]
+)
+{
+    return;
+}
+
+BOOLEAN OemIsLoadDefault()
+{
+    UINT32  Tmp;
+
+    Tmp = MmioRead32(0x602E0050);
+    if(BIT9 == (Tmp & BIT9))
+        return FALSE;
+    else
+        return TRUE;
+}
+
+VOID GetOemSetupConfig(pGBL_DATA pGblData)
+{
+    return;
+}
+
diff --git a/Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/OemMemConfigLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/OemMemConfigLibD05.inf
new file mode 100644
index 0000000..4c6ee4b
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMemConfigLibD05/OemMemConfigLibD05.inf
@@ -0,0 +1,44 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemMemConfigLibHi1616Evb
+  FILE_GUID                      = 06BC0DF0-22DA-11E6-B894-6FB79D10B849
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemMemConfigLib
+
+[Sources.common]
+  BoardFeatureD05.c
+  OemMemConfigLibD05.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+  HwPkg/HwPkg.dec
+
+[LibraryClasses]
+  SerialPortLib
+  CpldIoLib
+
+[BuildOptions]
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
new file mode 100644
index 0000000..77ee342
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
@@ -0,0 +1,226 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Protocol/Smbios.h>
+#include <IndustryStandard/SmBios.h>
+
+#include <PlatformArch.h>
+#include <Library/OemMiscLib.h>
+#include <Library/SerdesLib.h>
+#include <Library/I2CLib.h>
+#include <Library/HiiLib.h>
+#include <Library/IoLib.h>
+
+I2C_DEVICE gDS3231RtcDevice = {
+    .Socket = 0,
+    .Port = 4,
+    .DeviceType = DEVICE_TYPE_SPD,
+    .SlaveDeviceAddress = 0x68
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
+{
+    {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
+{
+    {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+serdes_param_t gSerdesParamNA = {
+    .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
+    .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
+    .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
+    .hilink3_mode = 0x0,
+    .hilink4_mode = 0xF,
+    .hilink5_mode = EM_HILINK5_SAS1_4LANE,
+    .hilink6_mode = 0x0,
+    .use_ssc      = 0,
+    };
+
+serdes_param_t gSerdesParamNB = {
+    .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
+    .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
+    .hilink2_mode = EM_HILINK2_SAS0_8LANE,
+    .hilink3_mode = 0x0,
+    .hilink4_mode = 0xF,
+    .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
+    .hilink6_mode = 0xF,
+    .use_ssc      = 0,
+    };
+
+serdes_param_t gSerdesParamS1NA = {
+    .hilink0_mode = EM_HILINK0_HCCS1_8LANE_16,
+    .hilink1_mode = EM_HILINK1_HCCS0_8LANE_16,
+    .hilink2_mode = EM_HILINK2_PCIE2_8LANE,
+    .hilink3_mode = 0x0,
+    .hilink4_mode = 0xF,
+    .hilink5_mode = EM_HILINK5_SAS1_4LANE,
+    .hilink6_mode = 0x0,
+    .use_ssc      = 0,
+    };
+
+serdes_param_t gSerdesParamS1NB = {
+    .hilink0_mode = EM_HILINK0_PCIE1_8LANE,
+    .hilink1_mode = EM_HILINK1_PCIE0_8LANE,
+    .hilink2_mode = EM_HILINK2_SAS0_8LANE,
+    .hilink3_mode = 0x0,
+    .hilink4_mode = 0xF,
+    .hilink5_mode = EM_HILINK5_PCIE2_2LANE_PCIE3_2LANE,
+    .hilink6_mode = 0xF,
+    .use_ssc      = 0,
+    };
+
+
+EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId)
+{
+  if (NULL == ParamA)
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+  if (NULL == ParamB)
+  {
+    DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if(0 == SocketId)
+  {
+      (VOID) CopyMem(ParamA, &gSerdesParamNA, sizeof(*ParamA));
+      (VOID) CopyMem(ParamB, &gSerdesParamNB, sizeof(*ParamB));
+  }
+  else
+  {
+      (VOID) CopyMem(ParamA, &gSerdesParamS1NA, sizeof(*ParamA));
+      (VOID) CopyMem(ParamB, &gSerdesParamS1NB, sizeof(*ParamB));
+  }
+
+  return EFI_SUCCESS;
+}
+
+
+VOID OemPcieResetAndOffReset(void)
+  {
+    return;
+  }
+
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
+    // PCIe0 Slot 1
+    {
+        {                                                     // Hdr
+            EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                         // Type,
+            0,                                                    // Length,
+            0                                                     // Handle
+        },
+        1,                                                    // SlotDesignation
+        SlotTypePciExpressX8,     // SlotType
+        SlotDataBusWidth8X,       // SlotDataBusWidth
+        SlotUsageAvailable,       // SlotUsage
+        SlotLengthOther,          // SlotLength
+        0x0001,                   // SlotId
+        {                         // SlotCharacteristics1
+            0,                      // CharacteristicsUnknown  :1;
+            0,                      // Provides50Volts         :1;
+            0,                      // Provides33Volts         :1;
+            0,                      // SharedSlot              :1;
+            0,                      // PcCard16Supported       :1;
+            0,                      // CardBusSupported        :1;
+            0,                      // ZoomVideoSupported      :1;
+            0                       // ModemRingResumeSupported:1;
+        },
+        {                         // SlotCharacteristics2
+            0,                      // PmeSignalSupported      :1;
+            0,                      // HotPlugDevicesSupported  :1;
+            0,                      // SmbusSignalSupported    :1;
+            0                       // Reserved                :5;
+        },
+        0x00,                     // SegmentGroupNum
+        0x00,                     // BusNum
+        0                         // DevFuncNum
+    },
+
+    // PCIe0 Slot 4
+    {
+        {                                                     // Hdr
+            EFI_SMBIOS_TYPE_SYSTEM_SLOTS,                         // Type,
+            0,                                                    // Length,
+            0                                                     // Handle
+        },
+        1,                                                    // SlotDesignation
+        SlotTypePciExpressX8,     // SlotType
+        SlotDataBusWidth8X,       // SlotDataBusWidth
+        SlotUsageAvailable,       // SlotUsage
+        SlotLengthOther,          // SlotLength
+        0x0004,                   // SlotId
+        {                         // SlotCharacteristics1
+            0,                      // CharacteristicsUnknown  :1;
+            0,                      // Provides50Volts         :1;
+            0,                      // Provides33Volts         :1;
+            0,                      // SharedSlot              :1;
+            0,                      // PcCard16Supported       :1;
+            0,                      // CardBusSupported        :1;
+            0,                      // ZoomVideoSupported      :1;
+            0                       // ModemRingResumeSupported:1;
+        },
+        {                         // SlotCharacteristics2
+            0,                      // PmeSignalSupported      :1;
+            0,                      // HotPlugDevicesSupported  :1;
+            0,                      // SmbusSignalSupported    :1;
+            0                       // Reserved                :5;
+        },
+        0x00,                     // SegmentGroupNum
+        0x00,                     // BusNum
+        0                         // DevFuncNum
+    }
+};
+
+
+UINT8 OemGetPcieSlotNumber ()
+{
+    return  sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
+  {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001), STRING_TOKEN(STR_LEMON_C10_DIMM_002)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011), STRING_TOKEN(STR_LEMON_C10_DIMM_012)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021), STRING_TOKEN(STR_LEMON_C10_DIMM_022)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031), STRING_TOKEN(STR_LEMON_C10_DIMM_032)}},
+
+  {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101), STRING_TOKEN(STR_LEMON_C10_DIMM_102)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111), STRING_TOKEN(STR_LEMON_C10_DIMM_112)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121), STRING_TOKEN(STR_LEMON_C10_DIMM_122)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131), STRING_TOKEN(STR_LEMON_C10_DIMM_132)}}
+};
+
+EFI_HII_HANDLE
+EFIAPI
+OemGetPackages (
+  )
+{
+    return HiiAddPackages (
+                            &gEfiCallerIdGuid,
+                            NULL,
+                            OemMiscLibHi1616EvbStrings,
+                            NULL,
+                            NULL
+                            );
+}
+
+
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni
new file mode 100644
index 0000000..491e8ac
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05Strings.uni
@@ -0,0 +1,56 @@
+﻿// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// --*/
+
+/=#
+
+#langdef en-US "English"
+
+//
+// Begin English Language Strings
+//
+#string STR_MEMORY_SUBCLASS_UNKNOWN    #language en-US  "Unknown"
+
+//
+// DIMM Device Locator strings
+
+// D03
+#string STR_LEMON_C10_DIMM_000     #language en-US "J5"
+#string STR_LEMON_C10_DIMM_001     #language en-US "J6"
+#string STR_LEMON_C10_DIMM_002     #language en-US "J7"
+#string STR_LEMON_C10_DIMM_010     #language en-US "J8"
+#string STR_LEMON_C10_DIMM_011     #language en-US "J9"
+#string STR_LEMON_C10_DIMM_012     #language en-US "J10"
+#string STR_LEMON_C10_DIMM_020     #language en-US "J11"
+#string STR_LEMON_C10_DIMM_021     #language en-US "J12"
+#string STR_LEMON_C10_DIMM_022     #language en-US "J13"
+#string STR_LEMON_C10_DIMM_030     #language en-US "J14"
+#string STR_LEMON_C10_DIMM_031     #language en-US "J15"
+#string STR_LEMON_C10_DIMM_032     #language en-US "J16"
+#string STR_LEMON_C10_DIMM_100     #language en-US "J17"
+#string STR_LEMON_C10_DIMM_101     #language en-US "J18"
+#string STR_LEMON_C10_DIMM_102     #language en-US "J19"
+#string STR_LEMON_C10_DIMM_110     #language en-US "J20"
+#string STR_LEMON_C10_DIMM_111     #language en-US "J21"
+#string STR_LEMON_C10_DIMM_112     #language en-US "J22"
+#string STR_LEMON_C10_DIMM_120     #language en-US "J23"
+#string STR_LEMON_C10_DIMM_121     #language en-US "J24"
+#string STR_LEMON_C10_DIMM_122     #language en-US "J25"
+#string STR_LEMON_C10_DIMM_130     #language en-US "J26"
+#string STR_LEMON_C10_DIMM_131     #language en-US "J27"
+#string STR_LEMON_C10_DIMM_132     #language en-US "J28"
+
+//
+// End English Language Strings
+//
+
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
new file mode 100644
index 0000000..c99210c
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
@@ -0,0 +1,127 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/OemMiscLib.h>
+#include <PlatformArch.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/LpcLib.h>
+#include <Library/PcdLib.h>
+REPORT_PCIEDIDVID2BMC  PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
+      {67,0,0,0},
+      {225,0,0,3},
+      {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
+      {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+
+// Right now we only support 1P
+BOOLEAN OemIsSocketPresent (UINTN Socket)
+{
+    UINT32 SocketMask = PcdGet32(PcdSocketMask);
+    return (BOOLEAN)((SocketMask & (1 << Socket)) ? TRUE : FALSE);
+}
+
+
+UINTN OemGetSocketNumber (VOID)
+{
+
+    if(!OemIsMpBoot())
+    {
+        return 1;
+    }
+
+    return 2;
+
+}
+
+
+UINTN OemGetDdrChannel (VOID)
+{
+    return 4;
+}
+
+
+UINTN OemGetDimmSlot(UINTN Socket, UINTN Channel)
+{
+    return 2;
+}
+
+
+// Nothing to do for EVB
+VOID OemPostEndIndicator (VOID)
+{
+
+     DEBUG((EFI_D_ERROR,"M3 release reset CONFIG........."));
+
+     MmioWrite32(0xd0002180, 0x3);
+     MmioWrite32(0xd0002194, 0xa4);
+     MmioWrite32(0xd0000a54, 0x1);
+
+     MicroSecondDelay(10000);
+
+     MmioWrite32(0xd0002108, 0x1);
+     MmioWrite32(0xd0002114, 0x1);
+     MmioWrite32(0xd0002120, 0x1);
+     MmioWrite32(0xd0003108, 0x1);
+
+     MicroSecondDelay(500000);
+     DEBUG((EFI_D_ERROR,"Done\n"));
+
+}
+
+
+
+VOID CoreSelectBoot(VOID)
+{
+    if (!PcdGet64 (PcdTrustedFirmwareEnable))
+    {
+        StartupAp ();
+    }
+
+    return;
+}
+
+BOOLEAN OemIsMpBoot()
+{
+    return PcdGet32(PcdIsMPBoot);
+}
+
+VOID OemLpcInit(VOID)
+{
+    LpcInit();
+    return;
+}
+
+UINT32 OemIsWarmBoot(VOID)
+{
+    return 0;
+}
+
+VOID OemBiosSwitch(UINT32 Master)
+{
+    (VOID)Master;
+    return;
+}
+
+BOOLEAN OemIsNeedDisableExpanderBuffer(VOID)
+{
+    return TRUE;
+}
\ No newline at end of file
diff --git a/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
new file mode 100644
index 0000000..fa81f1e
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
@@ -0,0 +1,56 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemMiscLibHi1616Evb
+  FILE_GUID                      = B9CE7465-21A2-4ecd-B347-BBDDBD098CEE
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemMiscLib
+
+[Sources.common]
+  BoardFeatureD05.c
+  OemMiscLibD05.c
+  BoardFeatureD05Strings.uni
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  TimerLib
+
+[BuildOptions]
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid   ## SOMETIMES_CONSUMES
+
+[Pcd]
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+  gHisiTokenSpaceGuid.PcdSocketMask
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+  gHisiTokenSpaceGuid.PcdIsMPBoot
+
+[FixedPcd.common]
+
+[Guids]
+
+[Protocols]
+
diff --git a/Platforms/Hisilicon/D05/Library/OemNicLib/OemNicLib.c b/Platforms/Hisilicon/D05/Library/OemNicLib/OemNicLib.c
new file mode 100644
index 0000000..80a5c39
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemNicLib/OemNicLib.c
@@ -0,0 +1,66 @@
+/** @file
+*
+*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2015, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Library/OemNicLib.h>
+
+//ETH_PRODUCT_DESC gEthPdtDesc[ETH_MAX_PORT] =
+//{
+//    {FALSE, ETH_INVALID,     ETH_INVALID,     ETH_INVALID,           ETH_INVALID},
+//    {FALSE, ETH_INVALID,     ETH_INVALID,     ETH_INVALID,           ETH_INVALID},
+//    {FALSE, ETH_INVALID,     ETH_INVALID,     ETH_INVALID,           ETH_INVALID},
+//    {FALSE, ETH_INVALID,     ETH_INVALID,     ETH_INVALID,           ETH_INVALID},
+//    {FALSE, ETH_INVALID,     ETH_INVALID,     ETH_INVALID,           ETH_INVALID},
+//    {FALSE, ETH_INVALID,     ETH_INVALID,     ETH_INVALID,           ETH_INVALID},
+//    {TRUE,  ETH_SPEED_1000M, ETH_FULL_DUPLEX, ETH_PHY_MVL88E1512_ID, 0x0},
+//    {FALSE, ETH_INVALID,     ETH_INVALID,     ETH_INVALID,           ETH_INVALID}
+//};
+
+ETH_PRODUCT_DESC gEthPdtDesc[ETH_MAX_PORT] =
+{
+    {TRUE,   ETH_SPEED_10KM,  ETH_FULL_DUPLEX, ETH_INVALID, ETH_INVALID},
+    {TRUE,   ETH_SPEED_10KM,  ETH_FULL_DUPLEX, ETH_INVALID, ETH_INVALID},
+    {FALSE,  ETH_INVALID,     ETH_INVALID,     ETH_INVALID, ETH_INVALID},
+    {FALSE,  ETH_INVALID,     ETH_INVALID,     ETH_INVALID, ETH_INVALID},
+    {TRUE,   ETH_SPEED_1000M, ETH_FULL_DUPLEX, ETH_PHY_MVL88E1512_ID, 0},
+    {TRUE,   ETH_SPEED_1000M, ETH_FULL_DUPLEX, ETH_PHY_MVL88E1512_ID, 1},
+    {FALSE,  ETH_INVALID,     ETH_INVALID,     ETH_INVALID, ETH_INVALID},
+    {FALSE,  ETH_INVALID,     ETH_INVALID,     ETH_INVALID, ETH_INVALID}
+};
+
+UINT32 OemEthFindFirstSP()
+{
+    UINT32 i;
+
+    for (i = 0; i < ETH_MAX_PORT; i++)
+    {
+        if (TRUE == gEthPdtDesc[i].Valid)
+        {
+            return i;
+        }
+    }
+
+    return ETH_INVALID;
+}
+
+ETH_PRODUCT_DESC *OemEthInit(UINT32 port)
+{
+    return (ETH_PRODUCT_DESC *)(&(gEthPdtDesc[port]));
+}
+
+
+BOOLEAN OemIsInitEth(UINT32 Port)
+{
+    return TRUE;
+}
diff --git a/Platforms/Hisilicon/D05/Library/OemNicLib/OemNicLib.inf b/Platforms/Hisilicon/D05/Library/OemNicLib/OemNicLib.inf
new file mode 100644
index 0000000..9fd10b9
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/OemNicLib/OemNicLib.inf
@@ -0,0 +1,39 @@
+#/** @file
+#
+#    Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2015, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = OemNicLib
+  FILE_GUID                      = 520F872C-FFCF-4EF3-AC01-85BDB0816DCE
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemNicLib
+
+[Sources.common]
+  OemNicLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  ArmPkg/ArmPkg.dec
+
+  HwPkg/HwPkg.dec
+
+[LibraryClasses]
+
+[BuildOptions]
+
+[Pcd]
+
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
new file mode 100644
index 0000000..aef8e3d
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.c
@@ -0,0 +1,270 @@
+/** @file
+
+  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+
+  This program and the accompanying materials
+  are licensed and made available under the terms and conditions of the BSD License
+  which accompanies this distribution.  The full text of the license may be found at
+  http://opensource.org/licenses/bsd-license.php
+
+  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+
+**/
+
+#include <Library/PcdLib.h>
+#include <Library/PlatformPciLib.h>
+
+PCI_ROOT_BRIDGE_RESOURCE_APPETURE  mResAppeture[PCIE_MAX_HOSTBRIDGE][PCIE_MAX_ROOTBRIDGE] = {
+ {// HostBridge 0
+  /* Port 0 */
+  {
+      PCI_HB0RB0_ECAM_BASE, //ecam
+      0x80,  //BusBase
+      0x87, //BusLimit
+      PCI_HB0RB0_PCIREGION_BASE, //Membase
+      PCI_HB0RB0_CPUMEMREGIONBASE + PCI_HB0RB0_PCIREGION_SIZE - 1, //Memlimit
+      PCI_HB0RB0_IO_BASE,  //IoBase
+      (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB0_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB0_PCI_BASE),//RbPciBar
+      PCI_HB0RB0_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB0_PCIREGION_BASE + PCI_HB0RB0_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 1 */
+  {
+      PCI_HB0RB1_ECAM_BASE,//ecam
+      0x90,  //BusBase
+      0x97, //BusLimit
+      PCI_HB0RB1_PCIREGION_BASE, //Membase
+      PCI_HB0RB1_CPUMEMREGIONBASE + PCI_HB0RB1_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB1_IO_BASE),  //IoBase
+      (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB1_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB1_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB1_PCI_BASE),  //RbPciBar
+      PCI_HB0RB1_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB1_PCIREGION_BASE + PCI_HB0RB1_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 2 */
+  {
+      PCI_HB0RB2_ECAM_BASE,
+      0x80,  //BusBase
+      0x87, //BusLimit
+      PCI_HB0RB2_CPUMEMREGIONBASE ,//MemBase
+      PCI_HB0RB2_CPUMEMREGIONBASE + PCI_HB0RB2_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB2_IO_BASE),  //IOBase
+      (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB2_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB2_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB2_PCI_BASE),  //RbPciBar
+      PCI_HB0RB2_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB2_PCIREGION_BASE + PCI_HB0RB2_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+
+  /* Port 3 */
+  {
+      PCI_HB0RB3_ECAM_BASE,
+      0xb0,  //BusBase
+      0xb7, //BusLimit
+      (PCI_HB0RB3_ECAM_BASE),  //MemBase
+      (PCI_HB0RB3_CPUMEMREGIONBASE + PCI_HB0RB3_PCIREGION_SIZE - 1), //MemLimit
+      (PCI_HB0RB3_IO_BASE), //IoBase
+      (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB3_IO_SIZE - 1),  //IoLimit
+      PCI_HB0RB3_CPUMEMREGIONBASE,
+      PCI_HB0RB3_CPUIOREGIONBASE,
+      (PCI_HB0RB3_PCI_BASE),  //RbPciBar
+      PCI_HB0RB3_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB3_PCIREGION_BASE + PCI_HB0RB3_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 4 */
+  {
+      PCI_HB0RB4_ECAM_BASE, //ecam
+      0x88,  //BusBase
+      0x8f, //BusLimit
+      PCI_HB0RB4_CPUMEMREGIONBASE, //Membase
+      PCI_HB0RB4_CPUMEMREGIONBASE + PCI_HB0RB4_PCIREGION_SIZE - 1, //Memlimit
+      PCI_HB0RB4_IO_BASE,  //IoBase
+      (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB4_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB4_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB4_PCI_BASE),  //RbPciBar
+      PCI_HB0RB4_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB4_PCIREGION_BASE + PCI_HB0RB4_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 5 */
+  {
+      PCI_HB0RB5_ECAM_BASE,//ecam
+      0x0,  //BusBase
+      0x7, //BusLimit
+      PCI_HB0RB5_CPUMEMREGIONBASE, //Membase
+      PCI_HB0RB5_CPUMEMREGIONBASE + PCI_HB0RB5_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB5_IO_BASE),  //IoBase
+      (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB5_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB5_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB5_PCI_BASE),  //RbPciBar
+      PCI_HB0RB5_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB5_PCIREGION_BASE + PCI_HB0RB5_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 6 */
+  {
+      PCI_HB0RB6_ECAM_BASE,
+      0xC0,  //BusBase
+      0xC7, //BusLimit
+      PCI_HB0RB6_PCIREGION_BASE ,//MemBase
+      PCI_HB0RB6_CPUMEMREGIONBASE + PCI_HB0RB6_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB6_IO_BASE),  //IOBase
+      (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB6_IO_SIZE - 1), //IoLimit
+      PCI_HB0RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB0RB6_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB0RB6_PCI_BASE),  //RbPciBar
+      PCI_HB0RB6_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB6_PCIREGION_BASE + PCI_HB0RB6_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+
+  /* Port 7 */
+  {
+      PCI_HB0RB7_ECAM_BASE,
+      0x90,  //BusBase
+      0x97, //BusLimit
+      PCI_HB0RB7_CPUMEMREGIONBASE,  //MemBase
+      PCI_HB0RB7_CPUMEMREGIONBASE + PCI_HB0RB7_PCIREGION_SIZE - 1, //MemLimit
+      (PCI_HB0RB7_IO_BASE), //IoBase
+      (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB7_IO_SIZE - 1),  //IoLimit
+      PCI_HB0RB7_CPUMEMREGIONBASE,
+      PCI_HB0RB7_CPUIOREGIONBASE,
+      (PCI_HB0RB7_PCI_BASE),  //RbPciBar
+      PCI_HB0RB7_PCIREGION_BASE, //PciRegionbase
+      PCI_HB0RB7_PCIREGION_BASE + PCI_HB0RB7_PCIREGION_SIZE - 1 //PciRegionlimit
+  }
+ },
+{// HostBridge 1
+  /* Port 0 */
+  {
+      PCI_HB1RB0_ECAM_BASE,
+      0x80,  //BusBase
+      0x87, //BusLimit
+      (PCI_HB1RB0_ECAM_BASE),  //MemBase
+      (PCI_HB1RB0_CPUMEMREGIONBASE + PCI_HB1RB0_PCIREGION_SIZE - 1), //MemLimit
+      PCI_HB1RB0_IO_BASE, //IoBase
+      (PCI_HB0RB0_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB0_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB0_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB0_PCI_BASE),  //RbPciBar
+      PCI_HB1RB0_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 1 */
+  {
+      PCI_HB1RB1_ECAM_BASE,
+      0x90,  //BusBase
+      0x97, //BusLimit
+      (PCI_HB1RB1_ECAM_BASE),  //MemBase
+      (PCI_HB1RB1_CPUMEMREGIONBASE + PCI_HB1RB1_PCIREGION_SIZE - 1), //MemLimit
+      PCI_HB1RB1_IO_BASE, //IoBase
+      (PCI_HB0RB1_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB1_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB1_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB1_PCI_BASE),  //RbPciBar
+      PCI_HB1RB1_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB1_PCIREGION_BASE + PCI_HB1RB1_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 2 */
+  {
+      PCI_HB1RB2_ECAM_BASE,
+      0x10,  //BusBase
+      0x1f, //BusLimit
+      PCI_HB1RB2_CPUMEMREGIONBASE,  //MemBase
+      PCI_HB1RB2_CPUMEMREGIONBASE + PCI_HB1RB2_PCIREGION_SIZE - 1, //MemLimit
+      PCI_HB1RB2_IO_BASE, //IoBase
+      (PCI_HB0RB2_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB2_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB2_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB2_PCI_BASE),  //RbPciBar
+      PCI_HB1RB2_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB2_PCIREGION_BASE + PCI_HB1RB2_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+
+  /* Port 3 */
+  {
+      PCI_HB1RB3_ECAM_BASE,
+      0xb0,  //BusBase
+      0xb7, //BusLimit
+      (PCI_HB1RB3_ECAM_BASE),  //MemBase
+      (PCI_HB1RB3_CPUMEMREGIONBASE + PCI_HB1RB3_PCIREGION_SIZE - 1), //MemLimit
+      PCI_HB1RB3_IO_BASE, //IoBase
+      (PCI_HB0RB3_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB3_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB3_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB3_PCI_BASE),  //RbPciBar
+      PCI_HB1RB3_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB3_PCIREGION_BASE + PCI_HB1RB3_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 4 */
+  {
+      PCI_HB1RB4_ECAM_BASE,
+      0x20,  //BusBase
+      0x2f, //BusLimit
+      PCI_HB1RB4_CPUMEMREGIONBASE,  //MemBase
+      PCI_HB1RB4_CPUMEMREGIONBASE + PCI_HB1RB4_PCIREGION_SIZE - 1, //MemLimit
+      PCI_HB1RB4_IO_BASE, //IoBase
+      (PCI_HB0RB4_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB4_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB4_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB4_PCI_BASE),  //RbPciBar
+      PCI_HB1RB4_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB4_PCIREGION_BASE + PCI_HB1RB4_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 5 */
+  {
+      PCI_HB1RB5_ECAM_BASE,
+      0x30,  //BusBase
+      0x3f, //BusLimit
+      PCI_HB1RB5_CPUMEMREGIONBASE,  //MemBase
+      PCI_HB1RB5_CPUMEMREGIONBASE + PCI_HB1RB5_PCIREGION_SIZE - 1, //MemLimit
+      PCI_HB1RB5_IO_BASE, //IoBase
+      (PCI_HB0RB5_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB5_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB5_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB5_PCI_BASE),  //RbPciBar
+      PCI_HB1RB5_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB5_PCIREGION_BASE + PCI_HB1RB5_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+  /* Port 6 */
+  {
+      PCI_HB1RB6_ECAM_BASE,
+      0xa8,  //BusBase
+      0xaf, //BusLimit
+      (PCI_HB1RB6_ECAM_BASE),  //MemBase
+      PCI_HB1RB6_CPUMEMREGIONBASE + PCI_HB1RB6_PCIREGION_SIZE - 1, //MemLimit
+      PCI_HB1RB6_IO_BASE, //IoBase
+      (PCI_HB0RB6_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB6_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB6_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB6_PCI_BASE),  //RbPciBar
+      PCI_HB1RB6_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB0_PCIREGION_BASE + PCI_HB1RB0_PCIREGION_SIZE - 1 //PciRegionlimit
+  },
+
+  /* Port 7 */
+  {
+      PCI_HB1RB7_ECAM_BASE,
+      0xb8,  //BusBase
+      0xbf, //BusLimit
+      (PCI_HB1RB7_ECAM_BASE),  //MemBase
+      PCI_HB1RB7_CPUMEMREGIONBASE + PCI_HB1RB7_PCIREGION_SIZE - 1, //MemLimit
+      PCI_HB1RB7_IO_BASE, //IoBase
+      (PCI_HB0RB7_CPUIOREGIONBASE + PCI_HB0RB0_IO_SIZE - 1), //IoLimit
+      PCI_HB1RB7_CPUMEMREGIONBASE, //CpuMemRegionBase
+      PCI_HB1RB7_CPUIOREGIONBASE,  //CpuIoRegionBase
+      (PCI_HB1RB7_PCI_BASE),  //RbPciBar
+      PCI_HB1RB7_PCIREGION_BASE, //PciRegionbase
+      PCI_HB1RB7_PCIREGION_BASE + PCI_HB1RB7_PCIREGION_SIZE - 1 //PciRegionlimit
+  }
+
+ }
+};
+
diff --git a/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
new file mode 100644
index 0000000..4a71238
--- /dev/null
+++ b/Platforms/Hisilicon/D05/Library/PlatformPciLib/PlatformPciLib.inf
@@ -0,0 +1,183 @@
+## @file
+#
+#  Copyright (c) 2016, Hisilicon Limited. All rights reserved.<BR>
+#  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
+#
+#  This program and the accompanying materials
+#  are licensed and made available under the terms and conditions of the BSD License
+#  which accompanies this distribution. The full text of the license may be found at
+#  http://opensource.org/licenses/bsd-license.php
+#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PlatformPciLib
+  FILE_GUID                      = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+
+[Sources]
+  PlatformPciLib.c
+
+[Packages]
+  MdePkg/MdePkg.dec
+  OpenPlatformPkg/Chips/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+
+[FixedPcd]
+  gHisiTokenSpaceGuid.PcdHb1BaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciConfigurationSpaceSize
+  gHisiTokenSpaceGuid.PciHb0Rb0Base
+  gHisiTokenSpaceGuid.PciHb0Rb1Base
+  gHisiTokenSpaceGuid.PciHb0Rb2Base
+  gHisiTokenSpaceGuid.PciHb0Rb3Base
+  gHisiTokenSpaceGuid.PciHb0Rb4Base
+  gHisiTokenSpaceGuid.PciHb0Rb5Base
+  gHisiTokenSpaceGuid.PciHb0Rb6Base
+  gHisiTokenSpaceGuid.PciHb0Rb7Base
+  gHisiTokenSpaceGuid.PciHb1Rb0Base
+  gHisiTokenSpaceGuid.PciHb1Rb1Base
+  gHisiTokenSpaceGuid.PciHb1Rb2Base
+  gHisiTokenSpaceGuid.PciHb1Rb3Base
+  gHisiTokenSpaceGuid.PciHb1Rb4Base
+  gHisiTokenSpaceGuid.PciHb1Rb5Base
+  gHisiTokenSpaceGuid.PciHb1Rb6Base
+  gHisiTokenSpaceGuid.PciHb1Rb7Base
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionBaseAddress
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionBaseAddress
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6PciRegionSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7PciRegionSize
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuMemRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuMemRegionBase
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6CpuIoRegionBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7CpuIoRegionBase
+
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb0IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb1IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb2IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb3IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb4IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb5IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb6IoSize
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoBase
+  gHisiTokenSpaceGuid.PcdHb0Rb7IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb0IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb1IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb2IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb3IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb4IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb5IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb6IoSize
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoBase
+  gHisiTokenSpaceGuid.PcdHb1Rb7IoSize
+
