From patchwork Wed Oct 19 01:31:26 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 78157 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp4581qge; Tue, 18 Oct 2016 18:32:35 -0700 (PDT) X-Received: by 10.159.32.227 with SMTP id 90mr535646uaa.147.1476840755352; Tue, 18 Oct 2016 18:32:35 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id i1si16486244vkb.15.2016.10.18.18.32.35; Tue, 18 Oct 2016 18:32:35 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id F14186163B; Wed, 19 Oct 2016 01:32:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 627776162F; Wed, 19 Oct 2016 01:32:30 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 5BC8261620; Wed, 19 Oct 2016 01:32:27 +0000 (UTC) Received: from mail-pf0-f176.google.com (mail-pf0-f176.google.com [209.85.192.176]) by lists.linaro.org (Postfix) with ESMTPS id 5D4C661620 for ; Wed, 19 Oct 2016 01:31:57 +0000 (UTC) Received: by mail-pf0-f176.google.com with SMTP id r16so5908171pfg.1 for ; Tue, 18 Oct 2016 18:31:57 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ER1XQXaZnUIsAAPcBy63AHBoIx16GShLYYh4S7qMjqc=; b=bao4aXZX+OuzkuJIG6m+OIkw59aIiT8/4DL7QOhCtJicAKxOoXairc/ltQnyGz1m/n GDOL0v23BNJSmu8k/UW+s13oRupqbcigFBYzi2fBcow297Qa/1TXmQ/m8Oc8mcwUOq28 LSmN/lAl4i3EaTFXOBEIglm6fZ+4XICTds6Y38gu+hRW4w39BJs2sc5/x2GVGi11Ekp5 1T+5dcCh6LQwyiCVVqnxiTF8XpABVtakd7g9nNJi8r9DzRxJT0OQdfeOnMTndpP2na+K JHmxvZyR1xKJiyHX0GOCN3vJOKll9T083M8Sx7jRY3UB0wO1V/QCAb4+cfTxkHOI40JI bNKA== X-Gm-Message-State: AA6/9RkUZ3lKPexsTLw1Yt0q9rdQrdI6bGJbOEf9RdgUlPVIyX1Cnba0vZb8zGvxy5Ku1g7GHcA= X-Received: by 10.98.194.68 with SMTP id l65mr6011972pfg.159.1476840716684; Tue, 18 Oct 2016 18:31:56 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id ad15sm58858808pac.33.2016.10.18.18.31.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 18 Oct 2016 18:31:56 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Wed, 19 Oct 2016 09:31:26 +0800 Message-Id: <1476840686-94794-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1476840686-94794-1-git-send-email-heyi.guo@linaro.org> References: <1476840686-94794-1-git-send-email-heyi.guo@linaro.org> Cc: Peicong Li Subject: [Linaro-uefi] [PATCH v2 13/24] Hisilicon/Serdes: add support for D05 X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Modify OemGetSerdesParam interface to support D05, for it has 2 sockets on the board, and each socket has 2 IO super clusters. The interface is modified to support getting serdes parameter for both IO super clusters (denoted as A and B) on each socket. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Peicong Li --- .../Type09/MiscSystemSlotDesignationFunction.c | 15 ++++++++------- Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h | 2 +- Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h | 2 +- .../Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c | 8 ++++---- .../D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c | 6 +++--- 5 files changed, 17 insertions(+), 16 deletions(-) diff --git a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c index a0e3de3..bc988d8 100644 --- a/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c +++ b/Chips/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/Type09/MiscSystemSlotDesignationFunction.c @@ -73,9 +73,10 @@ UpdateSlotUsage( ) { EFI_STATUS Status; - serdes_param_t sSerdesParam; + serdes_param_t SerdesParamA; + serdes_param_t SerdesParamB; - Status = OemGetSerdesParam (&sSerdesParam); + Status = OemGetSerdesParam (&SerdesParamA, &SerdesParamB, 0); if(EFI_ERROR(Status)) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] OemGetSerdesParam failed %r\n", __FUNCTION__, __LINE__, Status)); @@ -85,7 +86,7 @@ UpdateSlotUsage( // // PCIE0 // - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && sSerdesParam.hilink1_mode == EM_HILINK1_PCIE0_8LANE) + if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie0Data) && SerdesParamA.hilink1_mode == EM_HILINK1_PCIE0_8LANE) { InputData->CurrentUsage = SlotUsageAvailable; } @@ -95,7 +96,7 @@ UpdateSlotUsage( // if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie1Data) { - if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) + if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) { InputData->SlotDataBusWidth = SlotDataBusWidth4X; } @@ -106,12 +107,12 @@ UpdateSlotUsage( // if ((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie2Data) { - if (sSerdesParam.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) + if (SerdesParamA.hilink0_mode == EM_HILINK0_PCIE1_4LANE_PCIE2_4LANE) { InputData->SlotDataBusWidth = SlotDataBusWidth4X; InputData->CurrentUsage = SlotUsageAvailable; } - else if (sSerdesParam.hilink2_mode == EM_HILINK2_PCIE2_8LANE) + else if (SerdesParamA.hilink2_mode == EM_HILINK2_PCIE2_8LANE) { InputData->CurrentUsage = SlotUsageAvailable; } @@ -120,7 +121,7 @@ UpdateSlotUsage( // // PCIE3 // - if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && sSerdesParam.hilink5_mode == EM_HILINK5_PCIE3_4LANE) + if (((UINTN)InputData == (UINTN)&MiscSystemSlotDesignationPcie3Data) && SerdesParamA.hilink5_mode == EM_HILINK5_PCIE3_4LANE) { InputData->CurrentUsage = SlotUsageAvailable; } diff --git a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h index 700d40e..3bd5a0f 100755 --- a/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h +++ b/Chips/Hisilicon/Hi1610/Include/Library/SerdesLib.h @@ -82,7 +82,7 @@ typedef struct { UINT32 DsCfg; } SERDES_POLARITY_INVERT; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; UINT32 GetEthType(UINT8 EthChannel); diff --git a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h index 070934b..b6c7e20 100644 --- a/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h +++ b/Chips/Hisilicon/Pv660/Include/Library/SerdesLib.h @@ -76,7 +76,7 @@ typedef struct { } SERDES_POLARITY_INVERT; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param); +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId); extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[]; extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[]; UINT32 GetEthType(UINT8 EthChannel); diff --git a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c index d4aa84a..2dc1464 100644 --- a/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c +++ b/Platforms/Hisilicon/D02/Library/OemMiscLibD02/BoardFeatureD02.c @@ -59,15 +59,15 @@ serdes_param_t gSerdesParam = { .hilink5_mode = EM_HILINK5_SAS1_4LANE, }; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) { - if (NULL == Param) + if (ParamA == NULL) { - DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); + DEBUG((EFI_D_ERROR, "[%a]:[%dL] ParamA == NULL!\n", __FUNCTION__, __LINE__)); return EFI_INVALID_PARAMETER; } - (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param)); + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); return EFI_SUCCESS; } diff --git a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c index 23c55e1..7e4b9d0 100644 --- a/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c +++ b/Platforms/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c @@ -75,15 +75,15 @@ serdes_param_t gSerdesParam1 = { .use_ssc = 0, }; -EFI_STATUS OemGetSerdesParam (serdes_param_t *Param) +EFI_STATUS OemGetSerdesParam (serdes_param_t *ParamA, serdes_param_t *ParamB, UINT32 SocketId) { - if (NULL == Param) + if (ParamA == NULL) { DEBUG((EFI_D_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__)); return EFI_INVALID_PARAMETER; } - (VOID) CopyMem(Param, &gSerdesParam, sizeof(*Param)); + (VOID) CopyMem(ParamA, &gSerdesParam, sizeof(*ParamA)); return EFI_SUCCESS; }