From patchwork Thu Oct 27 03:15:06 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: gary guo X-Patchwork-Id: 79575 Delivered-To: patch@linaro.org Received: by 10.140.97.247 with SMTP id m110csp404659qge; Wed, 26 Oct 2016 20:16:51 -0700 (PDT) X-Received: by 10.55.217.19 with SMTP id u19mr3991636qki.312.1477538211338; Wed, 26 Oct 2016 20:16:51 -0700 (PDT) Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id g3si3021160qtd.71.2016.10.26.20.16.51; Wed, 26 Oct 2016 20:16:51 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 08F1B61D34; Thu, 27 Oct 2016 03:16:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2 autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 0DC6160E32; Thu, 27 Oct 2016 03:16:22 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 07B8660CD8; Thu, 27 Oct 2016 03:16:19 +0000 (UTC) Received: from mail-pf0-f181.google.com (mail-pf0-f181.google.com [209.85.192.181]) by lists.linaro.org (Postfix) with ESMTPS id 31E3260CB7 for ; Thu, 27 Oct 2016 03:16:18 +0000 (UTC) Received: by mail-pf0-f181.google.com with SMTP id n85so8210097pfi.1 for ; Wed, 26 Oct 2016 20:16:18 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=c5lrM1eXJpBUkmsMxkfJq+PX59DWjwnW/71JTfO2ANI=; b=PCFM2K+AxQyTIfg+Bx1vYIB/5IeHbFqV2lJTAG64LDcwvajV5j9zualYwIK4+dJM7a B+2wXQ5oj7HBhrpYleA8G6SIY2yihd6Mn2uDCK5ekQHzVmou5vcZfDEEqfhRXnhPbKwQ dipKkCO2xwpu+7JUUYtJ/1c7P6skv9HqzGNwuFVa7TQaoeg+HPbUY6MipPRUyyvBpYy7 6FF5+dZeR220UNci6Ci5snL/k6AQPMCa5KnWh5awtoORwohVpCEYW2TLunmnKJ6yFVqZ oI1bntp595c+yn35JIPLyL2W9yxW3ydU6sb2I0umK4W0vQ1DydZo5B8Rtc5M3OLUiEU2 kkSw== X-Gm-Message-State: ABUngvdUfzKTJ5veeKekeEcfBl6mRPo0Kc5Gp5uK+mzcNHZHhjVVV4MBDjbh0Bh9IWBIBJpldo4= X-Received: by 10.98.39.66 with SMTP id n63mr10305048pfn.72.1477538177526; Wed, 26 Oct 2016 20:16:17 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id h5sm7091734pfg.86.2016.10.26.20.16.15 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 26 Oct 2016 20:16:17 -0700 (PDT) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Thu, 27 Oct 2016 11:15:06 +0800 Message-Id: <1477538129-118465-2-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477538129-118465-1-git-send-email-heyi.guo@linaro.org> References: <1477538129-118465-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH 03/26] D02/D03/D05: Support Spd mirror mode X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Add Spd mirror mode related registers definitioni Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 955b9e4..305040a 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -161,6 +161,7 @@ typedef struct _DDR_DIMM{ UINT16 DimmSize; UINT16 DimmSpeed; UINT32 RankSize; + UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode struct DDR_RANK Rank[MAX_RANK_DIMM]; }DDR_DIMM; @@ -336,7 +337,7 @@ typedef struct _NVRAM{ typedef struct _MEMORY{ UINT8 Config0; UINT8 marginTest; - UINT8 Config1[5]; + UINT8 Config1[6]; UINT32 Config2; }MEMORY; @@ -789,6 +790,8 @@ struct ODT_ACTIVE_STRUCT { #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK +#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM +#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM #define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte #define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte