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[54.225.227.206]) by mx.google.com with ESMTP id f61si10717955qtd.103.2016.11.14.03.32.21; Mon, 14 Nov 2016 03:32:22 -0800 (PST) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id BB1D2608C4; Mon, 14 Nov 2016 11:32:21 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-1.9 required=5.0 tests=BAYES_00, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 0D4B0608CF; Mon, 14 Nov 2016 11:31:50 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id A25DB60D6A; Mon, 14 Nov 2016 11:31:46 +0000 (UTC) Received: from mail-pg0-f54.google.com (mail-pg0-f54.google.com [74.125.83.54]) by lists.linaro.org (Postfix) with ESMTPS id EB480608CA for ; Mon, 14 Nov 2016 11:31:21 +0000 (UTC) Received: by mail-pg0-f54.google.com with SMTP id 3so53517097pgd.0 for ; Mon, 14 Nov 2016 03:31:21 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=UmhY0u4oJoyvF8f7djckTCd4hV18Z+68pdgiSHWKwvI=; b=VMthhYM0yvP0rOnJ7fW/6cQUImYZFEhzNUbmCpINHgMtS1avfgr1DsDfLh63mRt1+r 7fymsXzsNbtbwaijghY5E7dUrCIhkiP5FUcW1ZU1itiGafMF49CWngxvh0h+IXtpXyde taJ/OYXWVlorpvwqlKr8bxoWIQDhIV69UC6u3Ss/CjFXlbxoYa6AWVo3E90qTE761zvX zYF4UAMd7eLFHAC7weKxkCqo2JmjRsjNezsWfR9vGe7aEbzUZzeakIv54+BGLgh65/iV 4TAJvm+uaxnO7Tu1EK3FQzWMXqIyhBMZkFMQJ9PmNDVwA5hB8bh911Nc/eQ11lTGv1iW hu3g== X-Gm-Message-State: ABUngveZaaIyCDgVQEz0jdVTxAZNpwTKCFnprmxsS48cCd4PXyQd8RkPiORO1dPp1Xc1J8Ix0Wg= X-Received: by 10.99.139.199 with SMTP id j190mr68384542pge.115.1479123081266; Mon, 14 Nov 2016 03:31:21 -0800 (PST) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id g82sm34663209pfb.43.2016.11.14.03.31.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 14 Nov 2016 03:31:20 -0800 (PST) From: Heyi Guo To: linaro-uefi@lists.linaro.org Date: Mon, 14 Nov 2016 19:29:30 +0800 Message-Id: <1479122995-50330-4-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1479122995-50330-1-git-send-email-heyi.guo@linaro.org> References: <1479122995-50330-1-git-send-email-heyi.guo@linaro.org> Subject: [Linaro-uefi] [PATCH 03/28] D02/D03/D05: Support Spd mirror mode X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" Add Spd mirror mode related registers definition Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Heyi Guo --- Chips/Hisilicon/Include/Library/HwMemInitLib.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Chips/Hisilicon/Include/Library/HwMemInitLib.h b/Chips/Hisilicon/Include/Library/HwMemInitLib.h index 955b9e4..fbd13f8 100644 --- a/Chips/Hisilicon/Include/Library/HwMemInitLib.h +++ b/Chips/Hisilicon/Include/Library/HwMemInitLib.h @@ -161,6 +161,7 @@ typedef struct _DDR_DIMM{ UINT16 DimmSize; UINT16 DimmSpeed; UINT32 RankSize; + UINT8 SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode struct DDR_RANK Rank[MAX_RANK_DIMM]; }DDR_DIMM; @@ -337,6 +338,7 @@ typedef struct _MEMORY{ UINT8 Config0; UINT8 marginTest; UINT8 Config1[5]; + UINT8 ErrorBypass; //register of spd mirror mode UINT32 Config2; }MEMORY; @@ -789,6 +791,8 @@ struct ODT_ACTIVE_STRUCT { #define SPD_FTB_TAA_DDR4 123 // Fine offset for TAA #define SPD_FTB_MAX_TCK_DDR4 124 // Fine offset for max TCK #define SPD_FTB_MIN_TCK_DDR4 125 // Fine offset for min TCK +#define SPD_MIRROR_UNBUFFERED 131 // Unbuffered:Address Mapping from Edge Connector to DRAM +#define SPD_MIRROR_REGISTERED 136 // Registered:Address Address Mapping from Register to DRAM #define SPD_MMID_LSB_DDR4 320 // Module Manufacturer ID Code, Least Significant Byte #define SPD_MMID_MSB_DDR4 321 // Module Manufacturer ID Code, Most Significant Byte