| Message ID | 1490015485-53685-3-git-send-email-chenhui.sun@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | D02/D03 platforms bug fix | expand |
On Mon, Mar 20, 2017 at 09:11:06PM +0800, Chenhui Sun wrote: > The I350 Hilink state is not stable, so we need to modify the > rx_tx_status_cfg to fix it, or the I350 enumeration fail may happen. > > Contributed-under: TianoCore Contribution Agreement 1.0 > Signed-off-by: shaochangliang <shaochangliang@huawei.com> > Signed-off-by: Heyi Guo <heyi.guo@linaro.org> > Signed-off-by: Yi Li <phoenix.liyi@huawei.com> > --- > Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 5 +++++ > 1 file changed, 5 insertions(+) > > diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c > index 0b5a659..3bad240 100644 > --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c > +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c > @@ -23,6 +23,9 @@ > #include <Library/TimerLib.h> > > #define PCIE_SYS_REG_OFFSET 0x1000 > +#define MUX_LOS_ALOS_REG_OFFSET 0x508 > +#define CH_RXTX_STATUS_CFG_EN BIT1 > +#define CH_RXTX_STATUS_CFG BIT2 > > static PCIE_INIT_CFG mPcieIntCfg; > UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; > @@ -470,6 +473,8 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) > RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); > Value |= (1 << 20); //bit 20: rxvalid enable > RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); > + RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i*0x4, \ Why 0x4? Can we have a descriptive #define instead? Also, spaces around '*'. > + CH_RXTX_STATUS_CFG_EN|CH_RXTX_STATUS_CFG); Spaces around '|'. > } > PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); > RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090); > -- > 1.9.1 >
diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 0b5a659..3bad240 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -23,6 +23,9 @@ #include <Library/TimerLib.h> #define PCIE_SYS_REG_OFFSET 0x1000 +#define MUX_LOS_ALOS_REG_OFFSET 0x508 +#define CH_RXTX_STATUS_CFG_EN BIT1 +#define CH_RXTX_STATUS_CFG BIT2 static PCIE_INIT_CFG mPcieIntCfg; UINT64 pcie_subctrl_base[2] = {0xb0000000, BASE_4TB + 0xb0000000}; @@ -470,6 +473,8 @@ VOID PciePcsInit(UINT32 soctype, UINT32 HostBridgeNum, UINT32 Port) RegRead(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); Value |= (1 << 20); //bit 20: rxvalid enable RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + PCS_SDS_CFG_REG + i * SDS_CFG_STRIDE, Value); + RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + MUX_LOS_ALOS_REG_OFFSET + i*0x4, \ + CH_RXTX_STATUS_CFG_EN|CH_RXTX_STATUS_CFG); } PcieRxValidCtrl(soctype, HostBridgeNum, Port, 0); RegWrite(PCIE_PHY_BASE_1610[HostBridgeNum][Port] + 0x264, 0x3D090);