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[54.225.227.206]) by mx.google.com with ESMTP id k62si9134895qkb.492.2017.09.19.07.15.06; Tue, 19 Sep 2017 07:15:07 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 8DE4F62D1B; Tue, 19 Sep 2017 14:15:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, RCVD_IN_SORBS_SPAM, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id 27B0D62F1C; Tue, 19 Sep 2017 14:10:29 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 73C3162CE2; Tue, 19 Sep 2017 14:05:51 +0000 (UTC) Received: from mail-pf0-f182.google.com (mail-pf0-f182.google.com [209.85.192.182]) by lists.linaro.org (Postfix) with ESMTPS id 026C362CFA for ; Tue, 19 Sep 2017 14:05:26 +0000 (UTC) Received: by mail-pf0-f182.google.com with SMTP id d187so28615pfg.11 for ; Tue, 19 Sep 2017 07:05:25 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=BOWpWyonPQnh3zuz2/OjETGCg9YULg6xOjp4pkr9t1g=; b=NOWIOJxEmdzkVnl+uniHjreW4Iywk8PinGEtdUaO0C6nA1MoVNOafFTzU+Waw9RO+D 05Jl9RX88WZBrRZxXooaxa9rdlY1m0Wwi/2YHO3LXwzFub1GrIyPcdCSUC7F7CENldx1 LLngL3hQhXjgm2wkHd8TEPQvqHp9VEEe3hG2686AyAvCzbkFMiiRl5GZG8HpCMmqUkd5 ekhwmP6aHVAj/IAaJLQhZVZzSRfvsRU/gcFcuqh7LaBRiQv/9ai60Lue5KwpumEjChN9 ql3VjxSslYrllY2OjQCWlvgfvU/S8ZEEu9dvZQVDu2KAGsqvO3Dn2Jb3LQm+JOcIBMJr HiyQ== X-Gm-Message-State: AHPjjUi6OFI4KGqVxh3zW82aKFgIQcro07LeStYk86MLClLH1ybtx4mj GBEZHV6E2vQCym+D1fe4l5GN+LVb X-Google-Smtp-Source: AOwi7QA08oz4emDCNDG4KNcmwaUpZZKV7+KyBFiDNe/XjMGiFym5WsY/PFRn3qqyWgigbSDS2kyDbQ== X-Received: by 10.99.99.197 with SMTP id x188mr1450270pgb.421.1505829925123; Tue, 19 Sep 2017 07:05:25 -0700 (PDT) Received: from localhost.localdomain ([119.145.15.121]) by smtp.gmail.com with ESMTPSA id 13sm4390439pfm.138.2017.09.19.07.05.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 19 Sep 2017 07:05:24 -0700 (PDT) From: Heyi Guo To: leif.lindholm@linaro.org, linaro-uefi@lists.linaro.org, graeme.gregory@linaro.org Date: Tue, 19 Sep 2017 21:56:18 +0800 Message-Id: <1505829398-52214-13-git-send-email-heyi.guo@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> References: <1505829398-52214-1-git-send-email-heyi.guo@linaro.org> Cc: huangming23@huawei.com, Yan Zhang , zhangjinsong2@huawei.com, guoheyi@huawei.com, wanghuiqiang@huawei.com Subject: [Linaro-uefi] [linaro-uefi v1 12/32] Disable PCIE ASPM X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" From: Yan Zhang In order to replace command line parameter pcie_aspm=off, BIOS needs to disable Pcie Aspm support during Pcie initilization. Change-Id: Ie58f0616563318a86f2248e8eb5de29bf2c621c6 Signed-off-by: Yan Zhang --- .../Hi1610/Drivers/PcieInit1610/PcieInitLib.c | 70 ++++++++++++++++++++++ .../Hi1610/Drivers/PcieInit1610/PcieInitLib.h | 2 + Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h | 2 + 3 files changed, 74 insertions(+) diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c index 8ab7fa3..e30f5d7 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.c @@ -1077,6 +1077,73 @@ DisableRcOptionRom ( return; } +VOID +PcieDbiCs2Enable( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN BOOLEAN Val + ) +{ + UINT32 RegVal; + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21, RegVal); + if (Val) { + RegVal = RegVal | BIT2; + /*BIT2: DBI Chip Select indicator. 0 indicates CS, 1 indicates CS2.*/ + } else { + RegVal = RegVal & (~BIT2); + } + RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21, RegVal); +} + +BOOLEAN +PcieDBIReadOnlyWriteEnable( + IN UINT32 HostBridgeNum, + IN UINT32 Port + ) +{ + UINT32 Val; + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, Val); + if (Val == 0x1) { + return TRUE; + } else { + RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, 0x1); + /*Delay 10us to make sure the PCIE device have enouph time to response. */ + MicroSecondDelay(10); + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_DBI_READ_ONLY_WRITE_ENABLE, Val); + if (Val == 0x1) { + return TRUE; + } + } + DEBUG ((DEBUG_ERROR,"PcieDBIReadOnlyWriteEnable Fail!!!\n")); + return FALSE; +} +VOID +PcieASPMSupportDisable( + IN UINT32 HostBridgeNum, + IN UINT32 Port, + IN UINT8 Val + ) +{ + PCIE_EP_PCIE_CAP3_U pcie_cap3; + if (Port >= PCIE_MAX_ROOTBRIDGE) { + DEBUG ((DEBUG_ERROR,"Port is not valid\n")); + return; + } + if (!PcieDBIReadOnlyWriteEnable (HostBridgeNum, Port)) { + DEBUG ((DEBUG_INFO,"PcieDeEmphasisLevelSet ReadOnly Reg do not Enable!!!\n")); + return; + } + PcieDbiCs2Enable (HostBridgeNum, Port, FALSE); + + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, pcie_cap3.UInt32); + pcie_cap3.Bits.active_state_power_management = Val; + RegWrite (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, pcie_cap3.UInt32); + RegRead (PCIE_APB_SLAVE_BASE_1610[HostBridgeNum][Port] + PCIE_EP_PCIE_CAP3_REG, pcie_cap3.UInt32); + DEBUG ((DEBUG_INFO,"ASPI active state power management: %d\n", pcie_cap3.Bits.active_state_power_management)); + + PcieDbiCs2Enable (HostBridgeNum, Port, TRUE); +} + EFI_STATUS EFIAPI PciePortInit ( @@ -1134,6 +1201,9 @@ PciePortInit ( /* disable link up interrupt */ (VOID)PcieMaskLinkUpInit(soctype, HostBridgeNum, PortIndex); + //disable ASPM + PcieASPMSupportDisable (HostBridgeNum, PortIndex, PCIE_ASPM_DISABLE); + /* Pcie Equalization*/ (VOID)PcieEqualization(soctype ,HostBridgeNum, PortIndex); diff --git a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h index 9a0f636..e96c53c 100644 --- a/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h +++ b/Chips/Hisilicon/Hi1610/Drivers/PcieInit1610/PcieInitLib.h @@ -77,6 +77,8 @@ #define RegWrite(addr,data) MmioWrite32((addr), (data)) #define RegRead(addr,data) ((data) = MmioRead32 (addr)) +#define PCIE_ASPM_DISABLE 0x0 +#define PCIE_ASPM_ENABLE 0x1 typedef struct tagPcieDebugInfo { diff --git a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h index bf57652..c8b9781 100644 --- a/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h +++ b/Chips/Hisilicon/Include/Regs/HisiPcieV1RegOffset.h @@ -135,6 +135,7 @@ #define PCIE_EEP_PORTLOGIC53_REG (0x888) #define PCIE_EEP_GEN3_CONTRL_REG (0x890) #define PCIE_EEP_PIPE_LOOPBACK_REG (0x8B8) +#define PCIE_DBI_READ_ONLY_WRITE_ENABLE (0x8BC) #define PCIE_EEP_PORTLOGIC54_REG (0x900) #define PCIE_EEP_PORTLOGIC55_REG (0x904) #define PCIE_EEP_PORTLOGIC56_REG (0x908) @@ -12556,6 +12557,7 @@ typedef union tagPortlogic93 #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG (PCIE_SUBCTRL_BASE + 0x1018) #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG (PCIE_SUBCTRL_BASE + 0x101C) #define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY7_REG (PCIE_SUBCTRL_BASE + 0x1020) +#define PCIE_SUBCTRL_SC_PCIE_SYS_CTRL21 (PCIE_SUBCTRL_BASE + 0x1024) #define PCIE_SUBCTRL_SC_DISPATCH_RETRY_CONTROL_REG (PCIE_SUBCTRL_BASE + 0x1030) #define PCIE_SUBCTRL_SC_DISPATCH_INTMASK_REG (PCIE_SUBCTRL_BASE + 0x1100) #define PCIE_SUBCTRL_SC_DISPATCH_RAWINT_REG (PCIE_SUBCTRL_BASE + 0x1104)