From patchwork Fri Jun 23 18:30:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ard Biesheuvel X-Patchwork-Id: 106279 Delivered-To: patch@linaro.org Received: by 10.140.91.2 with SMTP id y2csp345851qgd; Fri, 23 Jun 2017 11:31:20 -0700 (PDT) X-Received: by 10.55.70.69 with SMTP id t66mr10987245qka.147.1498242680153; Fri, 23 Jun 2017 11:31:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1498242680; cv=none; d=google.com; s=arc-20160816; b=g1SAGrLdtds+Xig08Fs2SXtmBSYquULn5zicRSV4fp2uoMWW+Er77kc1UKmc/nJXYe Qvi77V2zB9Ua4uBMPHZ4BPJdlm2MiavwYb66/c5nxDfJfxRJMGdWJbjtcZSIRdAg16jh Abjhbe4eneABcBYTUVqbFh41DzfEDbfyokUdm7AfG3PMlbtZB8YAfjvWwkU3PGsa9REw GsTIz903rMQRiCnx/wGDnxg9xjPGB3GjKOkdmnXDsGdoefl7mXuG0G70PWZvW6uXS/xF Z4NnB3HqYqQpxDB9YpghxkUQH6BhXED5mXlCaHk5XEnbzSkh3RxlL/9dDKZkReFxAAiG R2hg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:references:in-reply-to:message-id :date:to:from:delivered-to:arc-authentication-results; bh=bnF8BM/A3BPxh6Oe+tOUAXOq/TgrcLHI8xweJbqA3I4=; b=MECKdSkIkLtu4WrEIA5NIAiUKb7+6OHzOoPe08UOMtaw/E12Ep8YwIpqR7U3PUX45+ 0mMfy4KIr4suRIaZh6vmo7wz35ow+5RpF87OhdNdjbC8bBlqbJyQUzOoKwTh8nhJTKC9 JYA0ilC2dy0bs5KPUHVELN3bkzjfCj3X4jKJMLR8ZUFc+3CONQ+xLy1/QVENoNcwTKmK qCA/1zRNqWNxYFDvXiijUyG7ClpYyZVpASqEOJpiqX8KlNjJRTCpfJsk0+MLreGpIfPo EiMdUWKOz5c4wQBSL3LxtnU3bLpH2S1hWJWCPYKH2Jn9SMu7X3unCAy17cnw7E2RTqVg ZxUQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.linaro.org (lists.linaro.org. [54.225.227.206]) by mx.google.com with ESMTP id m3si4518010qkd.257.2017.06.23.11.31.19; Fri, 23 Jun 2017 11:31:20 -0700 (PDT) Received-SPF: pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) client-ip=54.225.227.206; Authentication-Results: mx.google.com; spf=pass (google.com: domain of linaro-uefi-bounces@lists.linaro.org designates 54.225.227.206 as permitted sender) smtp.mailfrom=linaro-uefi-bounces@lists.linaro.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id C9B2A60C34; Fri, 23 Jun 2017 18:31:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on ip-10-142-244-252 X-Spam-Level: X-Spam-Status: No, score=-4.7 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, URIBL_BLOCKED autolearn=disabled version=3.4.0 Received: from [127.0.0.1] (localhost [127.0.0.1]) by lists.linaro.org (Postfix) with ESMTP id C432D60C39; Fri, 23 Jun 2017 18:31:06 +0000 (UTC) X-Original-To: linaro-uefi@lists.linaro.org Delivered-To: linaro-uefi@lists.linaro.org Received: by lists.linaro.org (Postfix, from userid 109) id 2404B60C2E; Fri, 23 Jun 2017 18:31:00 +0000 (UTC) Received: from mail-wr0-f174.google.com (mail-wr0-f174.google.com [209.85.128.174]) by lists.linaro.org (Postfix) with ESMTPS id 11DDF60C12 for ; Fri, 23 Jun 2017 18:30:59 +0000 (UTC) Received: by mail-wr0-f174.google.com with SMTP id 77so76644867wrb.1 for ; Fri, 23 Jun 2017 11:30:59 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=usQ5WTkCobnYF8CeIHGAFym8ub4eUm2XdAlmsPG0a0k=; b=AzgzhRbWsUcMy2eoD+Um4iTUN1224fnPf9EnGev5wpEwwNU9wSQkPvSil37TjvWlXs i8aXETvrdfSawTKwVT20YFjjUesJt/BeQ2Oj/aJrRrnVz2IUHWJTyrfBRFLZ20MM9NX0 ac+p7kpL2TXTDLyByN217alf2lZDVlA76g1tGr2xqf65fVOaGYNBKixIw/Xt1zDV/OmK d9Vsv2dFUsQ3RvvJZaDGeoP4w0lMtoMrCOSaNPSrR/Fm3Nr5sMt+t6L1whnFYP7bsdth DptwopFCzw8ytfjZbMSBgU0IlrupNVpXKhseduOpEahOZygoH3VtDpmL4WPCXWfjQVHw ko+w== X-Gm-Message-State: AKS2vOxBfzhnzT2Wuxwl6oLFuZlFDoguCbh4/YL4f9cbTnnrx2xZEEE9 gjMzDHUK/6tXcC68PV6trYka X-Received: by 10.28.17.4 with SMTP id 4mr1742288wmr.63.1498242657909; Fri, 23 Jun 2017 11:30:57 -0700 (PDT) Received: from localhost.localdomain ([160.171.41.197]) by smtp.gmail.com with ESMTPSA id l190sm5632336wmb.18.2017.06.23.11.30.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 23 Jun 2017 11:30:57 -0700 (PDT) From: Ard Biesheuvel To: linaro-uefi@lists.linaro.org Date: Fri, 23 Jun 2017 18:30:40 +0000 Message-Id: <20170623183045.21494-2-ard.biesheuvel@linaro.org> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20170623183045.21494-1-ard.biesheuvel@linaro.org> References: <20170623183045.21494-1-ard.biesheuvel@linaro.org> Cc: rfranz@cavium.com, alan@softiron.co.uk Subject: [Linaro-uefi] [PATCH 1/6] Platforms/AMD/Styx: remove incorrect timer frequency X-BeenThere: linaro-uefi@lists.linaro.org X-Mailman-Version: 2.1.16 Precedence: list List-Id: "For discussions about Linaro-related UEFI development. Not a substitute for edk2-devel." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: linaro-uefi-bounces@lists.linaro.org Sender: "Linaro-uefi" The ARM generic timer needs to be programmed with the actual frequency of the input clock, but this can only be done from the most privileged execution mode implemented by the hardware. UEFI on AArch64 usually executes in EL2, which is not the most privileged execution mode in most cases, and so the timer driver is set up to deal with this: no attempt is made to program the PCD value PcdArmArchTimerFreqInHz into the frequency register. However, a non-zero PCD value is still treated as an override for the register value, in case the programmed value is known to be incorrect. However, on the various Styx based platforms, the PCD value is set to an incorrect non-zero value, and so the routines that convert time delays into cycle counts are off by 33% (187.5 MHz vs 250 MHz). This may affect timeouts related to SATA link training, and other low level routines that rely on accurate timekeeping. So remove the explicit PCD settings, so they default to 0, letting the driver use the programmed value instead. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Ard Biesheuvel --- Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc | 5 ----- Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc | 5 ----- Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc | 5 ----- 3 files changed, 15 deletions(-) diff --git a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc index f068713bf0b8..ddb944d0beb4 100644 --- a/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc +++ b/Platforms/AMD/Styx/CelloBoard/CelloBoard.dsc @@ -400,11 +400,6 @@ DEFINE DO_KCS = 0 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000 # - # ARM Architectual Timer Frequency - # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000 - - # # Cello has 2 SATA ports on the first controller. # gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2 diff --git a/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc index b1a7cfd4c4a8..f6d2d37014dd 100644 --- a/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc +++ b/Platforms/AMD/Styx/Overdrive1000Board/Overdrive1000Board.dsc @@ -402,11 +402,6 @@ DEFINE DO_KCS = 1 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000 # - # ARM Architectual Timer Frequency - # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000 - - # # 2 ports active on Overdrive 1000 # gAmdStyxTokenSpaceGuid.PcdSata0PortCount|2 diff --git a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc index 98f5c9452dcd..7ac3ce3760fa 100644 --- a/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc +++ b/Platforms/AMD/Styx/OverdriveBoard/OverdriveBoard.dsc @@ -409,11 +409,6 @@ DEFINE DO_KCS = 1 gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xE112F000 # - # ARM Architectual Timer Frequency - # - gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|187500000 - - # # Overdrive B1 has 14 SATA ports across 2 controllers. # gAmdStyxTokenSpaceGuid.PcdSata0PortCount|8