diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
index 94454569f6..9ca7160dad 100644
--- a/Platform/Hisilicon/D06/D06.dsc
+++ b/Platform/Hisilicon/D06/D06.dsc
@@ -70,6 +70,7 @@
 
   TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
   RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
+  OemMiscLib|Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
   OemAddressMapLib|Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.inf
   PlatformSysCtrlLib|Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.inf
 
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
new file mode 100644
index 0000000000..8f68f7cec5
--- /dev/null
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
@@ -0,0 +1,47 @@
+#/** @file
+#
+#    Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+#    Copyright (c) 2018, Linaro Limited. All rights reserved.
+#
+#    This program and the accompanying materials
+#    are licensed and made available under the terms and conditions of the BSD License
+#    which accompanies this distribution. The full text of the license may be found at
+#    http://opensource.org/licenses/bsd-license.php
+#
+#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+#
+#**/
+
+[Defines]
+  INF_VERSION                    = 0x0001001A
+  BASE_NAME                      = OemMiscLib
+  FILE_GUID                      = 3002911C-C160-4C46-93BB-782846673EEA
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = OemMiscLib
+
+[Sources.common]
+  BoardFeatureD06.c
+  BoardFeatureD06Strings.uni
+  OemMiscLibD06.c
+
+[Packages]
+  ArmPkg/ArmPkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MdePkg/MdePkg.dec
+  Silicon/Hisilicon/HisiPkg.dec
+
+[LibraryClasses]
+  PcdLib
+  SerdesLib
+  TimerLib
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid   ## SOMETIMES_CONSUMES
+
+[Pcd]
+  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+  gHisiTokenSpaceGuid.PcdIsMPBoot
+  gHisiTokenSpaceGuid.PcdSocketMask
+  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
index 87cb498dd7..efecb9aa77 100644
--- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
@@ -22,7 +22,11 @@
 #include <PlatformArch.h>
 #include <Library/I2CLib.h>
 
-#define PCIEDEVICE_REPORT_MAX      4
+#define PCIEDEVICE_REPORT_MAX      8
+#define MAX_PROCESSOR_SOCKETS      MAX_SOCKET
+#define MAX_MEMORY_CHANNELS        MAX_CHANNEL
+#define MAX_DIMM_PER_CHANNEL       MAX_DIMM
+
 typedef struct _REPORT_PCIEDIDVID2BMC{
     UINTN   Bus;
     UINTN   Device;
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c
new file mode 100644
index 0000000000..7e3f2e2a0e
--- /dev/null
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c
@@ -0,0 +1,432 @@
+/** @file
+*
+*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <IndustryStandard/SmBios.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/DebugLib.h>
+#include <Library/HiiLib.h>
+#include <Library/I2CLib.h>
+#include <Library/IoLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/SerdesLib.h>
+#include <Protocol/Smbios.h>
+
+#include <PlatformArch.h>
+
+I2C_DEVICE gRtcDevice = {
+  .Socket = 0,
+  .Port = 5,
+  .DeviceType = DEVICE_TYPE_SPD,
+  .SlaveDeviceAddress = 0x68
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
+{
+  {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
+{
+  {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
+};
+
+SERDES_PARAM gSerdesParamNA = {
+  .Hilink0Mode = EmHilink0Hccs1X8Width16,
+  .Hilink1Mode = EmHilink1Hccs0X8Width16,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Sas1X4,
+  .Hilink6Mode = 0x0,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParamNB = {
+  .Hilink0Mode = EmHilink0Pcie1X8,
+  .Hilink1Mode = EmHilink1Pcie0X8,
+  .Hilink2Mode = EmHilink2Sas0X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2,
+  .Hilink6Mode = 0xF,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParamS1NA = {
+  .Hilink0Mode = EmHilink0Hccs1X8Width16,
+  .Hilink1Mode = EmHilink1Hccs0X8Width16,
+  .Hilink2Mode = EmHilink2Pcie2X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Sas1X4,
+  .Hilink6Mode = 0x0,
+  .UseSsc      = 0,
+};
+
+SERDES_PARAM gSerdesParamS1NB = {
+  .Hilink0Mode = EmHilink0Pcie1X8,
+  .Hilink1Mode = EmHilink1Pcie0X8,
+  .Hilink2Mode = EmHilink2Sas0X8,
+  .Hilink3Mode = 0x0,
+  .Hilink4Mode = 0xF,
+  .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2,
+  .Hilink6Mode = 0xF,
+  .UseSsc      = 0,
+};
+
+
+EFI_STATUS
+OemGetSerdesParam (
+  OUT SERDES_PARAM *ParamA,
+  OUT SERDES_PARAM *ParamB,
+  IN  UINT32       SocketId
+ )
+{
+  if (NULL == ParamA) {
+    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  } if (NULL == ParamB) {
+    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
+    return EFI_INVALID_PARAMETER;
+  }
+
+  if (0 == SocketId) {
+    (VOID) CopyMem (ParamA, &gSerdesParamNA, sizeof (*ParamA));
+    (VOID) CopyMem (ParamB, &gSerdesParamNB, sizeof (*ParamB));
+  } else {
+    (VOID) CopyMem (ParamA, &gSerdesParamS1NA, sizeof (*ParamA));
+    (VOID) CopyMem (ParamB, &gSerdesParamS1NB, sizeof (*ParamB));
+  }
+
+  return EFI_SUCCESS;
+}
+
+VOID
+OemPcieResetAndOffReset (
+  VOID
+  )
+{
+  return;
+}
+
+SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
+  // PCIe0 Slot 1
+  {
+    {                                       // Hdr
+        EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+        0,                                  // Length,
+        0                                   // Handle
+    },
+    1,                                      // SlotDesignation
+    SlotTypePciExpressX16,                  // SlotType
+    SlotDataBusWidth16X,                    // SlotDataBusWidth
+    SlotUsageAvailable,                     // SlotUsage
+    SlotLengthOther,                        // SlotLength
+    0x0001,                                 // SlotId
+    {                                       // SlotCharacteristics1
+        0,                                  // CharacteristicsUnknown  :1;
+        0,                                  // Provides50Volts         :1;
+        0,                                  // Provides33Volts         :1;
+        0,                                  // SharedSlot              :1;
+        0,                                  // PcCard16Supported       :1;
+        0,                                  // CardBusSupported        :1;
+        0,                                  // ZoomVideoSupported      :1;
+        0                                   // ModemRingResumeSupported:1;
+    },
+    {                                       // SlotCharacteristics2
+        0,                                  // PmeSignalSupported      :1;
+        0,                                  // HotPlugDevicesSupported :1;
+        0,                                  // SmbusSignalSupported    :1;
+        0                                   // Reserved                :5;
+    },
+    0x00,                                   // SegmentGroupNum
+    0x00,                                   // BusNum
+    0                                       // DevFuncNum
+  },
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0002,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0003,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+
+
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0004,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX16,                  // SlotType
+      SlotDataBusWidth16X,                    // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0005,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0006,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0007,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+  {
+      {                                       // Hdr
+          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
+          0,                                  // Length,
+          0                                   // Handle
+      },
+      1,                                      // SlotDesignation
+      SlotTypePciExpressX8,                   // SlotType
+      SlotDataBusWidth8X,                     // SlotDataBusWidth
+      SlotUsageAvailable,                     // SlotUsage
+      SlotLengthOther,                        // SlotLength
+      0x0008,                                 // SlotId
+      {                                       // SlotCharacteristics1
+          0,                                  // CharacteristicsUnknown  :1;
+          0,                                  // Provides50Volts         :1;
+          0,                                  // Provides33Volts         :1;
+          0,                                  // SharedSlot              :1;
+          0,                                  // PcCard16Supported       :1;
+          0,                                  // CardBusSupported        :1;
+          0,                                  // ZoomVideoSupported      :1;
+          0                                   // ModemRingResumeSupported:1;
+      },
+      {                                       // SlotCharacteristics2
+          0,                                  // PmeSignalSupported      :1;
+          0,                                  // HotPlugDevicesSupported :1;
+          0,                                  // SmbusSignalSupported    :1;
+          0                                   // Reserved                :5;
+      },
+      0x00,                                   // SegmentGroupNum
+      0x00,                                   // BusNum
+      0                                       // DevFuncNum
+  },
+
+  };
+
+UINT8
+OemGetPcieSlotNumber (
+  VOID
+  )
+{
+  return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
+}
+
+EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
+  {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_040), STRING_TOKEN(STR_LEMON_C10_DIMM_041)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_050), STRING_TOKEN(STR_LEMON_C10_DIMM_051)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_060), STRING_TOKEN(STR_LEMON_C10_DIMM_061)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_070), STRING_TOKEN(STR_LEMON_C10_DIMM_071)}},
+
+  {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_140), STRING_TOKEN(STR_LEMON_C10_DIMM_141)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_150), STRING_TOKEN(STR_LEMON_C10_DIMM_151)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_160), STRING_TOKEN(STR_LEMON_C10_DIMM_161)},
+   {STRING_TOKEN(STR_LEMON_C10_DIMM_170), STRING_TOKEN(STR_LEMON_C10_DIMM_171)}}
+};
+
+EFI_HII_HANDLE
+EFIAPI
+OemGetPackages (
+  VOID
+  )
+{
+  return HiiAddPackages (
+           &gEfiCallerIdGuid,
+           NULL,
+           OemMiscLibStrings,
+           NULL,
+           NULL
+           );
+}
+
+
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
new file mode 100644
index 0000000000..95521752ff
--- /dev/null
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
@@ -0,0 +1,119 @@
+/** @file
+*
+*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
+*  Copyright (c) 2018, Linaro Limited. All rights reserved.
+*
+*  This program and the accompanying materials
+*  are licensed and made available under the terms and conditions of the BSD License
+*  which accompanies this distribution.  The full text of the license may be found at
+*  http://opensource.org/licenses/bsd-license.php
+*
+*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+*
+**/
+
+#include <Uefi.h>
+#include <PlatformArch.h>
+#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/LpcLib.h>
+#include <Library/OemAddressMapLib.h>
+#include <Library/OemMiscLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PlatformSysCtrlLib.h>
+#include <Library/SerdesLib.h>
+#include <Library/SerialPortLib.h>
+#include <Library/TimerLib.h>
+
+REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
+  {67,0,0,0},
+  {225,0,0,3},
+  {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
+  {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+};
+
+// Right now we only support 1P
+BOOLEAN
+OemIsSocketPresent (
+  UINTN Socket
+  )
+{
+  UINT32 SocketMask = PcdGet32 (PcdSocketMask);
+  return (BOOLEAN)((SocketMask & (1 << Socket)) ? TRUE : FALSE);
+}
+
+
+UINTN
+OemGetSocketNumber (
+  VOID
+  )
+{
+  if(!OemIsMpBoot ()) {
+    return 1;
+  }
+
+  return MAX_PROCESSOR_SOCKETS;
+}
+
+
+UINTN
+OemGetDdrChannel (
+  VOID
+  )
+{
+  return MAX_MEMORY_CHANNELS;
+}
+
+
+UINTN
+OemGetDimmSlot (
+  UINTN Socket,
+  UINTN Channel
+  )
+{
+  return MAX_DIMM_PER_CHANNEL;
+}
+
+
+BOOLEAN
+OemIsMpBoot (
+  VOID
+  )
+{
+  return PcdGet32 (PcdIsMPBoot);
+}
+
+VOID
+OemLpcInit (
+  VOID
+  )
+{
+  LpcInit ();
+  return;
+}
+
+UINT32
+OemIsWarmBoot (
+  VOID
+  )
+{
+  return 0;
+}
+
+VOID
+OemBiosSwitch (
+  UINT32 Master
+  )
+{
+  (VOID)Master;
+  return;
+}
+
+BOOLEAN
+OemIsNeedDisableExpanderBuffer (
+  VOID
+  )
+{
+  return TRUE;
+}
diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni
new file mode 100644
index 0000000000..046fa05dff
--- /dev/null
+++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni
@@ -0,0 +1,64 @@
+// *++
+//
+// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
+//
+// This program and the accompanying materials
+// are licensed and made available under the terms and conditions of the BSD License
+// which accompanies this distribution.  The full text of the license may be found at
+// http://opensource.org/licenses/bsd-license.php
+//
+// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
+// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
+//
+// --*/
+
+/=#
+
+#langdef en-US "English"
+
+//
+// Begin English Language Strings
+//
+#string STR_MEMORY_SUBCLASS_UNKNOWN    #language en-US  "Unknown"
+
+//
+// DIMM Device Locator strings
+
+// D06
+#string STR_LEMON_C10_DIMM_000     #language en-US "J5"
+#string STR_LEMON_C10_DIMM_001     #language en-US "J6"
+#string STR_LEMON_C10_DIMM_010     #language en-US "J7"
+#string STR_LEMON_C10_DIMM_011     #language en-US "J8"
+#string STR_LEMON_C10_DIMM_020     #language en-US "J9"
+#string STR_LEMON_C10_DIMM_021     #language en-US "J10"
+#string STR_LEMON_C10_DIMM_030     #language en-US "J11"
+#string STR_LEMON_C10_DIMM_031     #language en-US "J12"
+#string STR_LEMON_C10_DIMM_040     #language en-US "J13"
+#string STR_LEMON_C10_DIMM_041     #language en-US "J14"
+#string STR_LEMON_C10_DIMM_050     #language en-US "J15"
+#string STR_LEMON_C10_DIMM_051     #language en-US "J16"
+#string STR_LEMON_C10_DIMM_060     #language en-US "J17"
+#string STR_LEMON_C10_DIMM_061     #language en-US "J18"
+#string STR_LEMON_C10_DIMM_070     #language en-US "J19"
+#string STR_LEMON_C10_DIMM_071     #language en-US "J20"
+#string STR_LEMON_C10_DIMM_100     #language en-US "J21"
+#string STR_LEMON_C10_DIMM_101     #language en-US "J22"
+#string STR_LEMON_C10_DIMM_110     #language en-US "J23"
+#string STR_LEMON_C10_DIMM_111     #language en-US "J24"
+#string STR_LEMON_C10_DIMM_120     #language en-US "J25"
+#string STR_LEMON_C10_DIMM_121     #language en-US "J26"
+#string STR_LEMON_C10_DIMM_130     #language en-US "J27"
+#string STR_LEMON_C10_DIMM_131     #language en-US "J28"
+#string STR_LEMON_C10_DIMM_140     #language en-US "J29"
+#string STR_LEMON_C10_DIMM_141     #language en-US "J30"
+#string STR_LEMON_C10_DIMM_150     #language en-US "J31"
+#string STR_LEMON_C10_DIMM_151     #language en-US "J32"
+#string STR_LEMON_C10_DIMM_160     #language en-US "J33"
+#string STR_LEMON_C10_DIMM_161     #language en-US "J34"
+#string STR_LEMON_C10_DIMM_170     #language en-US "J35"
+#string STR_LEMON_C10_DIMM_171     #language en-US "J36"
+
+//
+// End English Language Strings
+//
+
diff --git a/v2/v2-0000-cover-letter.patch b/v2/v2-0000-cover-letter.patch
new file mode 100644
index 0000000000..b2fe3e351f
--- /dev/null
+++ b/v2/v2-0000-cover-letter.patch
@@ -0,0 +1,316 @@
+From 7181548f40616d5086dba15cc557703e517e9c50 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Tue, 14 Aug 2018 16:06:00 +0800
+Subject: [PATCH edk2-platforms v2 00/43] Upload for D06 platform 
+
+The major features of this patchset include:
+1 D06 source code;
+2 Unify some D0x modules;
+
+This patch set is base on pcihostbridage-v2.
+For compiling D06, add below hunk to edk2-platforms.config
+[d06]
+LONGNAME=HiSilicon D06
+DSC=Platform/Hisilicon/D06/D06.dsc
+ARCH=AARCH64
+
+Code can also be found in github: https://github.com/hisilicon/OpenPlatformPkg.git
+branch: d06-platform-v2
+
+
+Heyi Guo (3):
+  Hisilicon/D06: Add Debug Serial Port Init Driver
+  Hisilicon/Hi1620: Add ACPI PPTT table
+  Platform/Hisilicon/D06: Enable ACPI PPTT
+
+Luqi Jiang (1):
+  Hisilicon/D06: add apei driver
+
+Ming Huang (32):
+  Silicon/Hisilicon: Modify the MRC interface for other module
+  Silicon/Hisilicon: Separate PlatformArch.h
+  Silicon/Hisilicon/Acpi: Move some macro to PlatformArch.h
+  Hisilicon/D0x: Move CustomData.Fv to common path of Hisilicon
+  Hisilicon/D0x: Move IpmiCmdLib to common path of Hisilicon
+  Hisilicon/D0x: Unify FlashFvbDxe driver
+  Hisilicon/D0X: Rename the global variable gDS3231RtcDevice
+  Hisilicon/D06: Add several base file for D06
+  Platform/Hisilicon/D06: Add M41T83RealTimeClockLib
+  Platform/Hisilicon/D06: Add edk2-non-osi components for D06
+  Hisilicon/D06: Add OemMiscLibD06
+  Silicon/Hisilicon/D06: Wait for all disk ready
+  Silicon/Hisilicon/Acpi: Unify HisiAcipPlatformDxe
+  Hisilicon/D06: Add ACPI Tables for D06
+  Silicon/Hisilicon/D06: Stop watchdog
+  Hisilicon/I2C: Modify I2CLib.c for coding style
+  Silicon/Hisilicon/I2C: Refactor I2C library
+  Silicon/Hisilicon/D06: Fix I2C enable fail issue for D06
+  Silicon/Hisilicon/D06: Add I2C delay for HNS auto config
+  Hisilicon/I2C: Fix a typo issue
+  Platform/Hisilicon/D06: Add OemNicLib
+  Platform/Hisilicon/D06: Add OemNicConfig2P Driver
+  Platform/Hisilicon/D06: Add EarlyConfigPeim peim
+  Platform/Hisilicon/D06: Add PciHostBridgeLib
+  Silicon/Hisilicon/D06: Add some Lpc macro to LpcLib.h
+  Platform/Hisilicon/D06: Add capsule upgrade support
+  Silicon/Hisilicon/D06: Add I2C Bus Exception handle function
+  Silicon/Hisilicon/Setup: Support SPCR table switch
+  Silicon/Hisilicon/setup: Support SMMU switch
+  Hisilicon/D06: Add PciPlatformLib
+  Hisilicon/D06: Add edk2-non-osi Shell components
+  Platform/Hisilicon/D0x: Update version string to 18.08
+
+Sun Yuanchen (3):
+  Silicon/Hisilicon/D0x: Move dimm size definition to PlatformArch.h
+  Silicon/Hisilicon/D0x: Move RAS macro to PlatformArch.h
+  Hisilicon/D0x: Update SMBIOS type9 info
+
+Yang XinYi (2):
+  Hisilicon/D06: Add Hi1620OemConfigUiLib
+  Silicon/Hisilicon/Setup: Add Setup Item "EnableGOP"
+
+ZhenYao (1):
+  Silicon/Hisilicon/D06: Modify for close slave core clock.
+
+shaochangliang (1):
+  Silicon/Hisilicon/D06: Optimize HNS config CDR post time
+
+ Platform/Hisilicon/D06/D06.dec                |   29 +
+ Silicon/Hisilicon/HisiPkg.dec                 |    6 +
+ Platform/Hisilicon/D03/D03.dsc                |    4 +-
+ Platform/Hisilicon/D05/D05.dsc                |    4 +-
+ Platform/Hisilicon/D06/D06.dsc                |  490 ++++
+ Platform/Hisilicon/D03/D03.fdf                |    8 +-
+ Platform/Hisilicon/D05/D05.fdf                |    8 +-
+ Platform/Hisilicon/D06/D06.fdf                |  444 ++++
+ .../OemMiscLib2P/OemMiscLib2PHi1610.inf       |    1 +
+ .../Library/OemMiscLibD05/OemMiscLibD05.inf   |    1 +
+ .../OemNicConfig2PHi1620/OemNicConfig2P.inf   |   43 +
+ .../SystemFirmwareDescriptor.inf              |   50 +
+ .../EarlyConfigPeim/EarlyConfigPeimD06.inf    |   50 +
+ .../Library/OemMiscLibD06/OemMiscLibD06.inf   |   51 +
+ .../D06/Library/OemNicLib/OemNicLib.inf       |   35 +
+ .../PciHostBridgeLib/PciHostBridgeLib.inf     |   36 +
+ .../Drivers/FlashFvbDxe/FlashFvbDxe.inf       |    7 +-
+ .../HisiAcpiPlatformDxe/AcpiPlatformDxe.inf   |    3 +-
+ .../ProcessorSubClassDxe.inf                  |    2 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Apei.inf    |   64 +
+ .../Pl011DebugSerialPortInitDxe.inf           |   48 +
+ .../Hi1620AcpiTables/AcpiTablesHi1620.inf     |   59 +
+ .../Hi1620OemConfigUiLib/OemConfigUiLib.inf   |   68 +
+ .../Hi1620PciPlatformLib.inf                  |   30 +
+ Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf        |   48 +
+ .../M41T83RealTimeClockLib.inf                |   46 +
+ .../PlatformBootManagerLib.inf                |    4 +
+ .../OemNicConfig2PHi1620/OemNicConfig.h       |   25 +
+ .../Hisilicon/D06/Include/Library/CpldD06.h   |   39 +
+ .../Smbios/MemorySubClassDxe/MemorySubClass.h |    2 -
+ .../Hi1610/Hi1610AcpiTables/Hi1610Platform.h  |   27 +-
+ .../Hisilicon/Hi1610/Include/PlatformArch.h   |   71 +
+ .../Hi1616/D05AcpiTables/Hi1616Platform.h     |   24 +-
+ .../Hisilicon/Hi1616/Include/PlatformArch.h   |   71 +
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h  |   41 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Bert/bert.h |   43 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Einj/einj.h |  146 ++
+ .../Hi1620/Drivers/Apei/ErrorSource/Ghes.h    |  110 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Erst/erst.h |  146 ++
+ .../Hisilicon/Hi1620/Drivers/Apei/Hest/hest.h |   59 +
+ .../Hi1620/Drivers/Apei/OemApeiHi1620.h       |   43 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Platform.h  |   27 +
+ .../Hi1620/Hi1620OemConfigUiLib/OemConfig.h   |  142 ++
+ .../Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h |   64 +
+ .../Hi1620/Include/Library/SerdesLib.h        |   85 +
+ .../Hisilicon/Hi1620/Include/PlatformArch.h   |   67 +
+ Silicon/Hisilicon/Hi1620/Pptt/Pptt.h          |   68 +
+ .../Hisilicon/Include/Library/AcpiNextLib.h   |   31 +-
+ .../Hisilicon/Include/Library/HwMemInitLib.h  |  356 +--
+ .../Hisilicon/Include/Library/IpmiCmdLib.h    |   16 +
+ Silicon/Hisilicon/Include/Library/LpcLib.h    |   51 +-
+ .../Include/Library/OemAddressMapLib.h        |    8 +
+ .../Hisilicon/Include/Library/OemConfigData.h |   85 +
+ .../Hisilicon/Include/Library/OemMiscLib.h    |    9 +-
+ Silicon/Hisilicon/Include/Library/OemNicLib.h |   57 +
+ .../Include/Library/PlatformSysCtrlLib.h      |    6 +
+ Silicon/Hisilicon/Include/PlatformArch.h      |   35 -
+ Silicon/Hisilicon/Library/I2CLib/I2CHw.h      |    9 +-
+ .../M41T83RealTimeClock.h                     |  158 ++
+ .../DS3231RealTimeClockLib.c                  |    8 +-
+ .../OemMiscLib2P/BoardFeature2PHi1610.c       |    2 +-
+ .../Library/OemMiscLib2P/OemMiscLib2PHi1610.c |   24 +
+ .../Library/OemMiscLibD05/BoardFeatureD05.c   |    2 +-
+ .../D05/Library/OemMiscLibD05/OemMiscLibD05.c |   27 +-
+ .../OemNicConfig2PHi1620/OemNicConfig2P.c     |   71 +
+ .../SystemFirmwareDescriptorPei.c             |   70 +
+ .../D06/EarlyConfigPeim/EarlyConfigPeimD06.c  |  107 +
+ .../Library/OemMiscLibD06/BoardFeatureD06.c   |  432 ++++
+ .../D06/Library/OemMiscLibD06/OemMiscLibD06.c |  222 ++
+ .../D06/Library/OemNicLib/OemNicLib.c         |  570 +++++
+ .../PciHostBridgeLib/PciHostBridgeLib.c       |  635 ++++++
+ .../Drivers/FlashFvbDxe/FlashFvbDxe.c         |   22 +-
+ .../HisiAcpiPlatformDxe/UpdateAcpiTable.c     |  118 +-
+ .../Smbios/AddSmbiosType9/AddSmbiosType9.c    |   14 +-
+ .../Smbios/MemorySubClassDxe/MemorySubClass.c |   26 +-
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c  |  108 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Bert/bert.c |   92 +
+ .../Hisilicon/Hi1620/Drivers/Apei/Einj/einj.c |  349 +++
+ .../Hi1620/Drivers/Apei/ErrorSource/Ghes.c    |  330 +++
+ .../Hisilicon/Hi1620/Drivers/Apei/Erst/erst.c |  374 ++++
+ .../Hisilicon/Hi1620/Drivers/Apei/Hest/hest.c |  119 +
+ .../Hi1620/Drivers/Apei/OemApeiHi1620.c       |  337 +++
+ .../Pl011DebugSerialPortInitDxe.c             |   64 +
+ .../Hi1620/Hi1620OemConfigUiLib/OemConfig.c   |  364 +++
+ .../Hi1620PciPlatformLib.c                    |   67 +
+ Silicon/Hisilicon/Hi1620/Pptt/Pptt.c          |  543 +++++
+ .../DS3231RealTimeClockLib.c                  |    8 +-
+ Silicon/Hisilicon/Library/I2CLib/I2CLib.c     |  975 ++++----
+ .../M41T83RealTimeClockLib.c                  |  564 +++++
+ .../PlatformBootManagerLib/PlatformBm.c       |   65 +
+ .../SystemFirmwareUpdateConfig.ini            |   46 +
+ .../SystemFirmwareDescriptor.aslc             |   81 +
+ .../OemMiscLibD06/BoardFeatureD06Strings.uni  |   64 +
+ .../Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl      |  409 ++++
+ .../Hi1620/Hi1620AcpiTables/Dsdt/Com.asl      |   30 +
+ .../Hi1620AcpiTables/Dsdt/DsdtHi1620.asl      |   35 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Apei.asl      |   93 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Ged.asl       |   58 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl      | 1459 ++++++++++++
+ .../Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl      |   41 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Pci.asl       | 1216 ++++++++++
+ .../Hi1620AcpiTables/Dsdt/Hi1620Power.asl     |   28 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Rde.asl       |   47 +
+ .../Hi1620AcpiTables/Dsdt/Hi1620Sec.asl       |   57 +
+ .../Dsdt/Hi1620Socip4_i2c100k.asl             |  249 +++
+ .../Dsdt/Hi1620Socip4_i2c400k.asl             |  249 +++
+ .../Hi1620AcpiTables/Dsdt/LpcUart_clk.asl     |   49 +
+ .../Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl  | 1658 ++++++++++++++
+ .../Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl     |   49 +
+ .../Hi1620/Hi1620AcpiTables/Facs.aslc         |   67 +
+ .../Hi1620/Hi1620AcpiTables/Fadt.aslc         |   91 +
+ .../Hi1620/Hi1620AcpiTables/Gtdt.aslc         |   86 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc   |   86 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Iort.asl    | 1989 +++++++++++++++++
+ .../Hi1620AcpiTables/Hi1620IortNoSmmu.asl     | 1736 ++++++++++++++
+ .../Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc   |   64 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc   |   64 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc   |   81 +
+ .../Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc   |  166 ++
+ .../Hi1620/Hi1620AcpiTables/MadtHi1620.aslc   |  375 ++++
+ .../Hi1620OemConfigUiLib/MemoryConfig.hfr     |  154 ++
+ .../Hi1620OemConfigUiLib/MemoryConfig.uni     |  103 +
+ .../Hi1620OemConfigUiLib/MiscConfig.hfr       |   48 +
+ .../Hi1620OemConfigUiLib/MiscConfig.uni       |   27 +
+ .../Hi1620OemConfigUiLib/OemConfigUiLib.uni   |   24 +
+ .../OemConfigUiLibStrings.uni                 |   42 +
+ .../Hi1620OemConfigUiLib/OemConfigVfr.Vfr     |   89 +
+ .../Hi1620OemConfigUiLib/PcieConfig.hfr       |  219 ++
+ .../PcieConfigStrings.uni                     |  111 +
+ .../Hi1620OemConfigUiLib/PciePortConfig.hfr   |  167 ++
+ .../Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr |  172 ++
+ .../Hi1620/Hi1620OemConfigUiLib/RasConfig.uni |   85 +
+ .../Hi1620OemConfigUiLib/iBMCConfig.hfr       |   81 +
+ .../Hi1620OemConfigUiLib/iBMCConfig.uni       |   34 +
+ 134 files changed, 21578 insertions(+), 970 deletions(-)
+ create mode 100644 Platform/Hisilicon/D06/D06.dec
+ create mode 100644 Platform/Hisilicon/D06/D06.dsc
+ create mode 100644 Platform/Hisilicon/D06/D06.fdf
+ create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf
+ create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+ create mode 100644 Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf
+ create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+ create mode 100644 Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf
+ create mode 100644 Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf
+ create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf
+ create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
+ create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h
+ create mode 100644 Platform/Hisilicon/D06/Include/Library/CpldD06.h
+ create mode 100644 Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+ create mode 100644 Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
+ create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.h
+ create mode 100644 Silicon/Hisilicon/Include/Library/OemConfigData.h
+ create mode 100644 Silicon/Hisilicon/Include/Library/OemNicLib.h
+ delete mode 100644 Silicon/Hisilicon/Include/PlatformArch.h
+ create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h
+ create mode 100644 Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c
+ create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
+ create mode 100644 Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c
+ create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c
+ create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+ create mode 100644 Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c
+ create mode 100644 Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c
+ create mode 100644 Silicon/Hisilicon/Hi1620/Pptt/Pptt.c
+ create mode 100644 Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c
+ create mode 100644 Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
+ create mode 100644 Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
+ create mode 100644 Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.Vfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr
+ create mode 100644 Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni
+
+-- 
+2.17.0
+
diff --git a/v2/v2-0001-Silicon-Hisilicon-Modify-the-MRC-interface-for-ot.patch b/v2/v2-0001-Silicon-Hisilicon-Modify-the-MRC-interface-for-ot.patch
new file mode 100644
index 0000000000..92d1dc2682
--- /dev/null
+++ b/v2/v2-0001-Silicon-Hisilicon-Modify-the-MRC-interface-for-ot.patch
@@ -0,0 +1,553 @@
+From 7305eac29491a482f4de3875e85486842ca3a389 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Fri, 20 Jul 2018 17:49:43 +0800
+Subject: [PATCH edk2-platforms v2 01/43] Silicon/Hisilicon: Modify the MRC
+ interface for other module
+
+This patch is to unify D0x. Add pGBL_INTERFACE struct define
+and remove useless interfece. Replace DMRC pGblData with pGblInterface;
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Include/Library/HwMemInitLib.h                    | 356 ++++----------------
+ Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c     |   4 +-
+ Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c |  26 +-
+ 3 files changed, 78 insertions(+), 308 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Include/Library/HwMemInitLib.h b/Silicon/Hisilicon/Include/Library/HwMemInitLib.h
+index 2663cad836..e1310e854c 100644
+--- a/Silicon/Hisilicon/Include/Library/HwMemInitLib.h
++++ b/Silicon/Hisilicon/Include/Library/HwMemInitLib.h
+@@ -50,48 +50,6 @@ typedef enum {
+     DDR_FREQ_MAX
+ } DDR_FREQUENCY_INDEX;
+ 
+-typedef struct _DDR_FREQ_TCK
+-{
+-    UINT32      ddrFreq;
+-    UINT32      ddrCk;
+-}DDR_FREQ_TCK;
+-
+-typedef struct _GBL_CFG{
+-
+-
+-}GBL_CFG;
+-
+-typedef struct _GBL_VAR{
+-
+-
+-}GBL_VAR;
+-
+-typedef struct _GBL_NVDATA{
+-
+-
+-}GBL_NVDATA;
+-
+-typedef struct _GOBAL {
+-    const GBL_CFG Config;  // constant input data
+-    GBL_VAR       Variable;    // variable, volatile data
+-    GBL_NVDATA    NvData;  // variable, non-volatile data for S3, warm boot path
+-    UINT32        PreBootFailed;
+-}GOBAL, *PGOBAL;
+-
+-struct DDR_RANK {
+-    BOOLEAN     Status;
+-    UINT16      RttNom;
+-    UINT16      RttPark;
+-    UINT16      RttWr;
+-    UINT16      MR0;
+-    UINT16      MR1;
+-    UINT16      MR2;
+-    UINT16      MR3;
+-    UINT16      MR4;
+-    UINT16      MR5;
+-    UINT16      MR6[9];
+-};
+-
+ struct baseMargin {
+   INT16 n;
+   INT16 p;
+@@ -101,171 +59,7 @@ struct rankMargin {
+   struct baseMargin rank[MAX_CHANNEL][MAX_RANK_CH];
+ };
+ 
+-typedef struct _DDR_DIMM{
+-    BOOLEAN     Status;
+-    UINT8       mapout;
+-    UINT8       DramType;           //Byte 2
+-    UINT8       ModuleType;         //Byte 3
+-    UINT8       ExtendModuleType;
+-    UINT8       SDRAMCapacity;      //Byte 4
+-    UINT8       BankNum;
+-    UINT8       BGNum;              //Byte 4 For DDR4
+-    UINT8       RowBits;            //Byte 5
+-    UINT8       ColBits;            //Byte 5
+-    UINT8       SpdVdd;             //Byte 6
+-    UINT8       DramWidth;          //Byte 7
+-    UINT8       RankNum;            //Byte 7
+-    UINT8       PrimaryBusWidth;    //Byte 8
+-    UINT8       ExtensionBusWidth;  //Byte 8
+-    UINT32      Mtb;
+-    UINT32      Ftb;
+-    UINT32      minTck;
+-    UINT8       MtbDividend;
+-    UINT8       MtbDivsor;
+-    UINT8       nCL;
+-    UINT32      nRCD;
+-    UINT32      nRP;
+-    UINT8       SPDftb;
+-    UINT8       SpdMinTCK;
+-    UINT8       SpdMinTCKFtb;
+-    UINT8       SpdMaxTCK;
+-    UINT8       SpdMinTCL;
+-    UINT8       SpdMinTCLFtb;
+-    UINT8       SpdMinTWR;
+-    UINT8       SpdMinTRCD;
+-    UINT8       SpdMinTRCDFtb;
+-    UINT8       SpdMinTRRD;
+-    UINT8       SpdMinTRRDL;
+-    UINT16      SpdMinTRAS;
+-    UINT16      SpdMinTRC;
+-    UINT16      SpdMinTRCFtb;
+-    UINT16      SpdMinTRFC;
+-    UINT8       SpdMinTWTR;
+-    UINT8       SpdMinTRTP;
+-    UINT8       SpdMinTAA;
+-    UINT8       SpdMinTAAFtb;
+-    UINT8       SpdMinTFAW;
+-    UINT8       SpdMinTRP;
+-    UINT8       SpdMinTRPFtb;
+-    UINT8       SpdMinTCCDL;
+-    UINT8       SpdMinTCCDLFtb;
+-    UINT8       SpdAddrMap;
+-    UINT8       SpdModuleAttr;
+-
+-    UINT8       SpdModPart[SPD_MODULE_PART];         // Module Part Number
+-    UINT8       SpdModPartDDR4[SPD_MODULE_PART_DDR4];     // Module Part Number DDR4
+-    UINT16      SpdMMfgId;              // Module Mfg Id from SPD
+-    UINT16      SpdRMId;              // Register Manufacturer Id
+-    UINT16      SpdMMDate;              // Module Manufacturing Date
+-    UINT32      SpdSerialNum;
+-    UINT16      DimmSize;
+-    UINT16      DimmSpeed;
+-    UINT32      RankSize;
+-    UINT8       SpdMirror; //Denote the dram address mapping is standard mode or mirrored mode
+-    struct DDR_RANK  Rank[MAX_RANK_DIMM];
+-}DDR_DIMM;
+-
+-typedef struct {
+-    UINT32      ddrcTiming0;
+-    UINT32      ddrcTiming1;
+-    UINT32      ddrcTiming2;
+-    UINT32      ddrcTiming3;
+-    UINT32      ddrcTiming4;
+-    UINT32      ddrcTiming5;
+-    UINT32      ddrcTiming6;
+-    UINT32      ddrcTiming7;
+-    UINT32      ddrcTiming8;
+-}DDRC_TIMING;
+-
+-typedef struct _MARGIN_RESULT{
+-    UINT32 OptimalDramVref[12];
+-    UINT32 optimalPhyVref[18];
+-}MARGIN_RESULT;
+-
+-typedef struct _DDR_Channel{
+-    BOOLEAN     Status;
+-    UINT8       CurrentDimmNum;
+-    UINT8       CurrentRankNum;
+-    UINT16      RankPresent;
+-    UINT8       DramType;
+-    UINT8       DramWidth;
+-    UINT8       ModuleType;
+-    UINT32      MemSize;
+-    UINT32      tck;
+-    UINT32      ratio;
+-    UINT32      CLSupport;
+-    UINT32      minTck;
+-    UINT32      taref;
+-    UINT32      nAA;
+-    UINT32      nAOND;
+-    UINT32      nCKE;
+-    UINT32      nCL;
+-    UINT32      nCCDL;
+-    UINT32      nCKSRX;
+-    UINT32      nCKSRE;
+-    UINT32      nCCDNSW;
+-    UINT32      nCCDNSR;
+-    UINT32      nFAW;
+-    UINT32      nMRD;
+-    UINT32      nMOD;
+-    UINT32      nRCD;
+-    UINT32      nRRD;
+-    UINT32      nRRDL;
+-    UINT32      nRAS;
+-    UINT32      nRC;
+-    UINT32      nRFC;
+-    UINT32      nRFCAB;
+-    UINT32      nRTP;
+-    UINT32      nRTW;
+-    UINT32      nRP;
+-    UINT32      nSRE;
+-    UINT32      nWL;
+-    UINT32      nWR;
+-    UINT32      nWTR;
+-    UINT32      nWTRL;
+-    UINT32      nXARD;
+-    UINT32      nZQPRD;
+-    UINT32      nZQINIT;
+-    UINT32      nZQCS;
+-    UINT8       cwl;  //tWL?
+-    UINT8       pl;     //parity latency
+-    UINT8       wr_pre_2t_en;
+-    UINT8       rd_pre_2t_en;
+-    UINT8       cmd_2t_en;
+-    UINT8       parity_en;
+-    UINT8       wr_dbi_en;
+-    UINT8       wr_dm_en;
+-    UINT8       ddr4_crc_en;
+-    UINT16      emrs0;
+-    UINT16      emrs1;
+-    UINT16      emrs1Wr;
+-    UINT16      emrs2;
+-    UINT16      emrs3;
+-    UINT16      emrs4;
+-    UINT16      emrs5;
+-    UINT16      emrs5Wr;
+-    UINT16      emrs6;
+-    UINT16      emrs7;
+-    UINT8       phy_rddata_set;
+-    UINT8       phyif_tim_rdcs;
+-    UINT8       phyif_tim_rden;
+-    UINT8       phyif_tim_wden;
+-    UINT8       phyif_tim_wdda;
+-    UINT8       phyif_tim_wdcs;
+-    UINT8       per_cs_training_en;
+-    UINT32      phyRdDataEnIeDly;
+-    UINT32      phyPadCalConfig;
+-    UINT32      phyDqsFallRiseDelay;
+-    UINT32      ddrcCfgDfiLat0;
+-    UINT32      ddrcCfgDfiLat1;
+-    UINT32      parityLatency;
+-    UINT32      dimm_parity_en;
+-    DDRC_TIMING ddrcTiming;
+-    DDR_DIMM    Dimm[MAX_DIMM];
+-    MARGIN_RESULT sMargin;
+-}DDR_CHANNEL;
+-
+-typedef struct _NVRAM_RANK{
++typedef struct _NVRAM_RANK_DATA {
+     UINT16      MR0;
+     UINT16      MR1;
+     UINT16      MR2;
+@@ -273,15 +67,15 @@ typedef struct _NVRAM_RANK{
+     UINT16      MR4;
+     UINT16      MR5;
+     UINT16      MR6[9];
+-}NVRAM_RANK;
++} NVRAM_RANK_DATA;
+ 
+-typedef struct _NVRAM_DIMM{
+-    NVRAM_RANK      Rank[MAX_RANK_DIMM];
+-}NVRAM_DIMM;
++typedef struct _NVRAM_DIMM_DATA {
++    NVRAM_RANK_DATA      Rank[MAX_RANK_DIMM];
++} NVRAM_DIMM_DATA;
+ 
+ 
+-typedef struct _NVRAM_CHANNEL{
+-    NVRAM_DIMM      Dimm[MAX_DIMM];
++typedef struct _NVRAM_CHANNEL_DATA {
++    NVRAM_DIMM_DATA      Dimm[MAX_DIMM];
+     UINT32          DDRC_CFG_ECC;
+     UINT32          DDRC_CFG_WORKMODE;
+     UINT32          DDRC_CFG_WORKMODE1;
+@@ -325,94 +119,70 @@ typedef struct _NVRAM_CHANNEL{
+     UINT32          DDRC_CFG_DDRPHY;
+     UINT32          Config[24];
+     BOOLEAN         Status;
+-}NVRAM_CHANNEL;
++} NVRAM_CHANNEL_DATA;
+ 
+-typedef struct _NVRAM{
+-    UINT32          NvramCrc;
+-    NVRAM_CHANNEL   Channel[MAX_SOCKET][MAX_CHANNEL];
+-    UINT32          DdrFreqIdx;
++typedef struct _NVRAM_DATA {
++    UINT32              NvramCrc;
++    NVRAM_CHANNEL_DATA  Channel[MAX_SOCKET][MAX_CHANNEL];
++    UINT32              DdrFreqIdx;
+ 
+-}NVRAM;
++} NVRAM_DATA;
+ 
+-typedef struct _MEMORY{
+-    UINT8           Config0;
+-    UINT8           marginTest;
+-    UINT8           Config1[5];
+-    UINT8           ErrorBypass; //register of spd mirror mode
+-    UINT32          Config2;
+-}MEMORY;
++struct DDR_RANK_DATA {
++    BOOLEAN     Enabled;
++};
+ 
+-typedef struct _NUMAINFO{
++typedef struct _DDR_DIMM_DATA {
++    BOOLEAN         Enabled;
++    UINT8           DramType;           //Byte 2
++    UINT8           ModuleType;         //Byte 3
++    UINT8           BankNum;            //Byte 4
++    UINT8           RowBits;            //Byte 5
++    UINT8           ColBits;            //Byte 5
++    UINT8           SpdVdd;             //Byte 6
++    UINT8           RankNum;            //Byte 7
++    UINT8           PrimaryBusWidth;    //Byte 8
++    UINT8           ExtensionBusWidth;  //Byte 8
++    UINT8           SpdModPart[SPD_MODULE_PART];                // Module Part Number
++    UINT8           SpdModPartDDR4[SPD_MODULE_PART_DDR4];       // Module Part Number DDR4
++    UINT16          SpdMMfgId;              // Module Mfg Id from SPD
++    UINT32          SpdSerialNum;
++    UINT32          RankSize;
++    UINT16          DimmSize;
++    UINT16          DimmSpeed;
++    UINT16          SpdMMDate;
++    struct DDR_RANK_DATA    Rank[MAX_RANK_DIMM];
++} DDR_DIMM_DATA;
++
++typedef struct _DDR_CHANNEL_DATA {
++    BOOLEAN         Enabled;
++    DDR_DIMM_DATA   Dimm[MAX_DIMM];
++    UINT8           CurrentDimmNum;
++} DDR_CHANNEL_DATA;
++
++typedef struct _MEMORY_DATA {
++    UINT8           RascBypass;
++} MEMORY_DATA;
++
++typedef struct _NUMAINFO_DATA {
+     UINT8           NodeId;
+     UINT64          Base;
+     UINT64          Length;
+     UINT32          ScclInterleaveEn;
+-}NUMAINFO;
+-
+-
+-typedef struct _GBL_DATA
+-{
+-    DDR_CHANNEL Channel[MAX_SOCKET][MAX_CHANNEL];
+-    UINT8       DramType;
+-    UINT8       CurrentDimmNum;
+-    UINT8       CurrentRankNum;
+-    UINT8       MaxSPCNum;
+-    UINT32      Freq;
+-    UINT32      SpdTckMtb;
+-    UINT32      SpdTckFtb;
+-    UINT32      SpdTck;
+-    UINT32      Tck;
+-    UINT32      DdrFreqIdx;
+-    UINT32      DevParaFreqIdx; //Maximum frequency of DDR device
+-    UINT32      MemSize;
+-    UINT32      EccEn;
+-
+-    BOOLEAN     SetupExist;
+-    UINT8       warmReset;
+-    UINT8       needColdReset;
+-
+-    UINT8       cl;
+-    UINT8       cwl;
+-    UINT8       pl;
+-    UINT8       wr_pre_2t_en;
+-    UINT8       rd_pre_2t_en;
+-    UINT8       cmd_2t_en;
+-    UINT8       ddr4_parity_en;
+-    UINT8       wr_dbi_en;
+-    UINT8       wr_dm_en;
+-    UINT8       ddr4_crc_en;
+-    UINT16      emrs0;
+-    UINT16      emrs1;
+-    UINT16      emrs2;
+-    UINT16      emrs3;
+-    UINT16      emrs4;
+-    UINT16      emrs5;
+-    UINT16      emrs6;
+-    UINT16      emrs7;
+-    UINT8       phy_rddata_set;
+-    UINT8       phyif_tim_rdcs;
+-    UINT8       phyif_tim_rden;
+-    UINT8       phyif_tim_wden;
+-    UINT8       phyif_tim_wdda;
+-    UINT8       phyif_tim_wdcs;
+-    UINT8       dimm_trtr;
+-    UINT8       dimm_twtw;
+-    UINT8       rnk_trtr;
+-    UINT8       rnk_twtw;
+-    UINT8       rnk_trtw;
+-    UINT8       rnk_twtr;
+-    UINT8       per_cs_training_en;
+-    UINT8       scale;
+-    UINT8       ddrFreq;
+-    UINT8       debugNeed;
+-    UINT8       ddr3OdtEnable;
+-    double      fprd;
+-    BOOLEAN     chipIsEc;
+-    NVRAM       nvram;
+-    MEMORY      mem;
+-    NUMAINFO    NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE];
+-
+-}GBL_DATA, *pGBL_DATA;
++} NUMAINFO_DATA;
++
++
++typedef struct _GBL_DATA_INTERFACE {
++    DDR_CHANNEL_DATA        Channel[MAX_SOCKET][MAX_CHANNEL];
++    UINT32                  DdrFreqIdx;
++    UINT32                  Freq;
++    UINT32                  EccEn;
++    UINT32                  MemSize;
++    BOOLEAN                 SetupExist;
++    NVRAM_DATA              NvRamData;
++    MEMORY_DATA             MemData;
++    NUMAINFO_DATA           NumaInfo[MAX_SOCKET][MAX_NUM_PER_TYPE];
++} GBL_INTERFACE;
+ 
+ typedef union {
+     struct {
+diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+index 7d06fccc2b..f5869841dc 100644
+--- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
++++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+@@ -56,7 +56,7 @@ UpdateSrat (
+   UINT8               Skt = 0;
+   UINTN               Index = 0;
+   VOID                *HobList;
+-  GBL_DATA            *Gbl_Data;
++  GBL_INTERFACE       *Gbl_Data;
+   UINTN               Base;
+   UINTN               Size;
+   UINT8               NodeId;
+@@ -69,7 +69,7 @@ UpdateSrat (
+   if (HobList == NULL) {
+     return EFI_UNSUPPORTED;
+   }
+-  Gbl_Data = (GBL_DATA*)GetNextGuidHob(&gHisiEfiMemoryMapGuid, HobList);
++  Gbl_Data = (GBL_INTERFACE*)GetNextGuidHob(&gHisiEfiMemoryMapGuid, HobList);
+   if (Gbl_Data == NULL) {
+     DEBUG((DEBUG_ERROR, "Get next Guid HOb fail.\n"));
+     return EFI_NOT_FOUND;
+diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c
+index da714c9e22..7d3005eb14 100644
+--- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c
++++ b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.c
+@@ -45,7 +45,7 @@ SmbiosGetManufacturer (
+ 
+ VOID
+ SmbiosGetPartNumber (
+-  IN pGBL_DATA          pGblData,
++  IN GBL_INTERFACE      *pGblData,
+   IN UINT8              Skt,
+   IN UINT8              Ch,
+   IN UINT8              Dimm,
+@@ -78,7 +78,7 @@ SmbiosGetPartNumber (
+ 
+ VOID
+ SmbiosGetSerialNumber (
+-  IN pGBL_DATA          pGblData,
++  IN GBL_INTERFACE      *pGblData,
+   IN UINT8              Skt,
+   IN UINT8              Ch,
+   IN UINT8              Dimm,
+@@ -96,14 +96,14 @@ SmbiosGetSerialNumber (
+ 
+ BOOLEAN
+ IsDimmPresent (
+-  IN  pGBL_DATA          pGblData,
++  IN  GBL_INTERFACE      *pGblData,
+   IN  UINT8              Skt,
+   IN  UINT8              Ch,
+   IN  UINT8              Dimm
+ )
+ {
+-    if (pGblData->Channel[Skt][Ch].Status == FALSE ||
+-          pGblData->Channel[Skt][Ch].Dimm[Dimm].Status == FALSE)
++    if (pGblData->Channel[Skt][Ch].Enabled == FALSE ||
++        pGblData->Channel[Skt][Ch].Dimm[Dimm].Enabled == FALSE)
+     {
+         return FALSE;
+     }
+@@ -115,7 +115,7 @@ IsDimmPresent (
+ 
+ UINT8
+ SmbiosGetMemoryType (
+-  IN  pGBL_DATA          pGblData,
++  IN  GBL_INTERFACE      *pGblData,
+   IN  UINT8              Skt,
+   IN  UINT8              Ch,
+   IN  UINT8              Dimm
+@@ -146,7 +146,7 @@ SmbiosGetMemoryType (
+ 
+ VOID
+ SmbiosGetTypeDetail (
+-  IN  pGBL_DATA             pGblData,
++  IN  GBL_INTERFACE         *pGblData,
+   IN  UINT8                 Skt,
+   IN  UINT8                 Ch,
+   IN  UINT8                 Dimm,
+@@ -186,7 +186,7 @@ SmbiosGetTypeDetail (
+ 
+ VOID
+ SmbiosGetDimmVoltageInfo (
+-  IN     pGBL_DATA             pGblData,
++  IN     GBL_INTERFACE         *pGblData,
+   IN     UINT8                 Skt,
+   IN     UINT8                 Ch,
+   IN     UINT8                 Dimm,
+@@ -281,7 +281,7 @@ SmbiosGetPartitionWidth (
+ 
+ EFI_STATUS
+ SmbiosAddType16Table (
+-  IN  pGBL_DATA          pGblData,
++  IN  GBL_INTERFACE      *pGblData,
+   OUT EFI_SMBIOS_HANDLE  *MemArraySmbiosHandle
+   )
+ {
+@@ -345,7 +345,7 @@ SmbiosAddType16Table (
+ 
+ EFI_STATUS
+ SmbiosAddType19Table (
+-  IN pGBL_DATA          pGblData,
++  IN GBL_INTERFACE      *pGblData,
+   IN EFI_SMBIOS_HANDLE  MemArraySmbiosHandle
+   )
+ {
+@@ -397,7 +397,7 @@ SmbiosAddType19Table (
+ 
+ EFI_STATUS
+ SmbiosAddType17Table (
+-  IN pGBL_DATA          pGblData,
++  IN GBL_INTERFACE      *pGblData,
+   IN UINT8              Skt,
+   IN UINT8              Ch,
+   IN UINT8              Dimm,
+@@ -692,7 +692,7 @@ MemorySubClassEntryPoint(
+     EFI_STATUS                      Status;
+     EFI_SMBIOS_PROTOCOL             *Smbios;
+     EFI_HOB_GUID_TYPE               *GuidHob;
+-    pGBL_DATA                       pGblData;
++    GBL_INTERFACE                   *pGblData;
+     EFI_SMBIOS_HANDLE               MemArraySmbiosHandle;
+     UINT8                           Skt, Ch, Dimm;
+ 
+@@ -702,7 +702,7 @@ MemorySubClassEntryPoint(
+         DEBUG((EFI_D_ERROR, "Could not get MemoryMap Guid hob.  %r\n"));
+         return EFI_NOT_FOUND;
+     }
+-    pGblData = (pGBL_DATA) GET_GUID_HOB_DATA(GuidHob);
++    pGblData = (GBL_INTERFACE*) GET_GUID_HOB_DATA(GuidHob);
+ 
+     //
+     // Locate dependent protocols
+-- 
+2.17.0
+
diff --git a/v2/v2-0002-Silicon-Hisilicon-Separate-PlatformArch.h.patch b/v2/v2-0002-Silicon-Hisilicon-Separate-PlatformArch.h.patch
new file mode 100644
index 0000000000..aa06d87e4e
--- /dev/null
+++ b/v2/v2-0002-Silicon-Hisilicon-Separate-PlatformArch.h.patch
@@ -0,0 +1,64 @@
+From 8f222866142663d081addf168aa3b10ea42566c4 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Fri, 20 Jul 2018 17:57:11 +0800
+Subject: [PATCH edk2-platforms v2 02/43] Silicon/Hisilicon: Separate
+ PlatformArch.h
+
+As the macro of PlatformArch.h is platform specific, so separate
+PlatformArch.h to Hi1610,Hi1616 for unifying D0x.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/{ => Hi1610}/Include/PlatformArch.h |  0
+ Silicon/Hisilicon/Hi1616/Include/PlatformArch.h       | 35 ++++++++++++++++++++
+ 2 files changed, 35 insertions(+)
+
+diff --git a/Silicon/Hisilicon/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+similarity index 100%
+rename from Silicon/Hisilicon/Include/PlatformArch.h
+rename to Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+new file mode 100644
+index 0000000000..bf0994a5e9
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+@@ -0,0 +1,35 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++
++
++#ifndef _PLATFORM_ARCH_H_
++#define _PLATFORM_ARCH_H_
++
++#define MAX_SOCKET      2
++#define MAX_DIE         4
++#define MAX_DDRC        2
++#define MAX_NODE        (MAX_SOCKET * MAX_DIE)
++#define MAX_CHANNEL     4
++#define MAX_DIMM        3
++#define MAX_RANK_CH     12
++#define MAX_RANK_DIMM   4
++// Max NUMA node number for each node type
++#define MAX_NUM_PER_TYPE 8
++
++#define S1_BASE               0x40000000000
++
++#endif
++
+-- 
+2.17.0
+
diff --git a/v2/v2-0003-Silicon-Hisilicon-Acpi-Move-some-macro-to-Platfor.patch b/v2/v2-0003-Silicon-Hisilicon-Acpi-Move-some-macro-to-Platfor.patch
new file mode 100644
index 0000000000..0dabbeae39
--- /dev/null
+++ b/v2/v2-0003-Silicon-Hisilicon-Acpi-Move-some-macro-to-Platfor.patch
@@ -0,0 +1,168 @@
+From 443c705936b3526f80994d8220a7c51b10b38420 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sat, 11 Aug 2018 15:14:10 +0800
+Subject: [PATCH edk2-platforms v2 03/43] Silicon/Hisilicon/Acpi: Move some
+ macro to PlatformArch.h
+
+ARM_ACPI_HEADER is used by a unify module in HwPkg,
+so move some macro to PlatformArch.h for unify D0x.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h | 27 +++-----------------
+ Silicon/Hisilicon/Hi1610/Include/PlatformArch.h            | 24 +++++++++++++++++
+ Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h    | 24 +----------------
+ Silicon/Hisilicon/Hi1616/Include/PlatformArch.h            | 23 +++++++++++++++++
+ 4 files changed, 51 insertions(+), 47 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h
+index 5a95b02055..28546bea99 100644
+--- a/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h
++++ b/Silicon/Hisilicon/Hi1610/Hi1610AcpiTables/Hi1610Platform.h
+@@ -1,8 +1,8 @@
+ /** @file
+ *
+ *  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+-*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+-*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*  Copyright (c) 2015-2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015-2018, Linaro Limited. All rights reserved.
+ *
+ *  This program and the accompanying materials
+ *  are licensed and made available under the terms and conditions of the BSD License
+@@ -20,28 +20,7 @@
+ #ifndef _HI1610_PLATFORM_H_
+ #define _HI1610_PLATFORM_H_
+ 
+-//
+-// ACPI table information used to initialize tables.
+-//
+-#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
+-#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64('H','I','P','0','6',' ',' ',' ') // OEM table id 8 bytes long
+-#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
+-#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32('I','N','T','L')
+-#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+-
+-// A macro to initialise the common header part of EFI ACPI tables as defined by
+-// EFI_ACPI_DESCRIPTION_HEADER structure.
+-#define ARM_ACPI_HEADER(Signature, Type, Revision) {              \
+-    Signature,                      /* UINT32  Signature */       \
+-    sizeof (Type),                  /* UINT32  Length */          \
+-    Revision,                       /* UINT8   Revision */        \
+-    0,                              /* UINT8   Checksum */        \
+-    { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
+-    EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+-    EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
+-    EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
+-    EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+-  }
++#include <../Include/PlatformArch.h>
+ 
+ #define HI1610_WATCHDOG_COUNT  2
+ 
+diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+index 45995c5893..8e5913447c 100644
+--- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+@@ -31,5 +31,29 @@
+ 
+ #define S1_BASE               0x40000000000
+ 
++
++//
++// ACPI table information used to initialize tables.
++//
++#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
++#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64 ('H','I','P','0','6',' ',' ',' ') // OEM table id 8 bytes long
++#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
++#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32 ('I','N','T','L')
++#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
++
++// A macro to initialise the common header part of EFI ACPI tables as defined by
++// EFI_ACPI_DESCRIPTION_HEADER structure.
++#define ARM_ACPI_HEADER(Signature, Type, Revision) {            \
++  Signature,                      /* UINT32  Signature */       \
++  sizeof (Type),                  /* UINT32  Length */          \
++  Revision,                       /* UINT8   Revision */        \
++  0,                              /* UINT8   Checksum */        \
++  { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
++  EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
++  EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
++  EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
++  EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
++  }
++
+ #endif
+ 
+diff --git a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
+index ad73aa2668..04f9e34a14 100644
+--- a/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
++++ b/Silicon/Hisilicon/Hi1616/D05AcpiTables/Hi1616Platform.h
+@@ -21,29 +21,7 @@
+ #define _HI1610_PLATFORM_H_
+ 
+ #include <IndustryStandard/Acpi.h>
+-
+-//
+-// ACPI table information used to initialize tables.
+-//
+-#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
+-#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long
+-#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
+-#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32('I','N','T','L')
+-#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
+-
+-// A macro to initialise the common header part of EFI ACPI tables as defined by
+-// EFI_ACPI_DESCRIPTION_HEADER structure.
+-#define ARM_ACPI_HEADER(Signature, Type, Revision) {              \
+-    Signature,                      /* UINT32  Signature */       \
+-    sizeof (Type),                  /* UINT32  Length */          \
+-    Revision,                       /* UINT8   Revision */        \
+-    0,                              /* UINT8   Checksum */        \
+-    { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
+-    EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
+-    EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
+-    EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
+-    EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+-  }
++#include <../Include/PlatformArch.h>
+ 
+ #define HI1616_WATCHDOG_COUNT  2
+ #define HI1616_GIC_STRUCTURE_COUNT  64
+diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+index bf0994a5e9..24167d1633 100644
+--- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+@@ -31,5 +31,28 @@
+ 
+ #define S1_BASE               0x40000000000
+ 
++//
++// ACPI table information used to initialize tables.
++//
++#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
++#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64 ('H','I','P','0','7',' ',' ',' ') // OEM table id 8 bytes long
++#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
++#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32 ('I','N','T','L')
++#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
++
++// A macro to initialise the common header part of EFI ACPI tables as defined by
++// EFI_ACPI_DESCRIPTION_HEADER structure.
++#define ARM_ACPI_HEADER(Signature, Type, Revision) {            \
++  Signature,                      /* UINT32  Signature */       \
++  sizeof (Type),                  /* UINT32  Length */          \
++  Revision,                       /* UINT8   Revision */        \
++  0,                              /* UINT8   Checksum */        \
++  { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
++  EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
++  EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
++  EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
++  EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
++  }
++
+ #endif
+ 
+-- 
+2.17.0
+
diff --git a/v2/v2-0004-Silicon-Hisilicon-D0x-Move-dimm-size-definition-t.patch b/v2/v2-0004-Silicon-Hisilicon-D0x-Move-dimm-size-definition-t.patch
new file mode 100644
index 0000000000..2176607cfb
--- /dev/null
+++ b/v2/v2-0004-Silicon-Hisilicon-D0x-Move-dimm-size-definition-t.patch
@@ -0,0 +1,57 @@
+From 62503a986ac8cc1222edfff18f6d611c9091e915 Mon Sep 17 00:00:00 2001
+From: Sun Yuanchen <sunyuanchen@huawei.com>
+Date: Fri, 29 Jun 2018 15:16:39 +0800
+Subject: [PATCH edk2-platforms v2 04/43] Silicon/Hisilicon/D0x: Move dimm size
+ definition to PlatformArch.h
+
+Unify MemorySubClassDxe by Moving dimm size macro definition
+to PlatformArch.h
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Sun Yuanchen <sunyuanchen@huawei.com>
+---
+ Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h | 2 --
+ Silicon/Hisilicon/Hi1610/Include/PlatformArch.h                     | 1 +
+ Silicon/Hisilicon/Hi1616/Include/PlatformArch.h                     | 1 +
+ 3 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h
+index c35ce39d61..0c201b4870 100644
+--- a/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h
++++ b/Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClass.h
+@@ -44,8 +44,6 @@
+ 
+ extern UINT8 MemorySubClassStrings[];
+ 
+-#define MAX_DIMM_SIZE       32  // In GB
+-
+ struct SPD_JEDEC_MANUFACTURER
+ {
+     UINT8  MfgIdLSB;
+diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+index 8e5913447c..2ff076901e 100644
+--- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+@@ -26,6 +26,7 @@
+ #define MAX_DIMM        3
+ #define MAX_RANK_CH     12
+ #define MAX_RANK_DIMM   4
++#define MAX_DIMM_SIZE   32  // In GB
+ // Max NUMA node number for each node type
+ #define MAX_NUM_PER_TYPE 8
+ 
+diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+index 24167d1633..60a60593be 100644
+--- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+@@ -26,6 +26,7 @@
+ #define MAX_DIMM        3
+ #define MAX_RANK_CH     12
+ #define MAX_RANK_DIMM   4
++#define MAX_DIMM_SIZE   32  // In GB
+ // Max NUMA node number for each node type
+ #define MAX_NUM_PER_TYPE 8
+ 
+-- 
+2.17.0
+
diff --git a/v2/v2-0005-Silicon-Hisilicon-D0x-Move-RAS-macro-to-PlatformA.patch b/v2/v2-0005-Silicon-Hisilicon-D0x-Move-RAS-macro-to-PlatformA.patch
new file mode 100644
index 0000000000..c4285bacab
--- /dev/null
+++ b/v2/v2-0005-Silicon-Hisilicon-D0x-Move-RAS-macro-to-PlatformA.patch
@@ -0,0 +1,68 @@
+From a36aa321b03a58b090f1cdbf54363a0f0bca40e6 Mon Sep 17 00:00:00 2001
+From: Sun Yuanchen <sunyuanchen@huawei.com>
+Date: Tue, 3 Jul 2018 18:14:59 +0800
+Subject: [PATCH edk2-platforms v2 05/43] Silicon/Hisilicon/D0x: Move RAS macro
+ to PlatformArch.h
+
+Move some RAS macros definition to PlatformArch.h for
+unifying D0x
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Sun Yuanchen <sunyuanchen@huawei.com>
+---
+ Silicon/Hisilicon/Hi1610/Include/PlatformArch.h |  9 +++++++--
+ Silicon/Hisilicon/Hi1616/Include/PlatformArch.h | 12 ++++++++++++
+ 2 files changed, 19 insertions(+), 2 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+index 2ff076901e..f39ae0748c 100644
+--- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+@@ -1,7 +1,7 @@
+ /** @file
+ *
+-*  Copyright (c) 2015, Hisilicon Limited. All rights reserved.
+-*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*  Copyright (c) 2015 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015 - 2018, Linaro Limited. All rights reserved.
+ *
+ *  This program and the accompanying materials
+ *  are licensed and made available under the terms and conditions of the BSD License
+@@ -32,6 +32,11 @@
+ 
+ #define S1_BASE               0x40000000000
+ 
++#define RASC_BASE                (0x5000)
++/* configuration register for Rank statistical information */
++#define RASC_CFG_INFOIDX_REG     (RASC_BASE + 0x5C)
++/* configuration register for Sparing level */
++#define RASC_CFG_SPLVL_REG       (RASC_BASE + 0xB8)
+ 
+ //
+ // ACPI table information used to initialize tables.
+diff --git a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+index 60a60593be..e02e4bdabd 100644
+--- a/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1616/Include/PlatformArch.h
+@@ -30,6 +30,18 @@
+ // Max NUMA node number for each node type
+ #define MAX_NUM_PER_TYPE 8
+ 
++#define RASC_BASE                (0x5000)
++/* configuration register for Rank statistical information */
++#define RASC_CFG_INFOIDX_REG     (RASC_BASE + 0x5C)
++/* configuration register for Sparing level */
++#define RASC_CFG_SPLVL_REG       (RASC_BASE + 0xB8)
++
++// for acpi
++#define NODE_IN_SOCKET                                  2
++#define CORE_NUM_PER_SOCKET                             32
++#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT        10
++#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT       8
++
+ #define S1_BASE               0x40000000000
+ 
+ //
+-- 
+2.17.0
+
diff --git a/v2/v2-0006-Hisilicon-D0x-Move-CustomData.Fv-to-common-path-o.patch b/v2/v2-0006-Hisilicon-D0x-Move-CustomData.Fv-to-common-path-o.patch
new file mode 100644
index 0000000000..04b2bb9a35
--- /dev/null
+++ b/v2/v2-0006-Hisilicon-D0x-Move-CustomData.Fv-to-common-path-o.patch
@@ -0,0 +1,45 @@
+From b9b60c7ac88cad3d1d568c80b72ae2c0cc31caaa Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sun, 5 Aug 2018 21:58:57 +0800
+Subject: [PATCH edk2-platforms v2 06/43] Hisilicon/D0x: Move CustomData.Fv to
+ common path of Hisilicon
+
+The CustomData.Fv is moved to Platform/Hisilicon in edk2-non-osi,
+so update D0x fdf to reflect this.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D03/D03.fdf | 2 +-
+ Platform/Hisilicon/D05/D05.fdf | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
+index cf11aeccc8..4591f7b5b1 100644
+--- a/Platform/Hisilicon/D03/D03.fdf
++++ b/Platform/Hisilicon/D03/D03.fdf
+@@ -113,7 +113,7 @@ DATA = {
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ 
+ 0x002F0000|0x00010000
+-FILE = Platform/Hisilicon/D03/CustomData.Fv
++FILE = Platform/Hisilicon/D0x-CustomData.Fv
+ 
+ ################################################################################
+ #
+diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
+index 701804360e..6227607ffe 100644
+--- a/Platform/Hisilicon/D05/D05.fdf
++++ b/Platform/Hisilicon/D05/D05.fdf
+@@ -113,7 +113,7 @@ DATA = {
+ gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ 
+ 0x002F0000|0x00010000
+-FILE = Platform/Hisilicon/D03/CustomData.Fv
++FILE = Platform/Hisilicon/D0x-CustomData.Fv
+ 
+ ################################################################################
+ #
+-- 
+2.17.0
+
diff --git a/v2/v2-0007-Hisilicon-D0x-Move-IpmiCmdLib-to-common-path-of-H.patch b/v2/v2-0007-Hisilicon-D0x-Move-IpmiCmdLib-to-common-path-of-H.patch
new file mode 100644
index 0000000000..e9a44875e5
--- /dev/null
+++ b/v2/v2-0007-Hisilicon-D0x-Move-IpmiCmdLib-to-common-path-of-H.patch
@@ -0,0 +1,45 @@
+From 28d55a316e744b645be9c123d63a1f94880498c9 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Tue, 7 Aug 2018 23:01:10 +0800
+Subject: [PATCH edk2-platforms v2 07/43] Hisilicon/D0x: Move IpmiCmdLib to
+ common path of Hisilicon
+
+The IpmiCmdLib is moved to Silicon/Hisilicon in edk2-non-osi,
+so update D0x dsc to reflect this.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D03/D03.dsc | 2 +-
+ Platform/Hisilicon/D05/D05.dsc | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
+index 38548a0f23..c12790ba59 100644
+--- a/Platform/Hisilicon/D03/D03.dsc
++++ b/Platform/Hisilicon/D03/D03.dsc
+@@ -38,7 +38,7 @@
+   I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
+   TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ 
+-  IpmiCmdLib|Silicon/Hisilicon/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
++  IpmiCmdLib|Silicon/Hisilicon/Library/IpmiCmdLib/IpmiCmdLib.inf
+ 
+   NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+   DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
+index f2bbf27639..94d386582e 100644
+--- a/Platform/Hisilicon/D05/D05.dsc
++++ b/Platform/Hisilicon/D05/D05.dsc
+@@ -41,7 +41,7 @@
+   I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
+   TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
+ 
+-  IpmiCmdLib|Silicon/Hisilicon/Hi1610/Library/IpmiCmdLib/IpmiCmdLib.inf
++  IpmiCmdLib|Silicon/Hisilicon/Library/IpmiCmdLib/IpmiCmdLib.inf
+ 
+   NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+   DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+-- 
+2.17.0
+
diff --git a/v2/v2-0008-Hisilicon-D0x-Unify-FlashFvbDxe-driver.patch b/v2/v2-0008-Hisilicon-D0x-Unify-FlashFvbDxe-driver.patch
new file mode 100644
index 0000000000..e40ec75c44
--- /dev/null
+++ b/v2/v2-0008-Hisilicon-D0x-Unify-FlashFvbDxe-driver.patch
@@ -0,0 +1,170 @@
+From 88f30696ccd1a22e7cbd776fae01d30bd63a46fb Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Wed, 4 Jul 2018 16:42:31 +0800
+Subject: [PATCH edk2-platforms v2 08/43] Hisilicon/D0x: Unify FlashFvbDxe
+ driver
+
+Add PcdSFCMEM0BaseAddress and switch three 32-bit macro
+PcdFlashNvStorage of D05/D03 to 64-bit for unifying FlashFvbDxe
+driver.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D03/D03.fdf                        |  6 +++---
+ Platform/Hisilicon/D05/D05.fdf                        |  6 +++---
+ Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf |  7 ++++---
+ Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c   | 22 ++++++++++----------
+ 4 files changed, 21 insertions(+), 20 deletions(-)
+
+diff --git a/Platform/Hisilicon/D03/D03.fdf b/Platform/Hisilicon/D03/D03.fdf
+index 4591f7b5b1..b23765020d 100644
+--- a/Platform/Hisilicon/D03/D03.fdf
++++ b/Platform/Hisilicon/D03/D03.fdf
+@@ -69,7 +69,7 @@ FILE = Platform/Hisilicon/D03/bl1.bin
+ FILE = Platform/Hisilicon/D03/fip.bin
+ 
+ 0x002D0000|0x0000E000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ DATA = {
+   ## This is the EFI_FIRMWARE_VOLUME_HEADER
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+@@ -97,7 +97,7 @@ DATA = {
+ }
+ 
+ 0x002DE000|0x00002000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ #NV_FTW_WORKING
+ DATA = {
+   # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
+@@ -110,7 +110,7 @@ DATA = {
+ }
+ 
+ 0x002E0000|0x00010000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ 
+ 0x002F0000|0x00010000
+ FILE = Platform/Hisilicon/D0x-CustomData.Fv
+diff --git a/Platform/Hisilicon/D05/D05.fdf b/Platform/Hisilicon/D05/D05.fdf
+index 6227607ffe..6fa5b5e6c8 100644
+--- a/Platform/Hisilicon/D05/D05.fdf
++++ b/Platform/Hisilicon/D05/D05.fdf
+@@ -69,7 +69,7 @@ FILE = Platform/Hisilicon/D05/bl1.bin
+ FILE = Platform/Hisilicon/D05/fip.bin
+ 
+ 0x002D0000|0x0000E000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+ DATA = {
+   ## This is the EFI_FIRMWARE_VOLUME_HEADER
+   0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+@@ -97,7 +97,7 @@ DATA = {
+ }
+ 
+ 0x002DE000|0x00002000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+ #NV_FTW_WORKING
+ DATA = {
+   # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
+@@ -110,7 +110,7 @@ DATA = {
+ }
+ 
+ 0x002E0000|0x00010000
+-gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ 
+ 0x002F0000|0x00010000
+ FILE = Platform/Hisilicon/D0x-CustomData.Fv
+diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+index 09ec7ce08b..f8be4741ef 100644
+--- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
++++ b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+@@ -54,14 +54,15 @@
+   gHisiSpiFlashProtocolGuid
+ 
+ [Pcd.common]
+-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase
++  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64
+   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
+-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase
++  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64
+   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
+-  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase
++  gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64
+   gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
+ 
+   gArmPlatformTokenSpaceGuid.PcdNorFlashCheckBlockLocked
++  gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress
+ 
+ [Depex]
+   gHisiSpiFlashProtocolGuid
+diff --git a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c
+index 7c6b64c33e..e18cc9e06e 100644
+--- a/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c
++++ b/Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.c
+@@ -28,8 +28,8 @@ FLASH_DESCRIPTION mFlashDevices[FLASH_DEVICE_COUNT] =
+ {
+     {
+         // UEFI Variable Services non-volatile storage
+-        0xa4000000,
+-        FixedPcdGet32(PcdFlashNvStorageVariableBase),
++        FixedPcdGet64 (PcdSFCMEM0BaseAddress),
++        FixedPcdGet64 (PcdFlashNvStorageVariableBase64),
+         0x20000,
+         SIZE_64KB,
+         {0xCC2CBF29, 0x1498, 0x4CDD, {0x81, 0x71, 0xF8, 0xB6, 0xB4, 0x1D, 0x09, 0x09}}
+@@ -145,8 +145,8 @@ InitializeFvAndVariableStoreHeaders (
+     Headers = AllocateZeroPool(HeadersLength);
+ 
+     // FirmwareVolumeHeader->FvLength is declared to have the Variable area AND the FTW working area AND the FTW Spare contiguous.
+-    ASSERT(PcdGet32(PcdFlashNvStorageVariableBase) + PcdGet32(PcdFlashNvStorageVariableSize) == PcdGet32(PcdFlashNvStorageFtwWorkingBase));
+-    ASSERT(PcdGet32(PcdFlashNvStorageFtwWorkingBase) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) == PcdGet32(PcdFlashNvStorageFtwSpareBase));
++    ASSERT(PcdGet64(PcdFlashNvStorageVariableBase64) + PcdGet32(PcdFlashNvStorageVariableSize) == PcdGet64(PcdFlashNvStorageFtwWorkingBase64));
++    ASSERT(PcdGet64(PcdFlashNvStorageFtwWorkingBase64) + PcdGet32(PcdFlashNvStorageFtwWorkingSize) == PcdGet64(PcdFlashNvStorageFtwSpareBase64));
+ 
+     // Check if the size of the area is at least one block size
+     ASSERT((PcdGet32(PcdFlashNvStorageVariableSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageVariableSize) / Instance->Media.BlockSize > 0));
+@@ -154,9 +154,9 @@ InitializeFvAndVariableStoreHeaders (
+     ASSERT((PcdGet32(PcdFlashNvStorageFtwSpareSize) > 0) && ((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareSize) / Instance->Media.BlockSize > 0));
+ 
+     // Ensure the Variable area Base Addresses are aligned on a block size boundaries
+-    ASSERT((UINT32)PcdGet32(PcdFlashNvStorageVariableBase) % Instance->Media.BlockSize == 0);
+-    ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwWorkingBase) % Instance->Media.BlockSize == 0);
+-    ASSERT((UINT32)PcdGet32(PcdFlashNvStorageFtwSpareBase) % Instance->Media.BlockSize == 0);
++    ASSERT((UINT32)PcdGet64(PcdFlashNvStorageVariableBase64) % Instance->Media.BlockSize == 0);
++    ASSERT((UINT32)PcdGet64(PcdFlashNvStorageFtwWorkingBase64) % Instance->Media.BlockSize == 0);
++    ASSERT((UINT32)PcdGet64(PcdFlashNvStorageFtwSpareBase64) % Instance->Media.BlockSize == 0);
+ 
+     //
+     // EFI_FIRMWARE_VOLUME_HEADER
+@@ -855,10 +855,10 @@ FvbInitialize (
+     UINT32      FvbNumLba;
+ 
+     Instance->Initialized = TRUE;
+-    mFlashNvStorageVariableBase = FixedPcdGet32 (PcdFlashNvStorageVariableBase);
++    mFlashNvStorageVariableBase = FixedPcdGet64 (PcdFlashNvStorageVariableBase64);
+ 
+     // Set the index of the first LBA for the FVB
+-    Instance->StartLba = (PcdGet32 (PcdFlashNvStorageVariableBase) - Instance->RegionBaseAddress) / Instance->Media.BlockSize;
++    Instance->StartLba = (PcdGet64 (PcdFlashNvStorageVariableBase64) - Instance->RegionBaseAddress) / Instance->Media.BlockSize;
+ 
+     // Determine if there is a valid header at the beginning of the Flash
+     Status = ValidateFvHeader (Instance);
+@@ -1208,8 +1208,8 @@ FlashFvbInitialize (
+     {
+         // Check if this Flash device contain the variable storage region
+         ContainVariableStorage =
+-            (FlashDevices[Index].RegionBaseAddress <= (UINT32)PcdGet32 (PcdFlashNvStorageVariableBase)) &&
+-            ((UINT32)(PcdGet32 (PcdFlashNvStorageVariableBase) + PcdGet32 (PcdFlashNvStorageVariableSize)) <= FlashDevices[Index].RegionBaseAddress + FlashDevices[Index].Size);
++             (FlashDevices[Index].RegionBaseAddress <= PcdGet64 (PcdFlashNvStorageVariableBase64)) &&
++             ((PcdGet64 (PcdFlashNvStorageVariableBase64) + PcdGet32 (PcdFlashNvStorageVariableSize)) <= FlashDevices[Index].RegionBaseAddress + FlashDevices[Index].Size);
+ 
+         Status = FlashCreateInstance (
+                      FlashDevices[Index].DeviceBaseAddress,
+-- 
+2.17.0
+
diff --git a/v2/v2-0009-Hisilicon-D0X-Rename-the-global-variable-gDS3231R.patch b/v2/v2-0009-Hisilicon-D0X-Rename-the-global-variable-gDS3231R.patch
new file mode 100644
index 0000000000..6dcf3efe16
--- /dev/null
+++ b/v2/v2-0009-Hisilicon-D0X-Rename-the-global-variable-gDS3231R.patch
@@ -0,0 +1,142 @@
+From edcaba67c20c15d40ec09fd0f4fc38dc86349cd2 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Fri, 29 Jun 2018 15:33:43 +0800
+Subject: [PATCH edk2-platforms v2 09/43] Hisilicon/D0X: Rename the global
+ variable gDS3231RtcDevice
+
+The global variable gDS3231RtcDevice is used by several
+modules included common module in HwPkg. Renaming it
+with a general name is proper.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Include/Library/OemMiscLib.h                                 | 2 +-
+ Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c | 8 ++++----
+ Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c             | 2 +-
+ Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c                 | 2 +-
+ Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c      | 8 ++++----
+ 5 files changed, 11 insertions(+), 11 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+index 6f18c0fa72..87cb498dd7 100644
+--- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
++++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+@@ -34,7 +34,7 @@ extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX];
+ BOOLEAN OemIsSocketPresent (UINTN Socket);
+ VOID CoreSelectBoot(VOID);
+ VOID OemPcieResetAndOffReset(void);
+-extern I2C_DEVICE gDS3231RtcDevice;
++extern I2C_DEVICE gRtcDevice;
+ 
+ UINTN OemGetSocketNumber(VOID);
+ UINTN OemGetDdrChannel (VOID);
+diff --git a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
+index 07fa52aa78..f6dbcf6b75 100644
+--- a/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
++++ b/Platform/Hisilicon/D03/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
+@@ -41,7 +41,7 @@
+ #include <Library/CpldD03.h>
+ #include <Library/CpldIoLib.h>
+ 
+-extern I2C_DEVICE gDS3231RtcDevice;
++extern I2C_DEVICE gRtcDevice;
+ 
+ STATIC BOOLEAN       mDS3231Initialized = FALSE;
+ 
+@@ -117,7 +117,7 @@ InitializeDS3231 (
+   // Prepare the hardware
+   (VOID)IdentifyDS3231();
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+   Status = I2CInit(Dev.Socket,Dev.Port,Normal);
+   if (EFI_ERROR (Status)) {
+@@ -199,7 +199,7 @@ LibGetTime (
+     }
+   }
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+   Status |= I2CRead(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+ 
+@@ -299,7 +299,7 @@ LibSetTime (
+     }
+   }
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+   Temp = ((Time->Second/10)<<4) | (Time->Second%10);
+   MicroSecondDelay(1000);
+diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
+index 66d62895a6..4771cb900c 100644
+--- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
++++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/BoardFeature2PHi1610.c
+@@ -25,7 +25,7 @@
+ #include <Library/I2CLib.h>
+ #include <Library/HiiLib.h>
+ 
+-I2C_DEVICE gDS3231RtcDevice = {
++I2C_DEVICE gRtcDevice = {
+     .Socket = 0,
+     .Port = 6,
+     .DeviceType = DEVICE_TYPE_SPD,
+diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
+index 15a509be5d..ae4c194070 100644
+--- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
++++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/BoardFeatureD05.c
+@@ -26,7 +26,7 @@
+ #include <Protocol/Smbios.h>
+ 
+ 
+-I2C_DEVICE gDS3231RtcDevice = {
++I2C_DEVICE gRtcDevice = {
+   .Socket = 0,
+   .Port = 4,
+   .DeviceType = DEVICE_TYPE_SPD,
+diff --git a/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c b/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
+index 02d6d7f14d..105eb15635 100644
+--- a/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
++++ b/Silicon/Hisilicon/Library/DS3231RealTimeClockLib/DS3231RealTimeClockLib.c
+@@ -39,7 +39,7 @@
+ #include <Library/I2CLib.h>
+ #include "DS3231RealTimeClock.h"
+ 
+-extern I2C_DEVICE gDS3231RtcDevice;
++extern I2C_DEVICE gRtcDevice;
+ 
+ STATIC BOOLEAN       mDS3231Initialized = FALSE;
+ 
+@@ -67,7 +67,7 @@ InitializeDS3231 (
+   // Prepare the hardware
+   (VOID)IdentifyDS3231();
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+   Status = I2CInit(Dev.Socket,Dev.Port,Normal);
+   if (EFI_ERROR (Status)) {
+@@ -143,7 +143,7 @@ LibGetTime (
+     }
+   }
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+ 
+   Status |= I2CRead(&Dev,DS3231_REGADDR_MONTH,1,&Temp);
+@@ -233,7 +233,7 @@ LibSetTime (
+     }
+   }
+ 
+-  (VOID) CopyMem(&Dev, &gDS3231RtcDevice, sizeof(Dev));
++  (VOID) CopyMem (&Dev, &gRtcDevice, sizeof(Dev));
+ 
+   Temp = ((Time->Second/10)<<4) | (Time->Second%10);
+   MicroSecondDelay(1000);
+-- 
+2.17.0
+
diff --git a/v2/v2-0010-Hisilicon-D06-Add-several-base-file-for-D06.patch b/v2/v2-0010-Hisilicon-D06-Add-several-base-file-for-D06.patch
new file mode 100644
index 0000000000..66f1b47ff7
--- /dev/null
+++ b/v2/v2-0010-Hisilicon-D06-Add-several-base-file-for-D06.patch
@@ -0,0 +1,1160 @@
+From d4e234e7fdabe58f9823bba7b194af03ec9f69e1 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Wed, 13 Jun 2018 20:13:08 +0800
+Subject: [PATCH edk2-platforms v2 10/43] Hisilicon/D06: Add several base file
+ for D06
+
+Add several base head files and add several build
+files for D06.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dec                       |  29 ++
+ Platform/Hisilicon/D06/D06.dsc                       | 455 ++++++++++++++++++++
+ Platform/Hisilicon/D06/D06.fdf                       | 351 +++++++++++++++
+ Platform/Hisilicon/D06/Include/Library/CpldD06.h     |  37 ++
+ Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h |  85 ++++
+ Silicon/Hisilicon/Hi1620/Include/PlatformArch.h      |  61 +++
+ Silicon/Hisilicon/Include/Library/OemAddressMapLib.h |   6 +
+ Silicon/Hisilicon/Include/Library/OemNicLib.h        |  57 +++
+ 8 files changed, 1081 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dec b/Platform/Hisilicon/D06/D06.dec
+new file mode 100644
+index 0000000000..710f083eee
+--- /dev/null
++++ b/Platform/Hisilicon/D06/D06.dec
+@@ -0,0 +1,29 @@
++#/** @file
++#
++#    Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#    Copyright (c) 2018, Linaro Limited. All rights reserved.
++#
++#    This program and the accompanying materials
++#    are licensed and made available under the terms and conditions of the BSD License
++#    which accompanies this distribution. The full text of the license may be found at
++#    http://opensource.org/licenses/bsd-license.php
++#
++#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++#
++# D06 Package
++#
++#
++#
++
++[Defines]
++  DEC_SPECIFICATION              = 0x0001001A
++  PACKAGE_NAME                   = D06Pkg
++  PACKAGE_GUID                   = B46F75D7-3864-450D-86D9-A0346A882232
++  PACKAGE_VERSION                = 0.1
++
++[Includes]
++  Include
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+new file mode 100644
+index 0000000000..d14fce1159
+--- /dev/null
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -0,0 +1,455 @@
++#
++#  Copyright (c) 2011-2012, ARM Limited. All rights reserved.
++#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#  Copyright (c) 2018, Linaro Limited. All rights reserved.
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution.  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#
++
++################################################################################
++#
++# Defines Section - statements that will be processed to create a Makefile.
++#
++################################################################################
++[Defines]
++  PLATFORM_NAME                  = D06
++  PLATFORM_GUID                  = D0D445F1-B2CA-4101-9986-1B23525CBEA6
++  PLATFORM_VERSION               = 0.1
++  DSC_SPECIFICATION              = 0x0001001A
++  OUTPUT_DIRECTORY               = Build/$(PLATFORM_NAME)
++  SUPPORTED_ARCHITECTURES        = AARCH64
++  BUILD_TARGETS                  = DEBUG|NOOPT|RELEASE
++  SKUID_IDENTIFIER               = DEFAULT
++  FLASH_DEFINITION               = Platform/Hisilicon/$(PLATFORM_NAME)/$(PLATFORM_NAME).fdf
++  DEFINE NETWORK_IP6_ENABLE      = FALSE
++  DEFINE HTTP_BOOT_ENABLE        = FALSE
++  DEFINE SECURE_BOOT_ENABLE      = FALSE
++
++!include Silicon/Hisilicon/Hisilicon.dsc.inc
++
++[LibraryClasses.common]
++  ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
++  ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLib.inf
++
++
++  I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
++  TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
++  NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
++  DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
++  HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
++  UefiHiiServicesLib|MdeModulePkg/Library/UefiHiiServicesLib/UefiHiiServicesLib.inf
++  UdpIoLib|MdeModulePkg/Library/DxeUdpIoLib/DxeUdpIoLib.inf
++  IpIoLib|MdeModulePkg/Library/DxeIpIoLib/DxeIpIoLib.inf
++  OrderedCollectionLib|MdePkg/Library/BaseOrderedCollectionRedBlackTreeLib/BaseOrderedCollectionRedBlackTreeLib.inf
++  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
++  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
++  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
++  BootLogoLib|MdeModulePkg/Library/BootLogoLib/BootLogoLib.inf
++  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
++
++!if $(NETWORK_IP6_ENABLE) == TRUE
++  TcpIoLib|MdeModulePkg/Library/DxeTcpIoLib/DxeTcpIoLib.inf
++!endif
++
++!if $(HTTP_BOOT_ENABLE) == TRUE
++  HttpLib|MdeModulePkg/Library/DxeHttpLib/DxeHttpLib.inf
++!endif
++
++  CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
++
++  TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
++
++  CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
++  GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
++  BmcConfigBootLib|Silicon/Hisilicon/Library/BmcConfigBootLib/BmcConfigBootLib.inf
++  UefiBootManagerLib|MdeModulePkg/Library/UefiBootManagerLib/UefiBootManagerLib.inf
++  SortLib|MdeModulePkg/Library/UefiSortLib/UefiSortLib.inf
++  ReportStatusCodeLib|MdeModulePkg/Library/DxeReportStatusCodeLib/DxeReportStatusCodeLib.inf
++  DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf
++  PlatformBootManagerLib|Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
++  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
++  CustomizedDisplayLib|MdeModulePkg/Library/CustomizedDisplayLib/CustomizedDisplayLib.inf
++
++  # USB Requirements
++  UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
++
++  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
++!if $(SECURE_BOOT_ENABLE) == TRUE
++  FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
++!endif
++  PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
++
++[LibraryClasses.common.SEC]
++  ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
++
++
++[LibraryClasses.common.DXE_RUNTIME_DRIVER]
++  I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLibRuntime.inf
++  SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
++
++[BuildOptions]
++  GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/Silicon/Hisilicon/Hi1620/Include
++
++################################################################################
++#
++# Pcd Section - list of all EDK II PCD Entries defined by this Platform
++#
++################################################################################
++
++[PcdsFeatureFlag.common]
++
++  ## If TRUE, Graphics Output Protocol will be installed on virtual handle created by ConsplitterDxe.
++  #  It could be set FALSE to save size.
++  gEfiMdeModulePkgTokenSpaceGuid.PcdConOutGopSupport|TRUE
++  gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
++  gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE
++  gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
++
++[PcdsFixedAtBuild.common]
++  gArmPlatformTokenSpaceGuid.PcdCoreCount|48
++  gEmbeddedTokenSpaceGuid.PcdPrePiCpuMemorySize|48
++
++  gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x2000
++
++
++  # Stacks for MPCores in Normal World
++  gArmPlatformTokenSpaceGuid.PcdCPUCoresStackBase|0xA0E88000
++  gArmPlatformTokenSpaceGuid.PcdCPUCorePrimaryStackSize|0x40000
++
++  gArmTokenSpaceGuid.PcdSystemMemoryBase|0x00000000
++  gArmTokenSpaceGuid.PcdSystemMemorySize|0x3FC00000
++
++  # Size of the region used by UEFI in permanent memory (Reserved 64MB)
++  gArmPlatformTokenSpaceGuid.PcdSystemMemoryUefiRegionSize|0x10000000
++
++  gHisiTokenSpaceGuid.PcdSerDesFlowCtrlFlag|1
++
++  gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x2
++
++  ## Serial Terminal
++  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x94080000
++  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase|0x400094080000
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate|115200
++
++  gArmPlatformTokenSpaceGuid.PL011UartClkInHz|200000000
++
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits|8
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity|1
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits|1
++
++  gHisiTokenSpaceGuid.PcdIsMPBoot|1
++  gHisiTokenSpaceGuid.PcdSocketMask|0x3
++  !ifdef $(FIRMWARE_VER)
++    gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
++  !else
++    gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D06 UEFI RC0 - B308 (V0.38)"
++  !endif
++
++  gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
++
++  gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"0.38"
++
++  gHisiTokenSpaceGuid.PcdSystemProductName|L"D06"
++  gHisiTokenSpaceGuid.PcdSystemVersion|L"VER.A"
++  gHisiTokenSpaceGuid.PcdBaseBoardProductName|L"D06"
++  gHisiTokenSpaceGuid.PcdBaseBoardVersion|L"Estuary"
++
++  gHisiTokenSpaceGuid.PcdCPUInfo|L"Hisilicon 1620"
++
++  # TA
++  gHisiTokenSpaceGuid.PcdArmPrimaryCoreTemp|0x80010000
++  gArmTokenSpaceGuid.PcdGicDistributorBase|0xAE000000
++  gArmTokenSpaceGuid.PcdGicRedistributorsBase|0xAE100000
++  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0xFE000000
++
++
++
++  #
++  # ARM Architectual Timer Frequency
++  #
++  # Set it to 0 so that the code will read frequency from register and be
++  # adapted to 100M and 50M boards
++  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz|0
++  gEmbeddedTokenSpaceGuid.PcdTimerPeriod|10000
++
++
++  gEfiMdeModulePkgTokenSpaceGuid.PcdResetOnMemoryTypeInformationChange|FALSE
++  gEfiIntelFrameworkModulePkgTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }
++  gEfiMdeModulePkgTokenSpaceGuid.PcdBootManagerMenuFile|{ 0x21, 0xaa, 0x2c, 0x46, 0x14, 0x76, 0x03, 0x45, 0x83, 0x6e, 0x8a, 0xb6, 0xf4, 0x66, 0x23, 0x31 }
++  gHisiTokenSpaceGuid.PcdSysControlBaseAddress|0x94010000
++  gHisiTokenSpaceGuid.PcdMailBoxAddress|0x0000FFF8
++
++  gHisiTokenSpaceGuid.PcdCpldBaseAddress|0x80000000
++  gHisiTokenSpaceGuid.PcdSFCMEM0BaseAddress|0x204000000
++
++  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress|0x94000000
++
++  ## 2+1
++  gHisiTokenSpaceGuid.PcdPlatformDefaultPackageType|0x1
++
++  gHisiTokenSpaceGuid.PcdTopOfLowMemory|0x40000000
++
++  gHisiTokenSpaceGuid.PcdBottomOfHighMemory|0x1000000000
++
++  gHisiTokenSpaceGuid.PcdNORFlashBase|0x80000000
++  gHisiTokenSpaceGuid.PcdNORFlashCachableSize|0x8000000
++
++  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable|0x1
++  gHisiTokenSpaceGuid.PcdMacAddress|0xA47E0000
++
++  # PCIe ECAM Access BaseAddress
++  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xD0000000
++  gEmbeddedTokenSpaceGuid.PcdPrePiCpuIoSize|16
++
++  gHisiTokenSpaceGuid.Pcdsoctype|0x1620
++
++  # SMBIOS 3.0 only
++  #  BIT0 set indicates 32-bit entry point and table are produced.<BR>
++  #  BIT1 set indicates 64-bit entry point and table are produced.<BR>
++  gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosEntryPointProvideMethod|0x2
++
++  #
++  # ACPI Table Version
++  #
++  #   BIT 1 - EFI_ACPI_TABLE_VERSION_1_0B.<BR>
++  #   BIT 2 - EFI_ACPI_TABLE_VERSION_2_0.<BR>
++  #   BIT 3 - EFI_ACPI_TABLE_VERSION_3_0.<BR>
++  #   BIT 4 - EFI_ACPI_TABLE_VERSION_4_0.<BR>
++  #   BIT 5 - EFI_ACPI_TABLE_VERSION_5_0.<BR>
++  gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiExposedTableVersions|0x20
++
++  gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE
++  gArmTokenSpaceGuid.PcdPciIoTranslation|0x0
++
++################################################################################
++#
++# Components Section - list of all EDK II Modules needed by this Platform
++#
++################################################################################
++[Components.common]
++
++  #
++  # SEC
++  #
++
++  #
++  # PEI Phase modules
++  #
++  ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
++  MdeModulePkg/Core/Pei/PeiMain.inf
++  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
++
++  ArmPlatformPkg/PlatformPei/PlatformPeim.inf
++
++  ArmPkg/Drivers/CpuPei/CpuPei.inf
++  IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
++  MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
++  MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
++
++  Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
++
++  MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
++    <LibraryClasses>
++      NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
++  }
++
++  #
++  # DXE
++  #
++  MdeModulePkg/Core/Dxe/DxeMain.inf {
++    <LibraryClasses>
++      NULL|MdeModulePkg/Library/DxeCrc32GuidedSectionExtractLib/DxeCrc32GuidedSectionExtractLib.inf
++  }
++  MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
++
++
++  #
++  # Architectural Protocols
++  #
++  ArmPkg/Drivers/CpuDxe/CpuDxe.inf
++  MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
++
++
++!if $(SECURE_BOOT_ENABLE) == TRUE
++  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
++    <LibraryClasses>
++      NULL|SecurityPkg/Library/DxeImageVerificationLib/DxeImageVerificationLib.inf
++  }
++  SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
++!else
++  MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
++!endif
++  Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
++  MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf {
++    <LibraryClasses>
++      NULL|MdeModulePkg/Library/VarCheckUefiLib/VarCheckUefiLib.inf
++      BaseMemoryLib|MdePkg/Library/BaseMemoryLib/BaseMemoryLib.inf
++  }
++  MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
++  MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
++
++  MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
++  MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
++  EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf {
++    <LibraryClasses>
++      CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLibRuntime.inf
++  }
++  EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
++
++  MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
++  MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
++  MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
++  MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
++  MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
++
++  MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
++
++  ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
++
++  ArmPkg/Drivers/TimerDxe/TimerDxe.inf
++
++  MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
++  IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
++  #
++  #ACPI
++  #
++  MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
++  Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
++
++  Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
++
++  #
++  # Usb Support
++  #
++  MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
++  MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
++  MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
++  MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
++  MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
++  MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
++
++  #
++  #network
++  #
++  MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
++
++  MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
++  MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
++  MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
++  MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
++  MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
++  MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
++  MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
++!if $(NETWORK_IP6_ENABLE) == TRUE
++  NetworkPkg/Ip6Dxe/Ip6Dxe.inf
++  NetworkPkg/TcpDxe/TcpDxe.inf
++  NetworkPkg/Udp6Dxe/Udp6Dxe.inf
++  NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
++  NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
++  NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
++!else
++  MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
++  MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
++!endif
++  MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
++!if $(HTTP_BOOT_ENABLE) == TRUE
++  NetworkPkg/DnsDxe/DnsDxe.inf
++  NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
++  NetworkPkg/HttpDxe/HttpDxe.inf
++  NetworkPkg/HttpBootDxe/HttpBootDxe.inf
++!endif
++
++  MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
++  MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
++  MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
++  #
++  # FAT filesystem + GPT/MBR partitioning
++  #
++
++  MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
++  MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
++  FatPkg/EnhancedFatDxe/Fat.inf
++  MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
++
++  MdeModulePkg/Application/UiApp/UiApp.inf {
++    <LibraryClasses>
++      NULL|MdeModulePkg/Library/BootManagerUiLib/BootManagerUiLib.inf
++      NULL|MdeModulePkg/Library/DeviceManagerUiLib/DeviceManagerUiLib.inf
++      NULL|MdeModulePkg/Library/BootMaintenanceManagerUiLib/BootMaintenanceManagerUiLib.inf
++  }
++  #
++  # Bds
++  #
++  MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
++
++  MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
++  Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
++  Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
++  Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
++  Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
++
++  #PCIe Support
++  Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf
++  ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
++  MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf {
++    <LibraryClasses>
++      PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
++      PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
++      PciHostBridgeLib|MdeModulePkg/Library/PciHostBridgeLibNull/PciHostBridgeLibNull.inf
++  }
++
++  MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
++
++  MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
++
++  #
++  # Memory test
++  #
++  MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
++  MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
++  MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
++  MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
++
++  #
++  # UEFI application (Shell Embedded Boot Loader)
++  #
++  ShellPkg/Application/Shell/Shell.inf {
++    <LibraryClasses>
++      ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib.inf
++      NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1CommandsLib.inf
++      NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1CommandsLib.inf
++      HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsingLib.inf
++      PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf
++      BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCommandLib.inf
++!if $(NETWORK_IP6_ENABLE) == TRUE
++      NULL|ShellPkg/Library/UefiShellNetwork2CommandsLib/UefiShellNetwork2CommandsLib.inf
++!endif
++
++!if $(INCLUDE_DP) == TRUE
++      NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
++!endif #$(INCLUDE_DP)
++
++    <PcdsFixedAtBuild>
++      gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
++      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
++      gEfiMdePkgTokenSpaceGuid.PcdUefiLibMaxPrintBufferSize|8000
++  }
++!if $(INCLUDE_TFTP_COMMAND) == TRUE
++  ShellPkg/DynamicCommand/TftpDynamicCommand/TftpDynamicCommand.inf {
++    <PcdsFixedAtBuild>
++      gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE
++  }
++!endif #$(INCLUDE_TFTP_COMMAND)
++
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+new file mode 100644
+index 0000000000..9567ede0ad
+--- /dev/null
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -0,0 +1,351 @@
++#
++#  Copyright (c) 2011, 2012, ARM Limited. All rights reserved.
++#  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++#  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution.  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++
++[DEFINES]
++
++################################################################################
++#
++# FD Section
++# The [FD] Section is made up of the definition statements and a
++# description of what goes into  the Flash Device Image.  Each FD section
++# defines one flash "device" image.  A flash device image may be one of
++# the following: Removable media bootable image (like a boot floppy
++# image,) an Option ROM image (that would be "flashed" into an add-in
++# card,) a System "Flash"  image (that would be burned into a system's
++# flash) or an Update ("Capsule") image that will be used to update and
++# existing system flash.
++#
++################################################################################
++[FD.D06]
++
++BaseAddress   = 0x204100000|gArmTokenSpaceGuid.PcdFdBaseAddress  # The base address of the Firmware in NOR Flash.
++
++Size          = 0x00400000|gArmTokenSpaceGuid.PcdFdSize         # The size in bytes of the FLASH Device
++ErasePolarity = 1
++
++# This one is tricky, it must be: BlockSize * NumBlocks = Size
++BlockSize     = 0x00010000
++NumBlocks     = 0x40
++
++################################################################################
++#
++# Following are lists of FD Region layout which correspond to the locations of different
++# images within the flash device.
++#
++# Regions must be defined in ascending order and may not overlap.
++#
++# A Layout Region start with a eight digit hex offset (leading "0x" required) followed by
++# the pipe "|" character, followed by the size of the region, also in hex with the leading
++# "0x" characters. Like:
++# Offset|Size
++# PcdOffsetCName|PcdSizeCName
++# RegionType <FV, DATA, or FILE>
++#
++################################################################################
++
++0x00000000|0x00100000
++gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
++
++0x00100000|0x00280000
++gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
++FV = FVMAIN_COMPACT
++
++0x00380000|0x00020000
++gHisiTokenSpaceGuid.PcdTrustedFirmwareBL1Base
++FILE = Platform/Hisilicon/D06/bl1.bin
++0x003A0000|0x00020000
++FILE = Platform/Hisilicon/D06/fip.bin
++
++0x003C0000|0x0000e000
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize
++DATA = {
++  ## This is the EFI_FIRMWARE_VOLUME_HEADER
++  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++  # FileSystemGuid: gEfiSystemNvDataFvGuid         =
++  0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,
++  0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,
++  # FvLength: 0x20000
++  0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00,
++  #Signature "_FVH"       #Attributes
++  0x5f, 0x46, 0x56, 0x48, 0xff, 0xfe, 0x04, 0x00,
++  #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision
++  0x48, 0x00, 0x36, 0x09, 0x00, 0x00, 0x00, 0x02,
++  #Blockmap[0]: 2 Blocks * 0x10000 Bytes / Block
++  0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,
++  #Blockmap[1]: End
++  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
++  ## This is the VARIABLE_STORE_HEADER
++!if $(SECURE_BOOT_ENABLE) == TRUE
++  #Signature: gEfiAuthenticatedVariableGuid =
++  #  { 0xaaf32c78, 0x947b, 0x439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}
++  0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,
++  0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,
++!else
++  #Signature: gEfiVariableGuid =
++  #  { 0xddcf3616, 0x3275, 0x4164, { 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}
++  0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,
++  0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,
++!endif
++  #Size: 0xe000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) = 0xdFB8
++  0xB8, 0xdF, 0x00, 0x00,
++  #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32
++  0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
++}
++
++0x003CE000|0x00002000
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize
++#NV_FTW_WORKING
++DATA = {
++  # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature = gEdkiiWorkingBlockSignatureGuid          =
++  0x2B, 0x29, 0x58, 0x9E, 0x68, 0x7C, 0x7D, 0x49,
++  0xA0, 0xCE, 0x65, 0x0 , 0xFD, 0x9F, 0x1B, 0x95,
++  # Crc:UINT32            #WorkingBlockValid:1, WorkingBlockInvalid:1, Reserved
++  0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,
++  # WriteQueueSize: UINT64 #Size: 0x2000 - 0x20 (FTW_WORKING_HEADER) = 0x1FE0
++  0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
++}
++
++0x003D0000|0x00010000
++gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase64|gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize
++
++0x003E0000|0x00010000
++
++0x003F0000|0x00010000
++FILE = Platform/Hisilicon/D0x-CustomData.Fv
++
++################################################################################
++#
++# FV Section
++#
++# [FV] section is used to define what components or modules are placed within a flash
++# device file.  This section also defines order the components and modules are positioned
++# within the image.  The [FV] section consists of define statements, set statements and
++# module statements.
++#
++################################################################################
++
++[FV.FvMain]
++BlockSize          = 0x40
++NumBlocks          = 0         # This FV gets compressed so make it just big enough
++FvAlignment        = 16        # FV alignment and FV attributes setting.
++ERASE_POLARITY     = 1
++MEMORY_MAPPED      = TRUE
++STICKY_WRITE       = TRUE
++LOCK_CAP           = TRUE
++LOCK_STATUS        = TRUE
++WRITE_DISABLED_CAP = TRUE
++WRITE_ENABLED_CAP  = TRUE
++WRITE_STATUS       = TRUE
++WRITE_LOCK_CAP     = TRUE
++WRITE_LOCK_STATUS  = TRUE
++READ_DISABLED_CAP  = TRUE
++READ_ENABLED_CAP   = TRUE
++READ_STATUS        = TRUE
++READ_LOCK_CAP      = TRUE
++READ_LOCK_STATUS   = TRUE
++
++  APRIORI DXE {
++    INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
++  }
++
++  INF MdeModulePkg/Core/Dxe/DxeMain.inf
++  INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
++
++  #
++  # PI DXE Drivers producing Architectural Protocols (EFI Services)
++  #
++  INF ArmPkg/Drivers/CpuDxe/CpuDxe.inf
++  INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
++
++  INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
++
++
++  INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
++  INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
++  INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
++
++  INF MdeModulePkg/Universal/CapsuleRuntimeDxe/CapsuleRuntimeDxe.inf
++  INF MdeModulePkg/Universal/MonotonicCounterRuntimeDxe/MonotonicCounterRuntimeDxe.inf
++
++!if $(SECURE_BOOT_ENABLE) == TRUE
++  INF SecurityPkg/VariableAuthenticated/SecureBootConfigDxe/SecureBootConfigDxe.inf
++!endif
++
++  INF MdeModulePkg/Universal/ResetSystemRuntimeDxe/ResetSystemRuntimeDxe.inf
++  INF EmbeddedPkg/RealTimeClockRuntimeDxe/RealTimeClockRuntimeDxe.inf
++  INF EmbeddedPkg/MetronomeDxe/MetronomeDxe.inf
++
++  INF MdeModulePkg/Universal/HiiDatabaseDxe/HiiDatabaseDxe.inf
++
++  #
++  # Multiple Console IO support
++  #
++  INF MdeModulePkg/Universal/Console/ConPlatformDxe/ConPlatformDxe.inf
++  INF MdeModulePkg/Universal/Console/ConSplitterDxe/ConSplitterDxe.inf
++  INF MdeModulePkg/Universal/Console/GraphicsConsoleDxe/GraphicsConsoleDxe.inf
++  INF MdeModulePkg/Universal/Console/TerminalDxe/TerminalDxe.inf
++  INF MdeModulePkg/Universal/SerialDxe/SerialDxe.inf
++
++  INF ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
++  INF ArmPkg/Drivers/TimerDxe/TimerDxe.inf
++
++  INF MdeModulePkg/Universal/WatchdogTimerDxe/WatchdogTimer.inf
++
++  #
++  # FAT filesystem + GPT/MBR partitioning
++  #
++  INF MdeModulePkg/Universal/Disk/DiskIoDxe/DiskIoDxe.inf
++  INF MdeModulePkg/Universal/Disk/PartitionDxe/PartitionDxe.inf
++  INF FatPkg/EnhancedFatDxe/Fat.inf
++  INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
++  INF IntelFrameworkModulePkg/Universal/StatusCode/RuntimeDxe/StatusCodeRuntimeDxe.inf
++
++  #
++  # Usb Support
++  #
++
++
++  INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf
++
++  INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf
++  INF MdeModulePkg/Bus/Usb/UsbBusDxe/UsbBusDxe.inf
++  INF MdeModulePkg/Bus/Usb/UsbKbDxe/UsbKbDxe.inf
++  INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
++  INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
++
++  INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
++  INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
++  INF Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
++
++
++
++  INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
++
++  INF Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
++
++  #
++  #ACPI
++  #
++  INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
++  INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
++
++  INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
++
++  #
++  #Network
++  #
++
++  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
++  INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
++  INF MdeModulePkg/Universal/Network/Dhcp4Dxe/Dhcp4Dxe.inf
++  INF MdeModulePkg/Universal/Network/DpcDxe/DpcDxe.inf
++  INF MdeModulePkg/Universal/Network/Ip4Dxe/Ip4Dxe.inf
++  INF MdeModulePkg/Universal/Network/MnpDxe/MnpDxe.inf
++  INF MdeModulePkg/Universal/Network/Mtftp4Dxe/Mtftp4Dxe.inf
++  INF MdeModulePkg/Universal/Network/Udp4Dxe/Udp4Dxe.inf
++!if $(NETWORK_IP6_ENABLE) == TRUE
++  INF NetworkPkg/Ip6Dxe/Ip6Dxe.inf
++  INF NetworkPkg/TcpDxe/TcpDxe.inf
++  INF NetworkPkg/Udp6Dxe/Udp6Dxe.inf
++  INF NetworkPkg/Dhcp6Dxe/Dhcp6Dxe.inf
++  INF NetworkPkg/Mtftp6Dxe/Mtftp6Dxe.inf
++  INF NetworkPkg/UefiPxeBcDxe/UefiPxeBcDxe.inf
++!else
++  INF MdeModulePkg/Universal/Network/Tcp4Dxe/Tcp4Dxe.inf
++  INF MdeModulePkg/Universal/Network/UefiPxeBcDxe/UefiPxeBcDxe.inf
++!endif
++  INF MdeModulePkg/Universal/Network/IScsiDxe/IScsiDxe.inf
++!if $(HTTP_BOOT_ENABLE) == TRUE
++  INF NetworkPkg/DnsDxe/DnsDxe.inf
++  INF NetworkPkg/HttpUtilitiesDxe/HttpUtilitiesDxe.inf
++  INF NetworkPkg/HttpDxe/HttpDxe.inf
++  INF NetworkPkg/HttpBootDxe/HttpBootDxe.inf
++!endif
++
++
++  #
++  # PCI Support
++  #
++  INF Silicon/Hisilicon/Drivers/PciPlatform/PciPlatform.inf
++  INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
++  INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
++  INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
++
++  INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
++  INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
++  INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
++  INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
++
++  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
++  #
++  # Build Shell from latest source code instead of prebuilt binary
++  #
++  INF ShellPkg/Application/Shell/Shell.inf
++
++  INF MdeModulePkg/Application/UiApp/UiApp.inf
++  #
++  # Bds
++  #
++  INF MdeModulePkg/Universal/DevicePathDxe/DevicePathDxe.inf
++
++  INF MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
++  INF MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
++  INF MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
++  INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
++
++[FV.FVMAIN_COMPACT]
++FvAlignment        = 16
++ERASE_POLARITY     = 1
++MEMORY_MAPPED      = TRUE
++STICKY_WRITE       = TRUE
++LOCK_CAP           = TRUE
++LOCK_STATUS        = TRUE
++WRITE_DISABLED_CAP = TRUE
++WRITE_ENABLED_CAP  = TRUE
++WRITE_STATUS       = TRUE
++WRITE_LOCK_CAP     = TRUE
++WRITE_LOCK_STATUS  = TRUE
++READ_DISABLED_CAP  = TRUE
++READ_ENABLED_CAP   = TRUE
++READ_STATUS        = TRUE
++READ_LOCK_CAP      = TRUE
++READ_LOCK_STATUS   = TRUE
++
++  APRIORI PEI {
++    INF  MdeModulePkg/Universal/PCD/Pei/Pcd.inf
++  }
++  INF ArmPlatformPkg/PrePeiCore/PrePeiCoreMPCore.inf
++  INF MdeModulePkg/Core/Pei/PeiMain.inf
++  INF ArmPlatformPkg/PlatformPei/PlatformPeim.inf
++
++  INF MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
++  INF MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
++
++  INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
++
++  INF ArmPkg/Drivers/CpuPei/CpuPei.inf
++  INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
++  INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
++
++  INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
++
++  FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
++    SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
++      SECTION FV_IMAGE = FVMAIN
++    }
++  }
++
++!include Silicon/Hisilicon/Hisilicon.fdf.inc
++
+diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h b/Platform/Hisilicon/D06/Include/Library/CpldD06.h
+new file mode 100644
+index 0000000000..be3548c8d1
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Include/Library/CpldD06.h
+@@ -0,0 +1,37 @@
++/** @file
++
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#ifndef __CPLDD06_H__
++#define __CPLDD06_H__
++
++#define CPLD_BASE_ADDRESS                 0x80000000
++
++#define CPLD_BIOSINDICATE_FLAG            0x09
++#define CPLD_I2C_SWITCH_FLAG              0x17
++#define CPU_GET_I2C_CONTROL               BIT2
++#define BMC_I2C_STATUS                    BIT3
++
++#define CPLD_LOGIC_VERSION                (0x4)
++#define CPLD_LOGIC_COMPILE_YEAR          (0x1)
++#define CPLD_LOGIC_COMPILE_MONTH         (0x2)
++#define CPLD_LOGIC_COMPILE_DAY           (0x3)
++
++#define CPLD_RISER_PRSNT_FLAG             0x40
++#define CPLD_RISER2_BOARD_ID              0x44
++
++#define CPLD_X8_X8_X8_BOARD_ID            0x92
++#define CPLD_X16_X8_BOARD_ID              0x93
++
++#endif /* __CPLDD06_H__ */
+diff --git a/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h b/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h
+new file mode 100644
+index 0000000000..05f0f7020e
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Include/Library/SerdesLib.h
+@@ -0,0 +1,85 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#ifndef _SERDES_LIB_H_
++#define _SERDES_LIB_H_
++
++typedef enum {
++  EmHilink0Hccs1X8 = 0,
++  EmHilink0Pcie1X8 = 2,
++  EmHilink0Pcie1X4Pcie2X4 = 3,
++  EmHilink0Sas2X8 = 4,
++  EmHilink0Hccs1X8Width16,
++  EmHilink0Hccs1X8Width32,
++  EmHilink0Hccs1X8Speed5G,
++} HILINK0_MODE_TYPE;
++
++typedef enum {
++  EmHilink1Sas2X1 = 0,
++  EmHilink1Hccs0X8 = 1,
++  EmHilink1Pcie0X8 = 2,
++  EmHilink1Hccs0X8Width16,
++  EmHilink1Hccs0X8Width32,
++  EmHilink1Hccs0X8Speed5G,
++} HILINK1_MODE_TYPE;
++
++typedef enum {
++  EmHilink2Pcie2X8 = 0,
++  EmHilink2Hccs2X8 = 1,
++  EmHilink2Sas0X8 = 2,
++  EmHilink2Hccs2X8Width16,
++  EmHilink2Hccs2X8Width32,
++  EmHilink2Hccs2X8Speed5G,
++} HILINK2_MODE_TYPE;
++
++typedef enum {
++  EmHilink5Pcie3X4 = 0,
++  EmHilink5Pcie2X2Pcie3X2 = 1,
++  EmHilink5Sas1X4 = 2,
++} HILINK5_MODE_TYPE;
++
++
++typedef struct {
++  HILINK0_MODE_TYPE Hilink0Mode;
++  HILINK1_MODE_TYPE Hilink1Mode;
++  HILINK2_MODE_TYPE Hilink2Mode;
++  UINT32 Hilink3Mode;
++  UINT32 Hilink4Mode;
++  HILINK5_MODE_TYPE Hilink5Mode;
++  UINT32 Hilink6Mode;
++  UINT32 UseSsc;
++} SERDES_PARAM;
++
++#define SERDES_INVALID_MACRO_ID  0xFFFFFFFF
++#define SERDES_INVALID_LANE_NUM  0xFFFFFFFF
++#define SERDES_INVALID_RATE_MODE  0xFFFFFFFF
++
++typedef struct {
++  UINT32 MacroId;
++  UINT32 DsNum;
++  UINT32 DsCfg;
++} SERDES_POLARITY_INVERT;
++
++EFI_STATUS OemGetSerdesParam (SERDES_PARAM *ParamA, SERDES_PARAM *ParamB, UINT32 SocketId);
++extern SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[];
++extern SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[];
++UINT32 GetEthType (UINT8 EthChannel);
++VOID SerdesEnableCtleDfe (UINT32 NimbusId, UINT32 Macro, UINT32 Lane, UINT32 LaneMode);
++
++EFI_STATUS EfiSerdesInitWrap (UINT32 RateMode);
++INT32 SerdesReset (UINT32 SiclId, UINT32 Macro);
++VOID SerdesLoadFirmware (UINT32 SiclId, UINT32 Macro);
++INT32 h30_serdes_run_firmware (UINT32 nimbus_id, UINT32 macro, UINT8 DsMask, UINT8 ctle_mode);
++#endif
+diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
+new file mode 100644
+index 0000000000..9539cfdada
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
+@@ -0,0 +1,61 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++
++
++#ifndef _PLATFORM_ARCH_H_
++#define _PLATFORM_ARCH_H_
++
++#define MAX_SOCKET      2
++#define MAX_DIE         4
++#define MAX_DDRC        4
++#define MAX_NODE        (MAX_SOCKET * MAX_DIE)
++#define MAX_CHANNEL     8
++#define MAX_DIMM        2
++#define MAX_RANK_CH     8
++#define MAX_RANK_DIMM   4
++#define MAX_DIMM_SIZE   256  // In GB
++// Max NUMA node number for each node type
++#define MAX_NUM_PER_TYPE 8
++
++#define RASC_BASE                (0x1800)
++#define RASC_CFG_INFOIDX_REG     (RASC_BASE + 0x58)  /* configuration register for Rank statistical information */
++#define RASC_CFG_SPLVL_REG       (RASC_BASE + 0xD4)  /* configuration register for Sparing level */
++
++//
++// ACPI table information used to initialize tables.
++//
++#define EFI_ACPI_ARM_OEM_ID           'H','I','S','I',' ',' '   // OEMID 6 bytes long
++#define EFI_ACPI_ARM_OEM_TABLE_ID     SIGNATURE_64 ('H','I','P','0','8',' ',' ',' ') // OEM table id 8 bytes long
++#define EFI_ACPI_ARM_OEM_REVISION     0x00000000
++#define EFI_ACPI_ARM_CREATOR_ID       SIGNATURE_32 ('H','I','S','I')
++#define EFI_ACPI_ARM_CREATOR_REVISION 0x20151124
++
++// A macro to initialise the common header part of EFI ACPI tables as defined by
++// EFI_ACPI_DESCRIPTION_HEADER structure.
++#define ARM_ACPI_HEADER(Signature, Type, Revision) {            \
++  Signature,                      /* UINT32  Signature */       \
++  sizeof (Type),                  /* UINT32  Length */          \
++  Revision,                       /* UINT8   Revision */        \
++  0,                              /* UINT8   Checksum */        \
++  { EFI_ACPI_ARM_OEM_ID },        /* UINT8   OemId[6] */        \
++  EFI_ACPI_ARM_OEM_TABLE_ID,      /* UINT64  OemTableId */      \
++  EFI_ACPI_ARM_OEM_REVISION,      /* UINT32  OemRevision */     \
++  EFI_ACPI_ARM_CREATOR_ID,        /* UINT32  CreatorId */       \
++  EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
++  }
++
++#endif
++
+diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
+index 21498b7056..332a79343f 100644
+--- a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
++++ b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
+@@ -27,7 +27,13 @@ typedef struct _DDRC_BASE_ID{
+ UINTN OemGetPoeSubBase (UINT32 NodeId);
+ UINTN OemGetPeriSubBase (UINT32 NodeId);
+ UINTN OemGetAlgSubBase (UINT32 NodeId);
++UINTN OemGetCfgbusBase (UINT32 NodeId);
++UINTN OemGetGicSubBase (UINT32 NodeId);
++UINTN OemGetHACSubBase (UINT32 NodeId);
++UINTN OemGetIOMGMTSubBase (UINT32 NodeId);
++UINTN OemGetNetworkSubBase (UINT32 NodeId);
+ UINTN OemGetM3SubBase (UINT32 NodeId);
++UINTN OemGetPCIeSubBase (UINT32 NodeId);
+ 
+ VOID OemAddressMapInit(VOID);
+ 
+diff --git a/Silicon/Hisilicon/Include/Library/OemNicLib.h b/Silicon/Hisilicon/Include/Library/OemNicLib.h
+new file mode 100644
+index 0000000000..66fe9a2e9b
+--- /dev/null
++++ b/Silicon/Hisilicon/Include/Library/OemNicLib.h
+@@ -0,0 +1,57 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++
++#ifndef _OEM_NIC_LIB_H_
++#define _OEM_NIC_LIB_H_
++
++#define ETH_MAX_PORT          8
++#define ETH_DEBUG_PORT0       6
++#define ETH_DEBUG_PORT1       7
++
++#define ETH_SPEED_10M     6
++#define ETH_SPEED_100M    7
++#define ETH_SPEED_1000M   8
++#define ETH_SPEED_10KM    9
++#define ETH_HALF_DUPLEX   0
++#define ETH_FULL_DUPLEX   1
++
++#define ETH_GDD_ID                          0x001378e0
++#define ETH_PHY_BCM5241_ID                  0x0143bc30
++#define ETH_PHY_MVL88E1145_ID               0x01410cd0
++#define ETH_PHY_MVL88E1119_ID               0x01410e80
++#define ETH_PHY_MVL88E1512_ID               0x01410dd0
++#define ETH_PHY_MVL88E1543_ID               0x01410ea0
++#define ETH_PHY_NLP3142_ID                  0x00000412
++
++#define ETH_INVALID                         0xffffffff
++
++typedef struct {
++  UINT32 Valid;
++  UINT32 Speed;
++  UINT32 Duplex;
++  UINT32 PhyId;
++  UINT32 PhyAddr;
++} ETH_PRODUCT_DESC;
++
++BOOLEAN OemIsInitEth (UINT32 Port);
++UINT32 OemEthFindFirstSP ();
++ETH_PRODUCT_DESC *OemEthInit (UINT32 port);
++UINT32 GetCpu1FiberType (UINT8 *Fiber1Type, UINT8 *Fiber2Type);
++UINT32 GetCpu2FiberType (UINT8 *Fiber1Type, UINT8 *Fiber2Type, UINT8 *Fiber100Ge);
++EFI_STATUS EFIAPI OemGetMac (IN OUT EFI_MAC_ADDRESS *Mac, IN UINTN Port);
++EFI_STATUS EFIAPI OemSetMac (IN EFI_MAC_ADDRESS *Mac, IN UINTN Port);
++
++#endif
+-- 
+2.17.0
+
diff --git a/v2/v2-0011-Platform-Hisilicon-D06-Add-M41T83RealTimeClockLib.patch b/v2/v2-0011-Platform-Hisilicon-D06-Add-M41T83RealTimeClockLib.patch
new file mode 100644
index 0000000000..15bb4f327c
--- /dev/null
+++ b/v2/v2-0011-Platform-Hisilicon-D06-Add-M41T83RealTimeClockLib.patch
@@ -0,0 +1,818 @@
+From 6335047a06601ba279e8a761a42794cd70461f4a Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Wed, 13 Jun 2018 20:20:29 +0800
+Subject: [PATCH edk2-platforms v2 11/43] Platform/Hisilicon/D06: Add
+ M41T83RealTimeClockLib
+
+Add M41T83RealTimeClockLib for RTC.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                              |   1 +
+ Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf |  46 ++
+ Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h      | 158 ++++++
+ Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c   | 564 ++++++++++++++++++++
+ 4 files changed, 769 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index d14fce1159..27358f8c78 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -65,6 +65,7 @@
+   CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
+ 
+   TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
++  RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
+ 
+   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+   GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+diff --git a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
+new file mode 100644
+index 0000000000..e0bf6b3f24
+--- /dev/null
++++ b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
+@@ -0,0 +1,46 @@
++#/** @file
++#
++#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++#  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution.  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = M41T83RealTimeClockLib
++  FILE_GUID                      = 470DFB96-E205-4515-A75E-2E60F853E79D
++  MODULE_TYPE                    = BASE
++  VERSION_STRING                 = 1.0
++  LIBRARY_CLASS                  = RealTimeClockLib
++
++[Sources.common]
++  M41T83RealTimeClockLib.c
++
++[Packages]
++  EmbeddedPkg/EmbeddedPkg.dec
++  MdePkg/MdePkg.dec
++  Platform/Hisilicon/D06/D06.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  BaseMemoryLib
++  CpldIoLib
++  DebugLib
++  I2CLib
++  IoLib
++  PcdLib
++  TimeBaseLib
++  TimerLib
++  UefiLib
++  UefiRuntimeLib        # Use EFiAtRuntime to check stage
++
++[Depex]
++  gEfiCpuArchProtocolGuid
+diff --git a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h
+new file mode 100644
+index 0000000000..ed10099bf3
+--- /dev/null
++++ b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClock.h
+@@ -0,0 +1,158 @@
++/** @file
++
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#ifndef __M41T83_REAL_TIME_CLOCK_H__
++#define __M41T83_REAL_TIME_CLOCK_H__
++
++// The delay is need for cpld and I2C. This is a empirical value. MemoryFance is no need.
++#define RTC_DELAY_30_MS            30000
++// The delay is need for cpld and I2C. This is a empirical value. MemoryFance is no need.
++#define RTC_DELAY_1000_MACROSECOND 1000
++// The delay is need for cpld and I2C. This is a empirical value. MemoryFance is no need.
++#define RTC_DELAY_2_MACROSECOND    2
++
++#define M41T83_REGADDR_DOTSECONDS       0x00
++#define M41T83_REGADDR_SECONDS          0x01
++#define M41T83_REGADDR_MINUTES          0x02
++#define M41T83_REGADDR_HOURS            0x03
++#define M41T83_REGADDR_WEEK_DAY         0x04
++#define M41T83_REGADDR_DAY              0x05
++#define M41T83_REGADDR_MONTH            0x06
++#define M41T83_REGADDR_YEAR             0x07
++#define M41T83_REGADDR_ALARM1SEC        0x0E
++#define M41T83_REGADDR_ALARM1MIN        0x0D
++#define M41T83_REGADDR_ALARM1HOUR       0x0C
++#define M41T83_REGADDR_ALARM1DATE       0x0B
++#define M41T83_REGADDR_ALARM1MONTH      0x0A
++
++#define M41T83_REGADDR_TIMERCONTROL     0x11
++
++#define M41T83_REGADDR_ALARM2SEC        0x18
++#define M41T83_REGADDR_ALARM2MIN        0x17
++#define M41T83_REGADDR_ALARM2HOUR       0x16
++#define M41T83_REGADDR_ALARM2DATE       0x15
++#define M41T83_REGADDR_ALARM2MONTH      0x14
++
++typedef union {
++  struct {
++    UINT8 TD0:1;
++    UINT8 TD1:1;
++    UINT8 RSV:3;
++    UINT8 TIE:1;
++    UINT8 TITP:1;
++    UINT8 TE:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_TIMERCONTROL;
++
++typedef union {
++  struct {
++    UINT8 MicroSeconds;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_DOTSECOND;
++
++typedef union {
++  struct{
++    UINT8 Seconds:7;
++    UINT8 ST:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_SECOND;
++
++typedef union {
++  struct {
++    UINT8 Minutes:7;
++    UINT8 Rsv:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_MINUTE;
++
++typedef union {
++  struct {
++    UINT8 Hours:6;
++    UINT8 CB:2;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_HOUR;
++
++typedef union {
++  struct{
++    UINT8 Days:3;
++    UINT8 Rsv:5;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_WEEK_DAY;
++
++typedef union {
++  struct{
++    UINT8 Days:6;
++    UINT8 Rsv:2;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_MONTH_DAY;
++
++typedef union {
++  struct {
++    UINT8 Months:5;
++    UINT8 Rsv:3;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_MONTH;
++
++typedef union {
++  struct {
++    UINT8 Years:8;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_YEAR;
++
++typedef union {
++  struct {
++    UINT8 Second:7;
++    UINT8 RPT11:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_ALARM1SEC;
++
++typedef union {
++  struct {
++    UINT8 Minute:7;
++    UINT8 RPT12:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_ALARM1MIN;
++
++typedef union {
++  struct {
++    UINT8 Hour:6;
++    UINT8 HT:1;
++    UINT8 RPT13:1;
++  } Bits;
++  UINT8 Uint8;
++} RTC_M41T83_ALARM1HOUR;
++
++typedef struct {
++  RTC_M41T83_DOTSECOND  DotSecond;
++  RTC_M41T83_SECOND     Second;
++  RTC_M41T83_MINUTE     Minute;
++  RTC_M41T83_HOUR       Hour;
++  RTC_M41T83_WEEK_DAY   WeekDay;
++  RTC_M41T83_MONTH_DAY  Day;
++  RTC_M41T83_MONTH      Month;
++  RTC_M41T83_YEAR       Year;
++} RTC_M41T83_TIME;
++
++#endif
+diff --git a/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c
+new file mode 100644
+index 0000000000..eabe8dc0f3
+--- /dev/null
++++ b/Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.c
+@@ -0,0 +1,564 @@
++/** @file
++
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#include <Uefi.h>
++#include <PiDxe.h>
++#include <Library/BaseLib.h>
++#include <Library/BaseMemoryLib.h>
++#include <Library/CpldD06.h>
++#include <Library/CpldIoLib.h>
++#include <Library/DebugLib.h>
++#include <Library/I2CLib.h>
++#include <Library/IoLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include <Library/PcdLib.h>
++#include <Library/TimeBaseLib.h>
++#include <Library/TimerLib.h>
++#include <Library/UefiLib.h>
++#include <Library/UefiBootServicesTableLib.h>
++#include <Library/UefiRuntimeLib.h>
++#include <Library/UefiRuntimeServicesTableLib.h>
++#include <Protocol/RealTimeClock.h>
++#include "M41T83RealTimeClock.h"
++
++extern I2C_DEVICE gRtcDevice;
++
++STATIC EFI_LOCK  mRtcLock;
++
++EFI_STATUS
++SwitchRtcI2cChannelAndLock (
++  VOID
++  )
++{
++  UINT8   Temp;
++  UINT8   Count;
++
++  for (Count = 0; Count < 100; Count++) {
++    // To get the other side's state is idle first
++    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++    if ((Temp & BIT3) != 0) {
++      (VOID) MicroSecondDelay (RTC_DELAY_30_MS);
++      // Try 100 times, if BMC has not released the bus, return preemption failed
++      if (Count == 99) {
++        if (!EfiAtRuntime ()) {
++          DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Clear cpu_i2c_rtc_state 100 times fail!\n",
++            __FUNCTION__, __LINE__));
++        }
++        return EFI_DEVICE_ERROR;
++      }
++      continue;
++    }
++
++    // if BMC free the bus, can be set 1 preemption
++    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++    Temp = Temp | CPU_GET_I2C_CONTROL;
++    // CPU occupied RTC I2C State
++    WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
++    (VOID) MicroSecondDelay (RTC_DELAY_2_MACROSECOND);
++    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++    // Is preempt success
++    if(CPU_GET_I2C_CONTROL == (Temp & CPU_GET_I2C_CONTROL)) {
++      break;
++    }
++    if (Count == 99) {
++      if (!EfiAtRuntime ()) {
++        DEBUG((DEBUG_ERROR, "[%a]:[%dL]  Clear cpu_i2c_rtc_state fail !!! \n",
++          __FUNCTION__, __LINE__));
++      }
++      return EFI_DEVICE_ERROR;
++    }
++    (VOID) MicroSecondDelay (RTC_DELAY_30_MS);
++  }
++
++  //Polling BMC RTC I2C status
++  for (Count = 0; Count < 100; Count++) {
++    Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++    if ((Temp & BIT3) == 0) {
++      return EFI_SUCCESS;
++    }
++    (VOID) MicroSecondDelay (RTC_DELAY_30_MS);
++  }
++
++  //If the BMC occupies the RTC I2C Channel, write back the CPU side is idle
++  // or the subsequent BMC will not preempt
++  Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++  Temp = Temp & (~CPU_GET_I2C_CONTROL);
++  WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
++
++  return EFI_NOT_READY;
++}
++
++
++/**
++  Read RTC content through its registers.
++
++  @param  Address   Address offset of RTC data.
++  @param  Size      Size of RTC data to read.
++  @param  Data      The data of UINT8 type read from RTC.
++
++  @return EFI_STATUS
++**/
++EFI_STATUS
++RtcRead (
++  IN  UINT8   Address,
++  IN  UINT8   Size,
++  OUT UINT8   *Data
++  )
++{
++  EFI_STATUS  Status;
++
++  Status = I2CRead (&gRtcDevice, Address, Size, Data);
++  MicroSecondDelay (RTC_DELAY_1000_MACROSECOND);
++  return Status;
++}
++
++/**
++  Write RTC through its registers.
++
++  @param  Address   Address offset of RTC data.
++  @param  Size      Size of RTC data to write.
++  @param  Data      The data of UINT8 type write from RTC.
++
++  @return EFI_STATUS
++**/
++EFI_STATUS
++RtcWrite (
++  IN  UINT8   Address,
++  IN  UINT8   Size,
++  UINT8       *Data
++  )
++{
++  EFI_STATUS  Status;
++
++  Status = I2CWrite (&gRtcDevice, Address, Size, Data);
++  MicroSecondDelay (RTC_DELAY_1000_MACROSECOND);
++  return Status;
++}
++
++VOID
++ReleaseOwnershipOfRtc (
++  VOID
++  )
++{
++  UINT8   Temp;
++
++  Temp = ReadCpldReg (CPLD_I2C_SWITCH_FLAG);
++  Temp = Temp & ~CPU_GET_I2C_CONTROL;
++  WriteCpldReg (CPLD_I2C_SWITCH_FLAG, Temp);
++}
++
++
++EFI_STATUS
++InitializeM41T83 (
++  VOID
++  )
++{
++  EFI_STATUS                Status;
++  RTC_M41T83_ALARM1HOUR     Alarm1Hour;
++  RTC_M41T83_SECOND         Second;
++
++  // Acquire RTC Lock to make access to RTC atomic
++  if (!EfiAtRuntime ()) {
++    EfiAcquireLock (&mRtcLock);
++  }
++
++  Status = I2CInit (gRtcDevice.Socket, gRtcDevice.Port, Normal);
++  MicroSecondDelay (RTC_DELAY_1000_MACROSECOND);
++  if (EFI_ERROR (Status)) {
++    if (!EfiAtRuntime ()) {
++      EfiReleaseLock (&mRtcLock);
++    }
++    return Status;
++  }
++
++  Status = SwitchRtcI2cChannelAndLock ();
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "Get i2c preemption failed: %r\n", Status));
++    if (!EfiAtRuntime ()) {
++      EfiReleaseLock (&mRtcLock);
++    }
++    return Status;
++  }
++
++  MicroSecondDelay(RTC_DELAY_1000_MACROSECOND);
++
++  // Set ST at Power up to clear Oscillator fail detection(OF)
++  Status = RtcRead (M41T83_REGADDR_SECONDS, 1, &Second.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++  }
++  Second.Bits.ST= 1;
++  Status = RtcWrite (M41T83_REGADDR_SECONDS, 1, &Second.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++    goto Exit;
++  }
++  Status = RtcRead (M41T83_REGADDR_SECONDS, 1, &Second.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++  }
++  Second.Bits.ST= 0;
++  Status = RtcWrite (M41T83_REGADDR_SECONDS, 1, &Second.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++    goto Exit;
++  }
++
++  // Clear HT bit to enanle write to the RTC registers (addresses 0-7)
++  Status = RtcRead (M41T83_REGADDR_ALARM1HOUR, 1, &Alarm1Hour.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++  }
++  Alarm1Hour.Bits.HT = 0;
++  Status = RtcWrite (M41T83_REGADDR_ALARM1HOUR, 1, &Alarm1Hour.Uint8);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++      __FUNCTION__, __LINE__, Status));
++    goto Exit;
++  }
++
++Exit:
++  // Release RTC Lock.
++  ReleaseOwnershipOfRtc ();
++  if (!EfiAtRuntime ()) {
++    EfiReleaseLock (&mRtcLock);
++  }
++  return Status;
++}
++
++/**
++  Sets the current local time and date information.
++
++  @param  Time                  A pointer to the current time.
++
++  @retval EFI_SUCCESS           The operation completed successfully.
++  @retval EFI_INVALID_PARAMETER A time field is out of range.
++  @retval EFI_DEVICE_ERROR      The time could not be set due due to hardware error.
++
++**/
++EFI_STATUS
++EFIAPI
++LibSetTime (
++  IN  EFI_TIME                *Time
++  )
++{
++  EFI_STATUS                  Status = EFI_SUCCESS;
++  RTC_M41T83_TIME             BcdTime;
++  UINT16                      CenturyBase = 2000;
++  UINTN                       LineNum = 0;
++
++  if (NULL == Time) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  if (!IsTimeValid (Time)) {
++    if (!EfiAtRuntime ()) {
++      DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++        __FUNCTION__, __LINE__, Status));
++      DEBUG ((DEBUG_ERROR, "Now RTC Time is : %04d-%02d-%02d %02d:%02d:%02d\n",
++        Time->Year, Time->Month, Time->Day, Time->Hour, Time->Minute, Time->Second
++      ));
++    }
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Status = SwitchRtcI2cChannelAndLock ();
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  (VOID)MicroSecondDelay (RTC_DELAY_1000_MACROSECOND);
++
++  SetMem (&BcdTime, sizeof (RTC_M41T83_TIME), 0);
++
++  // Acquire RTC Lock to make access to RTC atomic
++  if (!EfiAtRuntime ()) {
++    EfiAcquireLock (&mRtcLock);
++  }
++
++  BcdTime.Second.Bits.Seconds = DecimalToBcd8 (Time->Second);
++  BcdTime.Minute.Bits.Minutes = DecimalToBcd8 (Time->Minute);
++  BcdTime.Hour.Bits.Hours = DecimalToBcd8 (Time->Hour);
++  BcdTime.Day.Bits.Days = DecimalToBcd8 (Time->Day);
++  BcdTime.Month.Bits.Months = DecimalToBcd8 (Time->Month);
++  BcdTime.Year.Bits.Years = DecimalToBcd8 (Time->Year % 100);
++  BcdTime.Hour.Bits.CB = (Time->Year - CenturyBase) / 100 % 10;
++
++  Status = RtcWrite (M41T83_REGADDR_DOTSECONDS, 1, &BcdTime.DotSecond.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_SECONDS, 1, &BcdTime.Second.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_MINUTES, 1, &BcdTime.Minute.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_HOURS, 1, &BcdTime.Hour.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_DAY, 1, &BcdTime.Day.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_MONTH, 1, &BcdTime.Month.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++  Status = RtcWrite (M41T83_REGADDR_YEAR, 1, &BcdTime.Year.Uint8);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++
++Exit:
++  ReleaseOwnershipOfRtc ();
++  // Release RTC Lock.
++  if (!EfiAtRuntime ()) {
++    if (EFI_ERROR (Status)) {
++      DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++        __FUNCTION__, LineNum, Status));
++    }
++    EfiReleaseLock (&mRtcLock);
++  }
++  return Status;
++}
++
++
++/**
++  Returns the current time and date information, and the time-keeping capabilities
++  of the hardware platform.
++
++  @param  Time                   A pointer to storage to receive a snapshot of the current time.
++  @param  Capabilities           An optional pointer to a buffer to receive the real time clock
++                                 device's capabilities.
++
++  @retval EFI_SUCCESS            The operation completed successfully.
++  @retval EFI_INVALID_PARAMETER  Time is NULL.
++  @retval EFI_DEVICE_ERROR       The time could not be retrieved due to hardware error.
++  @retval EFI_SECURITY_VIOLATION The time could not be retrieved due to an authentication failure.
++**/
++EFI_STATUS
++EFIAPI
++LibGetTime (
++  OUT EFI_TIME                *Time,
++  OUT EFI_TIME_CAPABILITIES   *Capabilities
++  )
++{
++  EFI_STATUS                  Status = EFI_SUCCESS;
++  RTC_M41T83_TIME             BcdTime;
++  UINT16                      CenturyBase = 2000;
++  UINTN                       LineNum = 0;
++  BOOLEAN                     IsTimeInvalid = FALSE;
++  UINT8                       TimeTemp[7] = {0};
++
++  // Ensure Time is a valid pointer
++  if (Time == NULL) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Status = SwitchRtcI2cChannelAndLock ();
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++
++  MicroSecondDelay(RTC_DELAY_1000_MACROSECOND);
++
++  SetMem (&BcdTime, sizeof (RTC_M41T83_TIME), 0);
++  SetMem (Time , sizeof (EFI_TIME), 0);
++
++  // Acquire RTC Lock to make access to RTC atomic
++  if (!EfiAtRuntime ()) {
++    EfiAcquireLock (&mRtcLock);
++  }
++
++  Status = RtcRead (M41T83_REGADDR_SECONDS, 7, TimeTemp);
++  if (EFI_ERROR (Status)) {
++    LineNum = __LINE__;
++    goto Exit;
++  }
++
++  BcdTime.Second.Uint8 = TimeTemp[0];  //SECONDS
++  BcdTime.Minute.Uint8 = TimeTemp[1];  //MINUTES
++  BcdTime.Hour.Uint8 = TimeTemp[2];    //HOURS
++  BcdTime.Day.Uint8 = TimeTemp[4];     //DAY
++  BcdTime.Month.Uint8 = TimeTemp[5];   //MONTH
++  BcdTime.Year.Uint8 = TimeTemp[6];    //Year
++
++  Time->Year = BcdToDecimal8 (BcdTime.Year.Bits.Years);
++  Time->Year += CenturyBase + BcdTime.Hour.Bits.CB * 100;
++  Time->Month = BcdToDecimal8 (BcdTime.Month.Bits.Months);
++  Time->Day = BcdToDecimal8 (BcdTime.Day.Bits.Days);
++  Time->Hour = BcdToDecimal8 (BcdTime.Hour.Bits.Hours);
++  Time->Minute = BcdToDecimal8 (BcdTime.Minute.Bits.Minutes);
++  Time->Second = BcdToDecimal8 (BcdTime.Second.Bits.Seconds);
++  Time->TimeZone = EFI_UNSPECIFIED_TIMEZONE;
++
++  if (!IsTimeValid (Time)) {
++      Status = EFI_DEVICE_ERROR;
++      LineNum = __LINE__;
++      IsTimeInvalid = TRUE;
++      goto Exit;
++  }
++
++Exit:
++  ReleaseOwnershipOfRtc ();
++  // Release RTC Lock.
++  if (!EfiAtRuntime ()) {
++    if (EFI_ERROR (Status)) {
++      if (IsTimeInvalid == TRUE) {
++        DEBUG((DEBUG_ERROR, "%a(%d) Time invalid.\r\n",__FUNCTION__, LineNum));
++      } else {
++        DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\n",
++          __FUNCTION__, LineNum, Status));
++      }
++    }
++    EfiReleaseLock (&mRtcLock);
++  }
++  return Status;
++}
++
++
++/**
++  Returns the current wakeup alarm clock setting.
++
++  @param  Enabled               Indicates if the alarm is currently enabled or disabled.
++  @param  Pending               Indicates if the alarm signal is pending and requires acknowledgement.
++  @param  Time                  The current alarm setting.
++
++  @retval EFI_SUCCESS           The alarm settings were returned.
++  @retval EFI_INVALID_PARAMETER Any parameter is NULL.
++  @retval EFI_DEVICE_ERROR      The wakeup time could not be retrieved due to a hardware error.
++
++**/
++EFI_STATUS
++EFIAPI
++LibGetWakeupTime (
++  OUT BOOLEAN     *Enabled,
++  OUT BOOLEAN     *Pending,
++  OUT EFI_TIME    *Time
++  )
++{
++  // Not a required feature
++  return EFI_UNSUPPORTED;
++}
++
++
++/**
++  Sets the system wakeup alarm clock time.
++
++  @param  Enabled               Enable or disable the wakeup alarm.
++  @param  Time                  If Enable is TRUE, the time to set the wakeup alarm for.
++
++  @retval EFI_SUCCESS           If Enable is TRUE, then the wakeup alarm was enabled. If
++                                Enable is FALSE, then the wakeup alarm was disabled.
++  @retval EFI_INVALID_PARAMETER A time field is out of range.
++  @retval EFI_DEVICE_ERROR      The wakeup time could not be set due to a hardware error.
++  @retval EFI_UNSUPPORTED       A wakeup timer is not supported on this platform.
++
++**/
++EFI_STATUS
++EFIAPI
++LibSetWakeupTime (
++  IN  BOOLEAN      Enabled,
++  OUT EFI_TIME     *Time
++  )
++{
++  // Not a required feature
++  return EFI_UNSUPPORTED;
++}
++
++
++/**
++  This is the declaration of an EFI image entry point. This can be the entry point to an application
++  written to this specification, an EFI boot service driver, or an EFI runtime driver.
++
++  @param  ImageHandle           Handle that identifies the loaded image.
++  @param  SystemTable           System Table for this image.
++
++  @retval EFI_SUCCESS           The operation completed successfully.
++
++**/
++EFI_STATUS
++EFIAPI
++LibRtcInitialize (
++  IN EFI_HANDLE                            ImageHandle,
++  IN EFI_SYSTEM_TABLE                      *SystemTable
++  )
++{
++  EFI_STATUS    Status = EFI_SUCCESS;
++  EFI_TIME      EfiTime;
++
++  EfiInitializeLock (&mRtcLock, TPL_CALLBACK);
++
++  // Setup the setters and getters
++  gRT->GetTime       = LibGetTime;
++  gRT->SetTime       = LibSetTime;
++  gRT->GetWakeupTime = LibGetWakeupTime;
++  gRT->SetWakeupTime = LibSetWakeupTime;
++
++  Status = InitializeM41T83 ();
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Status : %r\nRTC M41T83 Init Failed !!!\n",
++            __FUNCTION__, __LINE__, Status));
++    /*
++     * Returning ERROR on failure of RTC initilization will cause the system to hang up.
++     * So we add some debug message to indecate the RTC initilization failed,
++     * and continue without returning with error to avoid system hanging up.
++     *
++     *return Status;
++     */
++  }
++
++  LibGetTime (&EfiTime, NULL);
++  if (!IsTimeValid (&EfiTime)) {
++    EfiTime.Year    = 2015;
++    EfiTime.Month   = 1;
++    EfiTime.Day     = 1;
++    EfiTime.Hour    = 0;
++    EfiTime.Minute  = 0;
++    EfiTime.Second  = 0;
++    Status = LibSetTime (&EfiTime);
++    if (EFI_ERROR (Status)) {
++      DEBUG ((DEBUG_ERROR, "[%a]:[%dL] RTC settime Status : %r\n",
++        __FUNCTION__, __LINE__, Status));
++    }
++  }
++
++  DEBUG ((
++    DEBUG_ERROR, "Now RTC Time is : %04d-%02d-%02d %02d:%02d:%02d\n",
++    EfiTime.Year, EfiTime.Month, EfiTime.Day, EfiTime.Hour, EfiTime.Minute,
++    EfiTime.Second
++    ));
++    /*
++     * Returning ERROR on failure of RTC initilization will cause the system to hang up.
++     * So we add some debug message to indecate the RTC initilization failed,
++     * and return success to avoid system hanging up.
++     */
++  return EFI_SUCCESS;
++}
+-- 
+2.17.0
+
diff --git a/v2/v2-0012-Platform-Hisilicon-D06-Add-edk2-non-osi-component.patch b/v2/v2-0012-Platform-Hisilicon-D06-Add-edk2-non-osi-component.patch
new file mode 100644
index 0000000000..984b1b6640
--- /dev/null
+++ b/v2/v2-0012-Platform-Hisilicon-D06-Add-edk2-non-osi-component.patch
@@ -0,0 +1,149 @@
+From 74db81672b83c782223a1e68963e4dbb090f592d Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sat, 21 Jul 2018 14:31:06 +0800
+Subject: [PATCH edk2-platforms v2 12/43] Platform/Hisilicon/D06: Add
+ edk2-non-osi components for D06
+
+Add PcdCoreCount to fix build issue while add binary components.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                                 |  7 +++++++
+ Platform/Hisilicon/D06/D06.fdf                                                 | 17 +++++++++++++++++
+ Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf |  2 ++
+ 3 files changed, 26 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 27358f8c78..94454569f6 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -41,6 +41,8 @@
+ 
+   I2CLib|Silicon/Hisilicon/Library/I2CLib/I2CLib.inf
+   TimerLib|ArmPkg/Library/ArmArchTimerLib/ArmArchTimerLib.inf
++  IpmiCmdLib|Silicon/Hisilicon/Library/IpmiCmdLib/IpmiCmdLib.inf
++
+   NetLib|MdeModulePkg/Library/DxeNetLib/DxeNetLib.inf
+   DpcLib|MdeModulePkg/Library/DxeDpcLib/DxeDpcLib.inf
+   HiiLib|MdeModulePkg/Library/UefiHiiLib/UefiHiiLib.inf
+@@ -64,8 +66,12 @@
+ 
+   CpldIoLib|Silicon/Hisilicon/Library/CpldIoLib/CpldIoLib.inf
+ 
++  SerdesLib|Silicon/Hisilicon/Hi1620/Library/Hi1620Serdes/Hi1620SerdesLib.inf
++
+   TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+   RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
++  OemAddressMapLib|Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.inf
++  PlatformSysCtrlLib|Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.inf
+ 
+   CapsuleLib|MdeModulePkg/Library/DxeCapsuleLibNull/DxeCapsuleLibNull.inf
+   GenericBdsLib|IntelFrameworkModulePkg/Library/GenericBdsLib/GenericBdsLib.inf
+@@ -81,6 +87,7 @@
+   # USB Requirements
+   UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf
+ 
++  LpcLib|Silicon/Hisilicon/Hi1620/Library/LpcLibHi1620/LpcLib.inf
+   SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
+ !if $(SECURE_BOOT_ENABLE) == TRUE
+   FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index 9567ede0ad..07fe096f61 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -56,6 +56,7 @@ NumBlocks     = 0x40
+ 
+ 0x00000000|0x00100000
+ gArmTokenSpaceGuid.PcdSecureFvBaseAddress|gArmTokenSpaceGuid.PcdSecureFvSize
++FILE = Platform/Hisilicon/D06/Sec/FVMAIN_SEC.Fv
+ 
+ 0x00100000|0x00280000
+ gArmTokenSpaceGuid.PcdFvBaseAddress|gArmTokenSpaceGuid.PcdFvSize
+@@ -163,6 +164,7 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Core/Dxe/DxeMain.inf
+   INF MdeModulePkg/Universal/PCD/Dxe/Pcd.inf
+ 
++  INF Platform/Hisilicon/D06/Drivers/IoInitDxe/IoInitDxe.inf
+   #
+   # PI DXE Drivers producing Architectural Protocols (EFI Services)
+   #
+@@ -170,6 +172,7 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+ 
+   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
++  INF Platform/Hisilicon/D06/Drivers/SFC/SfcDxeDriver.inf
+ 
+ 
+   INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+@@ -225,10 +228,15 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Bus/Usb/UsbMouseDxe/UsbMouseDxe.inf
+   INF MdeModulePkg/Bus/Usb/UsbMassStorageDxe/UsbMassStorageDxe.inf
+ 
++  INF Platform/Hisilicon/D06/Drivers/Ipmi/IpmiInterfaceDxe/IpmiInterfaceDxe.inf
++  INF Platform/Hisilicon/D06/Drivers/GetInfoFromBmc/GetInfoFromBmc.inf
+   INF MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf
+   INF Silicon/Hisilicon/Drivers/Smbios/SmbiosMiscDxe/SmbiosMiscDxe.inf
+   INF Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.inf
++  INF Platform/Hisilicon/D06/Drivers/TransferSmbiosInfo/TransSmbiosInfo.inf
++  INF Platform/Hisilicon/D06/Drivers/IpmiMiscOpDxe/IpmiMiscOpDxe.inf
+ 
++  INF Platform/Hisilicon/D06/Drivers/IpmiWatchdogDxe/IpmiWatchdogDxe.inf
+ 
+ 
+   INF Silicon/Hisilicon/Drivers/Smbios/MemorySubClassDxe/MemorySubClassDxe.inf
+@@ -246,6 +254,7 @@ READ_LOCK_STATUS   = TRUE
+   #
+   #Network
+   #
++  INF Platform/Hisilicon/D06/Drivers/Net/SnpHi1620NewDxe/SnpDxe.inf
+ 
+   INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+   INF MdeModulePkg/Universal/Network/ArpDxe/ArpDxe.inf
+@@ -282,8 +291,14 @@ READ_LOCK_STATUS   = TRUE
+   INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+   INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+   INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
++  INF Platform/Hisilicon/D06/Drivers/PcieRasInitDxe/PcieRasInitDxe.inf
++  INF Platform/Hisilicon/D06/Drivers/RasInitDxe/RasInitDxe.inf
+ 
++  # VGA Driver
++  #
++  INF Platform/Hisilicon/D06/Drivers/Sm750Dxe/UefiSmi.inf
+   INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf
++  INF Platform/Hisilicon/D06/Drivers/Sas/SasDxeDriver.inf
+   INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+   INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+   INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+@@ -335,6 +350,8 @@ READ_LOCK_STATUS   = TRUE
+ 
+   INF Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+ 
++  INF Platform/Hisilicon/D06/Drivers/Ipmi/IpmiInterfacePei/IpmiInterfacePei.inf
++  INF Platform/Hisilicon/D06/MemoryInitPei/MemoryInitPeim.inf
+   INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+   INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+   INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
+diff --git a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+index 2275586ff3..a47806f391 100644
+--- a/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
++++ b/Silicon/Hisilicon/Drivers/Smbios/ProcessorSubClassDxe/ProcessorSubClassDxe.inf
+@@ -28,6 +28,7 @@
+ 
+ [Packages]
+   ArmPkg/ArmPkg.dec
++  ArmPlatformPkg/ArmPlatformPkg.dec
+   MdePkg/MdePkg.dec
+   MdeModulePkg/MdeModulePkg.dec
+   IntelFrameworkPkg/IntelFrameworkPkg.dec
+@@ -52,6 +53,7 @@
+   gEfiSmbiosProtocolGuid                       # PROTOCOL ALWAYS_CONSUMED
+ 
+ [Pcd]
++  gArmPlatformTokenSpaceGuid.PcdCoreCount
+   gHisiTokenSpaceGuid.PcdCPUInfo
+   gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
+ 
+-- 
+2.17.0
+
diff --git a/v2/v2-0013-Hisilicon-D06-Add-OemMiscLibD06.patch b/v2/v2-0013-Hisilicon-D06-Add-OemMiscLibD06.patch
new file mode 100644
index 0000000000..491a305e54
--- /dev/null
+++ b/v2/v2-0013-Hisilicon-D06-Add-OemMiscLibD06.patch
@@ -0,0 +1,751 @@
+From ad190a05d535c5d242a404418b14496cc323fc47 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Fri, 15 Jun 2018 17:47:45 +0800
+Subject: [PATCH edk2-platforms v2 13/43] Hisilicon/D06: Add OemMiscLibD06
+
+This library include BoardFeatureD06.c and OemMiscLibD06.c c file,
+use for several modules like PciHostBridgeLib and Smbios.
+Enlarge macro PCIEDEVICE_REPORT_MAX for D06.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                          |   1 +
+ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf          |  47 +++
+ Silicon/Hisilicon/Include/Library/OemMiscLib.h                          |   6 +-
+ Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c          | 432 ++++++++++++++++++++
+ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c            | 132 ++++++
+ Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni |  64 +++
+ 6 files changed, 681 insertions(+), 1 deletion(-)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 94454569f6..9ca7160dad 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -70,6 +70,7 @@
+ 
+   TimeBaseLib|EmbeddedPkg/Library/TimeBaseLib/TimeBaseLib.inf
+   RealTimeClockLib|Silicon/Hisilicon/Library/M41T83RealTimeClockLib/M41T83RealTimeClockLib.inf
++  OemMiscLib|Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+   OemAddressMapLib|Platform/Hisilicon/D06/Library/OemAddressMapD06/OemAddressMapD06.inf
+   PlatformSysCtrlLib|Silicon/Hisilicon/Hi1620/Library/PlatformSysCtrlLibHi1620/PlatformSysCtrlLibHi1620.inf
+ 
+diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+new file mode 100644
+index 0000000000..8f68f7cec5
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+@@ -0,0 +1,47 @@
++#/** @file
++#
++#    Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#    Copyright (c) 2018, Linaro Limited. All rights reserved.
++#
++#    This program and the accompanying materials
++#    are licensed and made available under the terms and conditions of the BSD License
++#    which accompanies this distribution. The full text of the license may be found at
++#    http://opensource.org/licenses/bsd-license.php
++#
++#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = OemMiscLib
++  FILE_GUID                      = 3002911C-C160-4C46-93BB-782846673EEA
++  MODULE_TYPE                    = BASE
++  VERSION_STRING                 = 1.0
++  LIBRARY_CLASS                  = OemMiscLib
++
++[Sources.common]
++  BoardFeatureD06.c
++  BoardFeatureD06Strings.uni
++  OemMiscLibD06.c
++
++[Packages]
++  ArmPkg/ArmPkg.dec
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  PcdLib
++  SerdesLib
++  TimerLib
++
++[Ppis]
++  gEfiPeiReadOnlyVariable2PpiGuid   ## SOMETIMES_CONSUMES
++
++[Pcd]
++  gArmTokenSpaceGuid.PcdArmArchTimerFreqInHz
++  gHisiTokenSpaceGuid.PcdIsMPBoot
++  gHisiTokenSpaceGuid.PcdSocketMask
++  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
+diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+index 87cb498dd7..efecb9aa77 100644
+--- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
++++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+@@ -22,7 +22,11 @@
+ #include <PlatformArch.h>
+ #include <Library/I2CLib.h>
+ 
+-#define PCIEDEVICE_REPORT_MAX      4
++#define PCIEDEVICE_REPORT_MAX      8
++#define MAX_PROCESSOR_SOCKETS      MAX_SOCKET
++#define MAX_MEMORY_CHANNELS        MAX_CHANNEL
++#define MAX_DIMM_PER_CHANNEL       MAX_DIMM
++
+ typedef struct _REPORT_PCIEDIDVID2BMC{
+     UINTN   Bus;
+     UINTN   Device;
+diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c
+new file mode 100644
+index 0000000000..7e3f2e2a0e
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06.c
+@@ -0,0 +1,432 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include <Uefi.h>
++#include <IndustryStandard/SmBios.h>
++#include <Library/BaseMemoryLib.h>
++#include <Library/DebugLib.h>
++#include <Library/HiiLib.h>
++#include <Library/I2CLib.h>
++#include <Library/IoLib.h>
++#include <Library/OemMiscLib.h>
++#include <Library/SerdesLib.h>
++#include <Protocol/Smbios.h>
++
++#include <PlatformArch.h>
++
++I2C_DEVICE gRtcDevice = {
++  .Socket = 0,
++  .Port = 5,
++  .DeviceType = DEVICE_TYPE_SPD,
++  .SlaveDeviceAddress = 0x68
++};
++
++SERDES_POLARITY_INVERT gSerdesPolarityTxDesc[] =
++{
++  {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
++};
++
++SERDES_POLARITY_INVERT gSerdesPolarityRxDesc[] =
++{
++  {SERDES_INVALID_MACRO_ID, SERDES_INVALID_LANE_NUM}
++};
++
++SERDES_PARAM gSerdesParamNA = {
++  .Hilink0Mode = EmHilink0Hccs1X8Width16,
++  .Hilink1Mode = EmHilink1Hccs0X8Width16,
++  .Hilink2Mode = EmHilink2Pcie2X8,
++  .Hilink3Mode = 0x0,
++  .Hilink4Mode = 0xF,
++  .Hilink5Mode = EmHilink5Sas1X4,
++  .Hilink6Mode = 0x0,
++  .UseSsc      = 0,
++};
++
++SERDES_PARAM gSerdesParamNB = {
++  .Hilink0Mode = EmHilink0Pcie1X8,
++  .Hilink1Mode = EmHilink1Pcie0X8,
++  .Hilink2Mode = EmHilink2Sas0X8,
++  .Hilink3Mode = 0x0,
++  .Hilink4Mode = 0xF,
++  .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2,
++  .Hilink6Mode = 0xF,
++  .UseSsc      = 0,
++};
++
++SERDES_PARAM gSerdesParamS1NA = {
++  .Hilink0Mode = EmHilink0Hccs1X8Width16,
++  .Hilink1Mode = EmHilink1Hccs0X8Width16,
++  .Hilink2Mode = EmHilink2Pcie2X8,
++  .Hilink3Mode = 0x0,
++  .Hilink4Mode = 0xF,
++  .Hilink5Mode = EmHilink5Sas1X4,
++  .Hilink6Mode = 0x0,
++  .UseSsc      = 0,
++};
++
++SERDES_PARAM gSerdesParamS1NB = {
++  .Hilink0Mode = EmHilink0Pcie1X8,
++  .Hilink1Mode = EmHilink1Pcie0X8,
++  .Hilink2Mode = EmHilink2Sas0X8,
++  .Hilink3Mode = 0x0,
++  .Hilink4Mode = 0xF,
++  .Hilink5Mode = EmHilink5Pcie2X2Pcie3X2,
++  .Hilink6Mode = 0xF,
++  .UseSsc      = 0,
++};
++
++
++EFI_STATUS
++OemGetSerdesParam (
++  OUT SERDES_PARAM *ParamA,
++  OUT SERDES_PARAM *ParamB,
++  IN  UINT32       SocketId
++ )
++{
++  if (NULL == ParamA) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
++    return EFI_INVALID_PARAMETER;
++  } if (NULL == ParamB) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Param == NULL!\n", __FUNCTION__, __LINE__));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  if (0 == SocketId) {
++    (VOID) CopyMem (ParamA, &gSerdesParamNA, sizeof (*ParamA));
++    (VOID) CopyMem (ParamB, &gSerdesParamNB, sizeof (*ParamB));
++  } else {
++    (VOID) CopyMem (ParamA, &gSerdesParamS1NA, sizeof (*ParamA));
++    (VOID) CopyMem (ParamB, &gSerdesParamS1NB, sizeof (*ParamB));
++  }
++
++  return EFI_SUCCESS;
++}
++
++VOID
++OemPcieResetAndOffReset (
++  VOID
++  )
++{
++  return;
++}
++
++SMBIOS_TABLE_TYPE9 gPcieSlotInfo[] = {
++  // PCIe0 Slot 1
++  {
++    {                                       // Hdr
++        EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++        0,                                  // Length,
++        0                                   // Handle
++    },
++    1,                                      // SlotDesignation
++    SlotTypePciExpressX16,                  // SlotType
++    SlotDataBusWidth16X,                    // SlotDataBusWidth
++    SlotUsageAvailable,                     // SlotUsage
++    SlotLengthOther,                        // SlotLength
++    0x0001,                                 // SlotId
++    {                                       // SlotCharacteristics1
++        0,                                  // CharacteristicsUnknown  :1;
++        0,                                  // Provides50Volts         :1;
++        0,                                  // Provides33Volts         :1;
++        0,                                  // SharedSlot              :1;
++        0,                                  // PcCard16Supported       :1;
++        0,                                  // CardBusSupported        :1;
++        0,                                  // ZoomVideoSupported      :1;
++        0                                   // ModemRingResumeSupported:1;
++    },
++    {                                       // SlotCharacteristics2
++        0,                                  // PmeSignalSupported      :1;
++        0,                                  // HotPlugDevicesSupported :1;
++        0,                                  // SmbusSignalSupported    :1;
++        0                                   // Reserved                :5;
++    },
++    0x00,                                   // SegmentGroupNum
++    0x00,                                   // BusNum
++    0                                       // DevFuncNum
++  },
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0002,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0003,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++
++
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0004,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX16,                  // SlotType
++      SlotDataBusWidth16X,                    // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0005,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0006,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0007,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++  {
++      {                                       // Hdr
++          EFI_SMBIOS_TYPE_SYSTEM_SLOTS,       // Type,
++          0,                                  // Length,
++          0                                   // Handle
++      },
++      1,                                      // SlotDesignation
++      SlotTypePciExpressX8,                   // SlotType
++      SlotDataBusWidth8X,                     // SlotDataBusWidth
++      SlotUsageAvailable,                     // SlotUsage
++      SlotLengthOther,                        // SlotLength
++      0x0008,                                 // SlotId
++      {                                       // SlotCharacteristics1
++          0,                                  // CharacteristicsUnknown  :1;
++          0,                                  // Provides50Volts         :1;
++          0,                                  // Provides33Volts         :1;
++          0,                                  // SharedSlot              :1;
++          0,                                  // PcCard16Supported       :1;
++          0,                                  // CardBusSupported        :1;
++          0,                                  // ZoomVideoSupported      :1;
++          0                                   // ModemRingResumeSupported:1;
++      },
++      {                                       // SlotCharacteristics2
++          0,                                  // PmeSignalSupported      :1;
++          0,                                  // HotPlugDevicesSupported :1;
++          0,                                  // SmbusSignalSupported    :1;
++          0                                   // Reserved                :5;
++      },
++      0x00,                                   // SegmentGroupNum
++      0x00,                                   // BusNum
++      0                                       // DevFuncNum
++  },
++
++  };
++
++UINT8
++OemGetPcieSlotNumber (
++  VOID
++  )
++{
++  return sizeof (gPcieSlotInfo) / sizeof (SMBIOS_TABLE_TYPE9);
++}
++
++EFI_STRING_ID gDimmToDevLocator[MAX_SOCKET][MAX_CHANNEL][MAX_DIMM] = {
++  {{STRING_TOKEN(STR_LEMON_C10_DIMM_000), STRING_TOKEN(STR_LEMON_C10_DIMM_001)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_010), STRING_TOKEN(STR_LEMON_C10_DIMM_011)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_020), STRING_TOKEN(STR_LEMON_C10_DIMM_021)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_030), STRING_TOKEN(STR_LEMON_C10_DIMM_031)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_040), STRING_TOKEN(STR_LEMON_C10_DIMM_041)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_050), STRING_TOKEN(STR_LEMON_C10_DIMM_051)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_060), STRING_TOKEN(STR_LEMON_C10_DIMM_061)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_070), STRING_TOKEN(STR_LEMON_C10_DIMM_071)}},
++
++  {{STRING_TOKEN(STR_LEMON_C10_DIMM_100), STRING_TOKEN(STR_LEMON_C10_DIMM_101)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_110), STRING_TOKEN(STR_LEMON_C10_DIMM_111)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_120), STRING_TOKEN(STR_LEMON_C10_DIMM_121)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_130), STRING_TOKEN(STR_LEMON_C10_DIMM_131)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_140), STRING_TOKEN(STR_LEMON_C10_DIMM_141)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_150), STRING_TOKEN(STR_LEMON_C10_DIMM_151)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_160), STRING_TOKEN(STR_LEMON_C10_DIMM_161)},
++   {STRING_TOKEN(STR_LEMON_C10_DIMM_170), STRING_TOKEN(STR_LEMON_C10_DIMM_171)}}
++};
++
++EFI_HII_HANDLE
++EFIAPI
++OemGetPackages (
++  VOID
++  )
++{
++  return HiiAddPackages (
++           &gEfiCallerIdGuid,
++           NULL,
++           OemMiscLibStrings,
++           NULL,
++           NULL
++           );
++}
++
++
+diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+new file mode 100644
+index 0000000000..2cd360d49f
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+@@ -0,0 +1,132 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include <Uefi.h>
++#include <PlatformArch.h>
++#include <Library/DebugLib.h>
++#include <Library/IoLib.h>
++#include <Library/LpcLib.h>
++#include <Library/OemAddressMapLib.h>
++#include <Library/OemMiscLib.h>
++#include <Library/PcdLib.h>
++#include <Library/PlatformSysCtrlLib.h>
++#include <Library/SerdesLib.h>
++#include <Library/SerialPortLib.h>
++#include <Library/TimerLib.h>
++
++REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
++  {67,0,0,0},
++  {225,0,0,3},
++  {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
++  {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
++};
++
++// Right now we only support 1P
++BOOLEAN
++OemIsSocketPresent (
++  UINTN Socket
++  )
++{
++  UINT32 SocketMask = PcdGet32 (PcdSocketMask);
++  return (BOOLEAN)((SocketMask & (1 << Socket)) ? TRUE : FALSE);
++}
++
++
++UINTN
++OemGetSocketNumber (
++  VOID
++  )
++{
++  if(!OemIsMpBoot ()) {
++    return 1;
++  }
++
++  return MAX_PROCESSOR_SOCKETS;
++}
++
++
++UINTN
++OemGetDdrChannel (
++  VOID
++  )
++{
++  return MAX_MEMORY_CHANNELS;
++}
++
++
++UINTN
++OemGetDimmSlot (
++  UINTN Socket,
++  UINTN Channel
++  )
++{
++  return MAX_DIMM_PER_CHANNEL;
++}
++
++
++VOID
++CoreSelectBoot (
++  VOID
++  )
++{
++  if (!PcdGet64 (PcdTrustedFirmwareEnable))
++  {
++    StartupAp ();
++  }
++
++  return;
++}
++
++BOOLEAN
++OemIsMpBoot (
++  VOID
++  )
++{
++  return PcdGet32 (PcdIsMPBoot);
++}
++
++VOID
++OemLpcInit (
++  VOID
++  )
++{
++  LpcInit ();
++  return;
++}
++
++UINT32
++OemIsWarmBoot (
++  VOID
++  )
++{
++  return 0;
++}
++
++VOID
++OemBiosSwitch (
++  UINT32 Master
++  )
++{
++  (VOID)Master;
++  return;
++}
++
++BOOLEAN
++OemIsNeedDisableExpanderBuffer (
++  VOID
++  )
++{
++  return TRUE;
++}
+diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni
+new file mode 100644
+index 0000000000..046fa05dff
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/BoardFeatureD06Strings.uni
+@@ -0,0 +1,64 @@
++// *++
++//
++// Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR>
++//
++// This program and the accompanying materials
++// are licensed and made available under the terms and conditions of the BSD License
++// which accompanies this distribution.  The full text of the license may be found at
++// http://opensource.org/licenses/bsd-license.php
++//
++// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++//
++// --*/
++
++/=#
++
++#langdef en-US "English"
++
++//
++// Begin English Language Strings
++//
++#string STR_MEMORY_SUBCLASS_UNKNOWN    #language en-US  "Unknown"
++
++//
++// DIMM Device Locator strings
++
++// D06
++#string STR_LEMON_C10_DIMM_000     #language en-US "J5"
++#string STR_LEMON_C10_DIMM_001     #language en-US "J6"
++#string STR_LEMON_C10_DIMM_010     #language en-US "J7"
++#string STR_LEMON_C10_DIMM_011     #language en-US "J8"
++#string STR_LEMON_C10_DIMM_020     #language en-US "J9"
++#string STR_LEMON_C10_DIMM_021     #language en-US "J10"
++#string STR_LEMON_C10_DIMM_030     #language en-US "J11"
++#string STR_LEMON_C10_DIMM_031     #language en-US "J12"
++#string STR_LEMON_C10_DIMM_040     #language en-US "J13"
++#string STR_LEMON_C10_DIMM_041     #language en-US "J14"
++#string STR_LEMON_C10_DIMM_050     #language en-US "J15"
++#string STR_LEMON_C10_DIMM_051     #language en-US "J16"
++#string STR_LEMON_C10_DIMM_060     #language en-US "J17"
++#string STR_LEMON_C10_DIMM_061     #language en-US "J18"
++#string STR_LEMON_C10_DIMM_070     #language en-US "J19"
++#string STR_LEMON_C10_DIMM_071     #language en-US "J20"
++#string STR_LEMON_C10_DIMM_100     #language en-US "J21"
++#string STR_LEMON_C10_DIMM_101     #language en-US "J22"
++#string STR_LEMON_C10_DIMM_110     #language en-US "J23"
++#string STR_LEMON_C10_DIMM_111     #language en-US "J24"
++#string STR_LEMON_C10_DIMM_120     #language en-US "J25"
++#string STR_LEMON_C10_DIMM_121     #language en-US "J26"
++#string STR_LEMON_C10_DIMM_130     #language en-US "J27"
++#string STR_LEMON_C10_DIMM_131     #language en-US "J28"
++#string STR_LEMON_C10_DIMM_140     #language en-US "J29"
++#string STR_LEMON_C10_DIMM_141     #language en-US "J30"
++#string STR_LEMON_C10_DIMM_150     #language en-US "J31"
++#string STR_LEMON_C10_DIMM_151     #language en-US "J32"
++#string STR_LEMON_C10_DIMM_160     #language en-US "J33"
++#string STR_LEMON_C10_DIMM_161     #language en-US "J34"
++#string STR_LEMON_C10_DIMM_170     #language en-US "J35"
++#string STR_LEMON_C10_DIMM_171     #language en-US "J36"
++
++//
++// End English Language Strings
++//
++
+-- 
+2.17.0
+
diff --git a/v2/v2-0014-Silicon-Hisilicon-D06-Wait-for-all-disk-ready.patch b/v2/v2-0014-Silicon-Hisilicon-D06-Wait-for-all-disk-ready.patch
new file mode 100644
index 0000000000..8653ee9159
--- /dev/null
+++ b/v2/v2-0014-Silicon-Hisilicon-D06-Wait-for-all-disk-ready.patch
@@ -0,0 +1,132 @@
+From 1bf2ad05d4558134248da8bd92072a15db3a6de1 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sat, 12 May 2018 17:26:36 +0800
+Subject: [PATCH edk2-platforms v2 14/43] Silicon/Hisilicon/D06: Wait for all
+ disk ready
+
+This patch is relative to D06 SasDxe driver. The SasDxe set a
+variable to notice this libray. Here Wait for all disk ready
+for 15S at most.
+
+D06:
+For using straight-through hard disk backboard, some disk need
+15 seconds to ready. Actually, wait less 15 seconds here(minus
+the time from end of SAS driver to here).
+For using expander backboard, wait less 6 seconds here(minus
+the time from end of SAS driver to here).
+
+D03/D05:
+As Sas driver don't write the SASDiskInfo variable, D03/D05 will
+break the loop, so it no waiting here.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/HisiPkg.dec                                               |  1 +
+ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf |  2 +
+ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c               | 43 ++++++++++++++++++++
+ 3 files changed, 46 insertions(+)
+
+diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec
+index 35bea970ec..b56a6a6af7 100644
+--- a/Silicon/Hisilicon/HisiPkg.dec
++++ b/Silicon/Hisilicon/HisiPkg.dec
+@@ -45,6 +45,7 @@
+ 
+   gHisiEfiMemoryMapGuid  = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f}}
+   gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}}
++  gHisiOemVariableGuid = {0xac62b9a5, 0x9939, 0x41d3, {0xff, 0x5c, 0xc5, 0x80, 0x32, 0x7d, 0x9b, 0x29}}
+   gOemBootVariableGuid = {0xb7784577, 0x5aaf, 0x4557, {0xa1, 0x99, 0xd4, 0xa4, 0x2f, 0x45, 0x06, 0xf8}}
+   gEfiHisiSocControllerGuid = {0xee369cc3, 0xa743, 0x5382, {0x75, 0x64, 0x53, 0xe4, 0x31, 0x19, 0x38, 0x35}}
+ 
+diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+index 7a53befc44..a093f13fb0 100644
+--- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
++++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+@@ -49,6 +49,7 @@
+   MemoryAllocationLib
+   PcdLib
+   PrintLib
++  TimerLib
+   UefiBootManagerLib
+   UefiBootServicesTableLib
+   UefiLib
+@@ -67,6 +68,7 @@
+ [Guids]
+   gEfiEndOfDxeEventGroupGuid
+   gEfiTtyTermGuid
++  gHisiOemVariableGuid
+ 
+ [Protocols]
+   gEfiGenericMemTestProtocolGuid
+diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
+index 7dd5ba615c..d5f6d78fa4 100644
+--- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
++++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
+@@ -20,6 +20,7 @@
+ #include <Library/BmcConfigBootLib.h>
+ #include <Library/DevicePathLib.h>
+ #include <Library/PcdLib.h>
++#include <Library/TimerLib.h>
+ #include <Library/UefiBootManagerLib.h>
+ #include <Library/UefiLib.h>
+ #include <Protocol/DevicePath.h>
+@@ -554,6 +555,47 @@ PlatformBootManagerBeforeConsole (
+   PlatformRegisterOptionsAndKeys ();
+ }
+ 
++STATIC
++VOID
++WaitForDiskReady (
++  )
++{
++  EFI_STATUS                Status;
++  UINT32                    Index;
++  UINTN                     DataSize;
++  UINT32                    DiskInfo;
++  UINT8                     IsFinished;
++
++  Status = EFI_NOT_FOUND;
++  DataSize = sizeof (UINT32);
++  // Wait for 15 seconds at most.
++  for (Index = 0; Index < 15; Index++) {
++    Status = gRT->GetVariable (
++                    L"SASDiskInfo",
++                    &gHisiOemVariableGuid,
++                    NULL,
++                    &DataSize,
++                    &DiskInfo
++                    );
++    if (EFI_ERROR(Status)) {
++      DEBUG ((DEBUG_ERROR, "Get DiskInfo:%r\n", Status));
++      break;
++    }
++
++    IsFinished = (UINT8)(DiskInfo >> 24);
++    if (IsFinished) {
++      break;
++    }
++    DEBUG ((DEBUG_ERROR, "%a", Index == 0 ? "Wait for disk." : "."));
++    MicroSecondDelay(1000 * 1000);
++  }
++
++  if (!EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "DiskInfo:%x\n", DiskInfo));
++    EfiBootManagerConnectAll ();
++  }
++}
++
+ /**
+   Do the platform specific action after the console is ready
+   Possible things that can be done in PlatformBootManagerAfterConsole:
+@@ -583,6 +625,7 @@ PlatformBootManagerAfterConsole (
+   // Connect the rest of the devices.
+   //
+   EfiBootManagerConnectAll ();
++  WaitForDiskReady ();
+ 
+   //
+   // Enumerate all possible boot options.
+-- 
+2.17.0
+
diff --git a/v2/v2-0015-Silicon-Hisilicon-Acpi-Unify-HisiAcipPlatformDxe.patch b/v2/v2-0015-Silicon-Hisilicon-Acpi-Unify-HisiAcipPlatformDxe.patch
new file mode 100644
index 0000000000..42a1c605ee
--- /dev/null
+++ b/v2/v2-0015-Silicon-Hisilicon-Acpi-Unify-HisiAcipPlatformDxe.patch
@@ -0,0 +1,126 @@
+From cb2f00d4a6634df9d4ae16cc0ec877a930de1604 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Fri, 22 Jun 2018 14:09:41 +0800
+Subject: [PATCH edk2-platforms v2 15/43] Silicon/Hisilicon/Acpi: Unify
+ HisiAcipPlatformDxe
+
+The EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE struct is used by
+UpdateAcpiTable.c and Srat aslc. The struct may be different
+according to chips, so move some macro to PlatformArch.h.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Hi1610/Include/PlatformArch.h                 |  6 ++++
+ Silicon/Hisilicon/Hi1620/Include/PlatformArch.h                 |  6 ++++
+ Silicon/Hisilicon/Include/Library/AcpiNextLib.h                 | 31 ++++++++++++++------
+ Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c |  2 --
+ 4 files changed, 34 insertions(+), 11 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+index f39ae0748c..1ebddca4e5 100644
+--- a/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1610/Include/PlatformArch.h
+@@ -30,6 +30,12 @@
+ // Max NUMA node number for each node type
+ #define MAX_NUM_PER_TYPE 8
+ 
++// for acpi
++#define NODE_IN_SOCKET                                  2
++#define CORE_NUM_PER_SOCKET                             32
++#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT        10
++#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT       8
++
+ #define S1_BASE               0x40000000000
+ 
+ #define RASC_BASE                (0x5000)
+diff --git a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
+index 9539cfdada..f3ad45f6c6 100644
+--- a/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
++++ b/Silicon/Hisilicon/Hi1620/Include/PlatformArch.h
+@@ -57,5 +57,11 @@
+   EFI_ACPI_ARM_CREATOR_REVISION   /* UINT32  CreatorRevision */ \
+   }
+ 
++// for acpi
++#define NODE_IN_SOCKET                                  2
++#define CORE_NUM_PER_SOCKET                             48
++#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT        16
++#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT       1
++
+ #endif
+ 
+diff --git a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
+index fd05a3b960..2abffb65fc 100644
+--- a/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
++++ b/Silicon/Hisilicon/Include/Library/AcpiNextLib.h
+@@ -19,6 +19,21 @@
+ #ifndef __ACPI_NEXT_LIB_H__
+ #define __ACPI_NEXT_LIB_H__
+ 
++#include <PlatformArch.h>
++
++///
++/// ITS Affinity Structure Definition
++///
++#pragma pack(1)
++typedef struct {
++  UINT8   Type;
++  UINT8   Length;
++  UINT32  ProximityDomain;
++  UINT16  Reserved;
++  UINT32  ItsHwId;
++} EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE;
++#pragma pack()
++
+ #define EFI_ACPI_6_1_GIC_ITS_INIT(GicITSHwId, GicITSBase) \
+   { \
+     EFI_ACPI_6_1_GIC_ITS, sizeof (EFI_ACPI_6_1_GIC_ITS_STRUCTURE), EFI_ACPI_RESERVED_WORD, \
+@@ -42,8 +57,8 @@
+ #define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(                                               \
+     ProximityDomain, ItsId)                                                                     \
+   {                                                                                             \
+-    4, sizeof (EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE), ProximityDomain,                           \
+-    {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE}, ItsId                                                               \
++    4, sizeof (EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE), ProximityDomain,                           \
++    EFI_ACPI_RESERVED_WORD, ItsId                                                               \
+   }
+ 
+ #define EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(                                              \
+@@ -75,15 +90,13 @@
+ // Define the number of each table type.
+ // This is where the table layout is modified.
+ //
+-#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT  64
+-#define EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT                10
+-#define EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT               8
++#define EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT  (MAX_SOCKET*CORE_NUM_PER_SOCKET)
+ 
+ typedef struct {
+-  EFI_ACPI_6_0_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER          Header;
+-  EFI_ACPI_6_0_MEMORY_AFFINITY_STRUCTURE                      Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
+-  EFI_ACPI_6_0_GICC_AFFINITY_STRUCTURE                        Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
+-  EFI_ACPI_6_2_GIC_ITS_AFFINITY_STRUCTURE                     Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
++  EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_HEADER          Header;
++  EFI_ACPI_6_2_MEMORY_AFFINITY_STRUCTURE                      Memory[EFI_ACPI_MEMORY_AFFINITY_STRUCTURE_COUNT];
++  EFI_ACPI_6_2_GICC_AFFINITY_STRUCTURE                        Gicc[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
++  EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE                         Its[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
+ } EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE;
+ 
+ #pragma pack()
+diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+index f5869841dc..54f49977c3 100644
+--- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
++++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+@@ -20,8 +20,6 @@
+ #include <Library/UefiBootServicesTableLib.h>
+ #include <Library/UefiLib.h>
+ 
+-#define CORE_NUM_PER_SOCKET  32
+-#define NODE_IN_SOCKET       2
+ #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET)
+ 
+ STATIC
+-- 
+2.17.0
+
diff --git a/v2/v2-0016-Hisilicon-D06-Add-Debug-Serial-Port-Init-Driver.patch b/v2/v2-0016-Hisilicon-D06-Add-Debug-Serial-Port-Init-Driver.patch
new file mode 100644
index 0000000000..39d0253529
--- /dev/null
+++ b/v2/v2-0016-Hisilicon-D06-Add-Debug-Serial-Port-Init-Driver.patch
@@ -0,0 +1,172 @@
+From 476730eb3dc5807555d4908abc39f2a5becc130c Mon Sep 17 00:00:00 2001
+From: Heyi Guo <heyi.guo@linaro.org>
+Date: Mon, 7 May 2018 15:45:38 +0800
+Subject: [PATCH edk2-platforms v2 16/43] Hisilicon/D06: Add Debug Serial Port
+ Init Driver
+
+Hi1620 have two physical PL011 serial ports on the board,
+one for serial port console (described by ACPI SPCR) and
+the other for standard debug port (described by ACPI DBG2).
+This driver is to initialize the debug UART, not the serial
+console.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                                               |  1 +
+ Platform/Hisilicon/D06/D06.fdf                                                               |  1 +
+ Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf | 48 +++++++++++++++
+ Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c   | 64 ++++++++++++++++++++
+ 4 files changed, 114 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 9ca7160dad..20d2d2a1b4 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -422,6 +422,7 @@
+   # Memory test
+   #
+   MdeModulePkg/Universal/MemoryTest/NullMemoryTestDxe/NullMemoryTestDxe.inf
++  Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+   MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+   MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+   MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index 07fe096f61..8cac126ccf 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -303,6 +303,7 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+   INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ 
++  INF Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+   INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
+   #
+   # Build Shell from latest source code instead of prebuilt binary
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf b/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+new file mode 100644
+index 0000000000..8c91bdf0f4
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+@@ -0,0 +1,48 @@
++#/** @file
++#
++#    Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved.
++#    Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved.
++#
++#    This program and the accompanying materials
++#    are licensed and made available under the terms and conditions of the BSD License
++#    which accompanies this distribution. The full text of the license may be found at
++#    http://opensource.org/licenses/bsd-license.php
++#
++#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = Pl011DebugSerialPortInitDxe
++  FILE_GUID                      = 16D53E86-7EA4-47bd-861F-511EA9B8ABE0
++  MODULE_TYPE                    = DXE_DRIVER
++  VERSION_STRING                 = 1.0
++  ENTRY_POINT                    = SerialPortEntry
++
++[Sources.common]
++  Pl011DebugSerialPortInitDxe.c
++
++
++[Packages]
++  ArmPlatformPkg/ArmPlatformPkg.dec
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  BaseLib
++  UefiDriverEntryPoint
++
++[Pcd]
++  gArmPlatformTokenSpaceGuid.PL011UartClkInHz
++  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultDataBits
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultParity
++  gEfiMdePkgTokenSpaceGuid.PcdUartDefaultStopBits
++
++[Depex]
++  TRUE
++
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c b/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c
+new file mode 100644
+index 0000000000..8f83737327
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.c
+@@ -0,0 +1,64 @@
++/** @file
++
++    Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved.
++    Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved.
++
++    This program and the accompanying materials
++    are licensed and made available under the terms and conditions of the BSD License
++    which accompanies this distribution. The full text of the license may be found at
++    http://opensource.org/licenses/bsd-license.php
++
++    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#include <Uefi.h>
++#include <Library/BaseLib.h>
++#include <Library/DebugLib.h>
++#include <Library/PL011UartLib.h>
++#include <Library/PcdLib.h>
++#include <Library/SerialPortLib.h>
++
++RETURN_STATUS
++EFIAPI
++DebugSerialPortInitialize (
++  VOID
++  )
++{
++  UINT64              BaudRate;
++  UINT32              ReceiveFifoDepth;
++  EFI_PARITY_TYPE     Parity;
++  UINT8               DataBits;
++  EFI_STOP_BITS_TYPE  StopBits;
++
++  BaudRate = FixedPcdGet64 (PcdUartDefaultBaudRate);
++  ReceiveFifoDepth = 0;         // Use default FIFO depth
++  Parity = (EFI_PARITY_TYPE)FixedPcdGet8 (PcdUartDefaultParity);
++  DataBits = FixedPcdGet8 (PcdUartDefaultDataBits);
++  StopBits = (EFI_STOP_BITS_TYPE) FixedPcdGet8 (PcdUartDefaultStopBits);
++  return PL011UartInitializePort (
++           (UINTN)FixedPcdGet64 (PcdSerialDbgRegisterBase),
++           FixedPcdGet32 (PL011UartClkInHz),
++           &BaudRate,
++           &ReceiveFifoDepth,
++           &Parity,
++           &DataBits,
++           &StopBits
++           );
++}
++
++EFI_STATUS
++SerialPortEntry (
++  IN EFI_HANDLE         ImageHandle,
++  IN EFI_SYSTEM_TABLE   *SystemTable
++  )
++{
++  EFI_STATUS Status;
++  Status = DebugSerialPortInitialize ();
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "CPU1 TB serial port init ERROR: %r\n", Status));
++  }
++  return EFI_SUCCESS;
++}
++
+-- 
+2.17.0
+
diff --git a/v2/v2-0017-Hisilicon-D06-Add-ACPI-Tables-for-D06.patch b/v2/v2-0017-Hisilicon-D06-Add-ACPI-Tables-for-D06.patch
new file mode 100644
index 0000000000..0a2c72f49d
--- /dev/null
+++ b/v2/v2-0017-Hisilicon-D06-Add-ACPI-Tables-for-D06.patch
@@ -0,0 +1,10864 @@
+From 89b4761e354506305df57ee40f6089a536f965ae Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Thu, 21 Jun 2018 15:55:28 +0800
+Subject: [PATCH edk2-platforms v2 17/43] Hisilicon/D06: Add ACPI Tables for
+ D06
+
+ACPI tables for D06 2P, especially,Hi1620Iort.asl is include smmu
+and Hi1620IortNoSmmu.asl is without smmu.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                          |    1 +
+ Platform/Hisilicon/D06/D06.fdf                                          |    1 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf          |   59 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h              |   27 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl                  |  409 ++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl                  |   30 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl           |   35 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl           |   93 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl            |   58 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl           | 1459 ++++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl           |   41 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl            | 1216 ++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl          |   28 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl            |   47 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl            |   57 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl |  249 +++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl |  249 +++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl          |   49 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl       | 1658 ++++++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl                 |   49 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc                     |   67 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc                     |   91 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc                     |   86 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc               |   86 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl                | 1989 ++++++++++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl          | 1736 +++++++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc               |   64 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc               |   64 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc               |   81 +
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc               |  166 ++
+ Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc               |  375 ++++
+ 31 files changed, 10620 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 20d2d2a1b4..9d4a86a4f4 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -332,6 +332,7 @@
+   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+   Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
++  Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+   Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
+   #
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index 8cac126ccf..06203dc079 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -249,6 +249,7 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+   INF Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
++  INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+   INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
+   #
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+new file mode 100644
+index 0000000000..4157e0feef
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+@@ -0,0 +1,59 @@
++## @file
++#
++#  ACPI table data and ASL sources required to boot the platform.
++#
++#  Copyright (c) 2014, ARM Ltd. All rights reserved.
++#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#  Copyright (c) 2018, Linaro Limited. All rights reserved.
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution.  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++#
++##
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = Hi1620AcpiTables
++  FILE_GUID                      = 7E374E25-8E01-4FEE-87F2-390C23C606CD
++  MODULE_TYPE                    = USER_DEFINED
++  VERSION_STRING                 = 1.0
++
++[Sources]
++  Dsdt/DsdtHi1620.asl
++  Facs.aslc
++  Fadt.aslc
++  Gtdt.aslc
++  Hi1620Dbg2.aslc
++  Hi1620Iort.asl
++  Hi1620IortNoSmmu.asl
++  Hi1620Mcfg.aslc
++  Hi1620Slit.aslc
++  Hi1620Spcr.aslc
++  Hi1620Srat.aslc
++  MadtHi1620.aslc
++
++[Packages]
++  ArmPkg/ArmPkg.dec
++  ArmPlatformPkg/ArmPlatformPkg.dec
++  EmbeddedPkg/EmbeddedPkg.dec
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[FixedPcd]
++  gArmPlatformTokenSpaceGuid.PcdCoreCount
++  gArmPlatformTokenSpaceGuid.PcdSerialDbgRegisterBase
++  gArmTokenSpaceGuid.PcdArmArchTimerHypIntrNum
++  gArmTokenSpaceGuid.PcdArmArchTimerIntrNum
++  gArmTokenSpaceGuid.PcdArmArchTimerSecIntrNum
++  gArmTokenSpaceGuid.PcdArmArchTimerVirtIntrNum
++  gArmTokenSpaceGuid.PcdGicDistributorBase
++  gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
++  gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h
+new file mode 100644
+index 0000000000..5a6aa9a876
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Platform.h
+@@ -0,0 +1,27 @@
++/** @file
++*
++*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015-2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++
++#ifndef _HI1620_PLATFORM_H_
++#define _HI1620_PLATFORM_H_
++
++#include <../Include/PlatformArch.h>
++
++#define HI1620_WATCHDOG_COUNT  2
++
++#endif
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl
+new file mode 100644
+index 0000000000..ef8dae4d01
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/CPU.asl
+@@ -0,0 +1,409 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  //
++  // A57x16 Processor declaration
++  //
++  Device(CPU0) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 0)
++  }
++  Device(CPU1) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 1)
++  }
++  Device(CPU2) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 2)
++  }
++  Device(CPU3) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 3)
++  }
++  Device(CPU4) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 4)
++  }
++  Device(CPU5) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 5)
++  }
++  Device(CPU6) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 6)
++  }
++  Device(CPU7) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 7)
++  }
++  Device(CPU8) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 8)
++  }
++  Device(CPU9) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 9)
++  }
++  Device(CP10) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 10)
++  }
++  Device(CP11) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 11)
++  }
++  Device(CP12) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 12)
++  }
++  Device(CP13) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 13)
++  }
++  Device(CP14) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 14)
++  }
++  Device(CP15) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 15)
++  }
++  Device(CP16) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 16)
++  }
++  Device(CP17) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 17)
++  }
++  Device(CP18) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 18)
++  }
++  Device(CP19) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 19)
++  }
++  Device(CP20) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 20)
++  }
++  Device(CP21) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 21)
++  }
++  Device(CP22) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 22)
++  }
++  Device(CP23) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 23)
++  }
++  Device(CP24) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 24)
++  }
++  Device(CP25) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 25)
++  }
++  Device(CP26) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 26)
++  }
++  Device(CP27) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 27)
++  }
++  Device(CP28) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 28)
++  }
++  Device(CP29) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 29)
++  }
++  Device(CP30) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 30)
++  }
++  Device(CP31) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 31)
++  }
++  Device(CP32) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 32)
++  }
++  Device(CP33) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 33)
++  }
++  Device(CP34) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 34)
++  }
++  Device(CP35) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 35)
++  }
++  Device(CP36) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 36)
++  }
++  Device(CP37) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 37)
++  }
++  Device(CP38) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 38)
++  }
++  Device(CP39) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 39)
++  }
++  Device(CP40) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 40)
++  }
++  Device(CP41) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 41)
++  }
++  Device(CP42) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 42)
++  }
++  Device(CP43) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 43)
++  }
++  Device(CP44) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 44)
++  }
++  Device(CP45) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 45)
++  }
++  Device(CP46) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 46)
++  }
++  Device(CP47) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 47)
++  }
++
++  Device(CP48) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 48)
++  }
++  Device(CP49) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 49)
++  }
++  Device(CP50) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 50)
++  }
++  Device(CP51) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 51)
++  }
++  Device(CP52) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 52)
++  }
++  Device(CP53) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 53)
++  }
++  Device(CP54) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 54)
++  }
++  Device(CP55) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 55)
++  }
++  Device(CP56) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 56)
++  }
++  Device(CP57) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 57)
++  }
++  Device(CP58) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 58)
++  }
++  Device(CP59) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 59)
++  }
++  Device(CP60) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 60)
++  }
++  Device(CP61) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 61)
++  }
++  Device(CP62) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 62)
++  }
++  Device(CP63) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 63)
++  }
++  Device(CP64) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 64)
++  }
++  Device(CP65) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 65)
++  }
++  Device(CP66) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 66)
++  }
++  Device(CP67) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 67)
++  }
++  Device(CP68) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 68)
++  }
++  Device(CP69) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 69)
++  }
++  Device(CP70) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 70)
++  }
++  Device(CP71) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 71)
++  }
++  Device(CP72) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 72)
++  }
++  Device(CP73) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 73)
++  }
++  Device(CP74) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 74)
++  }
++  Device(CP75) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 75)
++  }
++  Device(CP76) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 76)
++  }
++  Device(CP77) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 77)
++  }
++  Device(CP78) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 78)
++  }
++  Device(CP79) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 79)
++  }
++  Device(CP80) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 80)
++  }
++  Device(CP81) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 81)
++  }
++  Device(CP82) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 82)
++  }
++  Device(CP83) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 83)
++  }
++  Device(CP84) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 84)
++  }
++  Device(CP85) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 85)
++  }
++  Device(CP86) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 86)
++  }
++  Device(CP87) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 87)
++  }
++  Device(CP88) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 88)
++  }
++  Device(CP89) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 89)
++  }
++  Device(CP90) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 90)
++  }
++  Device(CP91) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 91)
++  }
++  Device(CP92) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 92)
++  }
++  Device(CP93) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 93)
++  }
++  Device(CP94) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 94)
++  }
++  Device(CP95) {
++    Name(_HID, "ACPI0007")
++    Name(_UID, 95)
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl
+new file mode 100644
+index 0000000000..377d171abb
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Com.asl
+@@ -0,0 +1,30 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  Device(COM0) {
++    Name(_HID, "ARMH0011")
++    Name(_CID, "PL011")
++    Name(_UID, Zero)
++    Name(_CRS, ResourceTemplate() {
++      Memory32Fixed(ReadWrite, 0x94080000, 0x1000)
++      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 141 }
++    })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl
+new file mode 100644
+index 0000000000..7e26ba22b7
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/DsdtHi1620.asl
+@@ -0,0 +1,35 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++#include "Hi1620Platform.h"
++
++DefinitionBlock("DsdtTable.aml", "DSDT", 2, "HISI  ", "HIP08   ", EFI_ACPI_ARM_OEM_REVISION) {
++  include ("Com.asl")
++  include ("CPU.asl")
++  include ("Hi1620Pci.asl")
++  include ("Hi1620Mbig.asl")
++  include ("Hi1620Rde.asl")
++  include ("Hi1620Sec.asl")
++  include ("ipmi.asl")
++  include ("LpcUart_clk.asl")
++  include ("Hi1620Ged.asl")
++  include ("Hi1620Power.asl")
++  include ("Hi1620Apei.asl")
++  include ("Hi1620Mctp.asl")
++  include ("Pv680UncorePmu.asl")
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl
+new file mode 100644
+index 0000000000..0970ed9b99
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Apei.asl
+@@ -0,0 +1,93 @@
++/** @file
++*
++*  Copyright (c) 2018 Hisilicon Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++//Define a control method APEI
++Scope(_SB)
++{
++  Device(GED2) {
++    Name(_HID, "ACPI0013")
++    Name(_UID, 2)
++
++    Name (_CRS, ResourceTemplate ()  {
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive) {
++        122
++      }
++    })
++
++    Method (_EVT, 0x1) {
++      Switch(ToInteger(Arg0)) {
++        Case(122) {
++          Notify (\_SB.ERRD, 0x80)
++        }
++      }
++    }
++
++    Method (_STA, 0x0, NotSerialized) {
++      return (0xF);
++    }
++  }
++}
++
++Device (\_SB.ERRD)
++{
++  Name (_HID, EISAID("PNP0C33"))
++  Name (_UID, 0)
++  Method (_STA, 0x0, NotSerialized) {
++    Return(0xF)
++  }
++}
++
++Name(PWCP, Zero) // Platform-Wide Capability value.
++
++Scope (\_SB) {
++  Method (_OSC,4) {
++    // Create DWord-adressable for Arg3 First DWORD.
++    CreateDWordField(Arg3,0,CDW1)
++
++    // Check for proper UUID
++    If (LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48"))) {
++      // Create DWord-adressable fields from the Capabilities Buffer
++      CreateDWordField (Arg3,4,TPD2)
++
++      // Save Capabilities DWord2
++      Store (TPD2, PWCP)
++
++      // Set Bit[4]: APEI Support
++      Or (PWCP,0x10,PWCP)
++
++      If (LNotEqual(Arg1,One)) {// Unknown revision
++        Or (CDW1,0x08,CDW1)
++      }
++
++      // Update DWORD2 in the buffer
++      Store (PWCP,TPD2)
++
++      Return (Arg3)
++    }
++    ElseIf (LEqual(Arg0, ToUUID("ed855e0c-6c90-47bf-a62a-26de0fc5ad5c"))) { // Check for WHEA GUID
++      CreateDWordField (Arg3,4,TPD3)
++
++      Or (TPD3, 0x10, TPD3) //Set Bit[4]: APEI support.
++
++      If (LNotEqual(Arg1,One)) {// Unknown revision
++        Or (CDW1,0x08,CDW1)
++      }
++
++      return (Arg3)
++    }
++    Else {
++      Or (CDW1,4,CDW1) // Unrecognized UUID
++      Return (Arg3)
++    }
++  } // End _OSC
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl
+new file mode 100644
+index 0000000000..6664c0c681
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Ged.asl
+@@ -0,0 +1,58 @@
++/** @file
++*
++* Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++* Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++* Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++//
++// Ged
++//
++
++//Define a control method power button
++Scope(_SB)
++{
++  OperationRegion(IOM1, SystemMemory, 0x941900C8, 0x4)
++  Field(IOM1, DWordAcc, NoLock, Preserve) {
++    IMX0, 32,
++  }
++
++  Method (_INI) {
++    Store(IMX0, Local0)
++    And(Local0, 0xFFFFFFFC, Local0)
++    Or(Local0, 0x4, Local0)
++    Store(Local0, IMX0)
++  }
++
++  Device(GED1) {
++    Name(_HID, "ACPI0013")
++    Name(_UID, 0)
++
++    Name (_CRS, ResourceTemplate ()  {
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive) {
++        121
++      }
++    })
++
++    Method (_STA, 0x0, NotSerialized) {
++      return (0xF);
++    }
++
++    Method (_EVT, 0x1) {
++      Switch(ToInteger(Arg0)) {
++        Case(121) {
++          Notify (\_SB.PWRB, 0x80)
++        }
++      }
++    }
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl
+new file mode 100644
+index 0000000000..6adf5973a6
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mbig.asl
+@@ -0,0 +1,1459 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++Scope(_SB)
++{
++  //This is for S0-TB-L3T0 PMU implementation
++  Device(MB30) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x30)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-L3T1 PMU implementation
++  Device(MB31) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x31)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-L3T2 PMU implementation
++  Device(MB32) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x32)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-L3T3 PMU implementation
++  Device(MB33) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x33)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-L3T4 PMU implementation
++  Device(MB34) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x34)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-L3T5 PMU implementation
++  Device(MB35) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x35)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-DDRC0 PMU implementation
++  Device(MB38) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x38)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-DDRC1 PMU implementation
++  Device(MB39) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x39)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-DDRC2 PMU implementation
++  Device(MB3A) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x3A)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-DDRC3 PMU implementation
++  Device(MB3B) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x3B)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-HHA0 PMU implementation
++  Device(MB3C) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x3C)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TB-HHA1 PMU implementation
++  Device(MB3D) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x3D)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xA8080000,
++          0xA808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-L3T0 PMU implementation
++  Device(MB10) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x10)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-L3T1 PMU implementation
++  Device(MB11) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x11)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-L3T2 PMU implementation
++  Device(MB12) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x12)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-L3T3 PMU implementation
++  Device(MB13) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x13)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++
++  //This is for S0-TA-L3T4 PMU implementation
++  Device(MB14) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x14)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-L3T5 PMU implementation
++  Device(MB15) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x15)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-DDRC0 PMU implementation
++  Device(MB18) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x18)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-DDRC1 PMU implementation
++  Device(MB19) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x19)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-DDRC2 PMU implementation
++  Device(MB1A) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x1A)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-DDRC3 PMU implementation
++  Device(MB1B) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x1B)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-HHA0 PMU implementation
++  Device(MB1C) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x1C)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S0-TA-HHA1 PMU implementation
++  Device(MB1D) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x1D)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0xAC080000,
++          0xAC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-L3T0 PMU implementation
++  Device(MB70) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x70)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-L3T1 PMU implementation
++  Device(MB71) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x71)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-L3T2 PMU implementation
++  Device(MB72) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x72)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-L3T3 PMU implementation
++  Device(MB73) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x73)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++
++  //This is for S1-TB-L3T4 PMU implementation
++  Device(MB74) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x74)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-L3T5 PMU implementation
++  Device(MB75) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x75)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-DDRC0 PMU implementation
++  Device(MB78) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x78)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-DDRC1 PMU implementation
++  Device(MB79) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x79)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-DDRC2 PMU implementation
++  Device(MB7A) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x7A)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-DDRC3 PMU implementation
++  Device(MB7B) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x7B)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-HHA0 PMU implementation
++  Device(MB7C) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x7C)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TB-HHA1 PMU implementation
++  Device(MB7D) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x7D)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000A8080000,
++          0x4000A808ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-L3T0 PMU implementation
++  Device(MB50) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x50)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-L3T1 PMU implementation
++  Device(MB51) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x51)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-L3T2 PMU implementation
++  Device(MB52) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x52)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-L3T3 PMU implementation
++  Device(MB53) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x53)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++
++  //This is for S1-TA-L3T4 PMU implementation
++  Device(MB54) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x54)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-L3T5 PMU implementation
++  Device(MB55) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x55)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-DDRC0 PMU implementation
++  Device(MB58) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x58)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-DDRC1 PMU implementation
++  Device(MB59) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x59)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-DDRC2 PMU implementation
++  Device(MB5A) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x5A)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-DDRC3 PMU implementation
++  Device(MB5B) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x5B)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-HHA0 PMU implementation
++  Device(MB5C) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x5C)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++
++  //This is for S1-TA-HHA1 PMU implementation
++  Device(MB5D) {
++    Name(_HID, "HISI0152")
++    Name(_UID, 0x5D)
++    Name(_CID, "MBIGen")
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++          ResourceConsumer,
++          ,
++          MinFixed,
++          MaxFixed,
++          NonCacheable,
++          ReadWrite,
++          0x0,
++          0x4000AC080000,
++          0x4000AC08ffff,
++          0x0,
++          0x10000
++      )
++  })
++
++   Name(_DSD, Package () {
++        ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++        Package ()
++        {
++          Package () {"num-pins", 1}
++        }
++   })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl
+new file mode 100644
+index 0000000000..d039e8a110
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Mctp.asl
+@@ -0,0 +1,41 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++Scope(_SB)
++{
++  Device(LOC0) {
++    Name(_HID, "HISI02F1")
++    Name(_UID, 0)
++    Name (_CRS, ResourceTemplate ()  {
++      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive)
++      {
++        488,489
++      }
++    })
++  }
++
++  Device(MCT0) {
++    Name(_HID, "HISI0301")
++    Name(_UID, 0)
++    Name (_CRS, ResourceTemplate ()  {
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI4")
++      {
++        656
++      }
++    })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
+new file mode 100644
+index 0000000000..8e3547926a
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Pci.asl
+@@ -0,0 +1,1216 @@
++/** @file
++*
++*  Copyright (c) 2011-2015, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2016, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++//#include "ArmPlatform.h"
++Scope(_SB)
++{
++  Device (PCI0)
++  {                                          // PCI0 indicate host bridge 0
++    Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++    Name (_UID, 0)
++    Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++    Name(_SEG, 0)                            // Segment of this Root complex
++    Name (_BBN, 0x0)                         // Base Bus Number
++    Name (_CCA, 1)                           // cache coherence attribute
++
++    Name (_PRT, Package (){
++      // INTx configure for RP0, whoes device number is 0
++      // For ESL/FPGA debug, we should modify this according to
++      // specific hardware configuration.
++      Package () {0xFFFF,0,0,640},         // INT_A
++      Package () {0xFFFF,1,0,641},         // INT_B
++      Package () {0xFFFF,2,0,642},         // INT_C
++      Package () {0xFFFF,3,0,643},         // INT_D
++
++      // This is an example of RP1 INTx configure. Adding or not
++      // adding RPx INTx configure deponds on hardware board topology,
++      // if UEFI enables RPx, RPy, RPz... related INTx configure
++      // should be added
++      Package () {0x4FFFF,0,0,640},         // INT_A
++      Package () {0x4FFFF,1,0,641},         // INT_B
++      Package () {0x4FFFF,2,0,642},         // INT_C
++      Package () {0x4FFFF,3,0,643},         // INT_D
++
++      Package () {0x8FFFF,0,0,640},         // INT_A
++      Package () {0x8FFFF,1,0,641},         // INT_B
++      Package () {0x8FFFF,2,0,642},         // INT_C
++      Package () {0x8FFFF,3,0,643},         // INT_D
++
++      Package () {0xCFFFF,0,0,640},         // INT_A
++      Package () {0xCFFFF,1,0,641},         // INT_B
++      Package () {0xCFFFF,2,0,642},         // INT_C
++      Package () {0xCFFFF,3,0,643},         // INT_D
++
++      Package () {0x10FFFF,0,0,640},         // INT_A
++      Package () {0x10FFFF,1,0,641},         // INT_B
++      Package () {0x10FFFF,2,0,642},         // INT_C
++      Package () {0x10FFFF,3,0,643},         // INT_D
++
++      Package () {0x12FFFF,0,0,640},         // INT_A
++      Package () {0x12FFFF,1,0,641},         // INT_B
++      Package () {0x12FFFF,2,0,642},         // INT_C
++      Package () {0x12FFFF,3,0,643},         // INT_D
++      })
++
++    Method (_CRS, 0, Serialized) {
++      // Method is defined in 19.6.82 in ACPI 6.0 spec
++      Name (RBUF, ResourceTemplate () {
++        // 19.3.3 in ACPI 6.0 spec
++        WordBusNumber (
++          ResourceProducer,
++          MinFixed,
++          MaxFixed,
++          PosDecode,
++          0,                                 // AddressGranularity
++          0x00,                              // AddressMinimum - Minimum Bus Number
++          0x3f,                              // AddressMaximum - Maximum Bus Number
++          0,                                 // AddressTranslation - Set to 0
++          0x40                               // RangeLength - Number of Busses
++        )
++        QWordMemory (                        // 64-bit prefetch BAR windows
++          ResourceProducer,
++          PosDecode,
++          MinFixed,
++          MaxFixed,
++          Prefetchable,
++          ReadWrite,
++          0x0,                               // Granularity
++          0x80000000000,                     // Min Base Address pci address
++          0x83fffffffff,                     // Max Base Address
++          0x0,                               // Translate
++          0x4000000000                       // Length, 256G
++        )
++        QWordMemory (                        // 32-bit non-prefetch BAR windows
++          ResourceProducer,
++          PosDecode,
++          MinFixed,
++          MaxFixed,
++          Cacheable,
++          ReadWrite,
++          0x0,                               // Granularity
++          0xe0000000,                        // Min Base Address pci address
++          0xeffeffff,                        // Max Base Address
++          0x0,                               // Translate
++          0xfff0000                          // Length, 256M - 64K
++        )
++        QWordIO (
++          ResourceProducer,
++          MinFixed,
++          MaxFixed,
++          PosDecode,
++          EntireRange,
++          0x0,                               // Granularity
++          0x0,                               // Min Base Address
++          0xffff,                            // Max Base Address
++          0xefff0000,                        // Translate
++          0x10000                            // Length, 64K
++        )}
++      )                                      // Name(RBUF)
++      Return (RBUF)
++    }                                        // Method(_CRS), this method return RBUF!
++
++  //
++  // OS Control Handoff
++  //
++  Name(SUPP, Zero) // PCI _OSC Support Field value
++  Name(CTRL, Zero) // PCI _OSC Control Field value
++
++  Method(_OSC,4) {
++    // Check for proper UUID
++    If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
++      // Create DWord-adressable fields from the Capabilities Buffer
++      CreateDWordField(Arg3,0,CDW1)
++      CreateDWordField(Arg3,4,CDW2)
++      CreateDWordField(Arg3,8,CDW3)
++
++      // Save Capabilities DWord2 & 3
++      Store(CDW2,SUPP)
++      Store(CDW3,CTRL)
++
++      // Only allow native hot plug control if OS supports:
++      //  ASPM
++      //  Clock PM
++      //  MSI/MSI-X
++      If(LNotEqual(And(SUPP, 0x16), 0x16)) {
++        And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
++      }
++
++      // Always allow native PME, AER (no dependencies)
++
++      // Never allow SHPC (no SHPC controller in this system)
++      And(CTRL,0x1D,CTRL)
++
++      If(LNotEqual(Arg1,One)) {  // Unknown revision
++        Or(CDW1,0x08,CDW1)
++      }
++
++      If(LNotEqual(CDW3,CTRL)) {  // Capabilities bits were masked
++        Or(CDW1,0x10,CDW1)
++      }
++
++      // Update DWORD3 in the buffer
++      Store(CTRL,CDW3)
++      Return(Arg3)
++    } Else {
++      Or(CDW1,4,CDW1) // Unrecognized UUID
++      Return(Arg3)
++    }
++  } // End _OSC
++
++  Method (_HPX, 0) {
++    Return (Package(2) {
++      Package(6) {    // PCI Setting Record
++        0x00,         // Type 0
++        0x01,         // Revision 1
++        0x08,         // CacheLineSize in DWORDS
++        0x40,         // LatencyTimer in PCI clocks
++        0x01,         // Enable SERR (Boolean)
++        0x01          // Enable PERR (Boolean)
++      },
++
++      Package(18){   // PCI-X Setting Record
++        0x02,        // Type 2
++        0x01,        // Revision 1
++        0xFFFFFFFF,  // Uncorrectable Error Mask Register AND Mask, Keep ->1
++        0x00000000,  // Uncorrectable Error Mask Register OR Mask, keep ->0
++        0xFFFFFFFF,  // Uncorrectable Error Severity Register AND Mask
++        0x00000000,  // Uncorrectable Error Severity Register OR Mask
++        0xFFFFFFFF,  // Correctable Error Mask Register AND Mask
++        0x00000000,  // Correctable Error Mask Register OR Mask
++        0xFFFFFFFF,  // Advanced Error Capabilities and Control Register AND Mask
++        0x00000000,  // Advanced Error Capabilities and Control Register OR Mask
++        0xFFF7,      // Device Control Register AND Mask
++        0x0007,      // Device Control Register OR Mask
++        0xFFFF,      // Link Control Register AND Mask
++        0x0000,      // Link Control Register OR Mask
++        0xFFFFFFFF,  // Secondary Uncorrectable Error Severity Register AND Mask
++        0x00000000,  // Secondary Uncorrectable Error Severity Register OR Mask
++        0xFFFFFFFF,  // Secondary Uncorrectable Error Mask Register AND Mask
++        0x00000000   // Secondary Uncorrectable Error Mask Register OR Mask
++      }
++    })
++  }
++
++  Method (_STA, 0x0, NotSerialized) {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++} // Device(PCI0)
++
++
++Device (PCI1)
++{                                            // PCI1 indicate host bridge 1
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 1)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x7b)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                          // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0x7b,                              // AddressMinimum - Minimum Bus Number
++        0x7b,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x1                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows, where to show this ??
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x148800000,                       // Min Base Address pci address ??
++        0x148ffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x800000                           // Length, 8M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++} // Device(PCI1)
++
++Device (PCI2)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 2)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x7a)                         // Base Bus Number
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Name (_PRT, Package (){
++    Package () {0xFFFF,0,0,640},         // INT_A
++    Package () {0xFFFF,1,0,641},         // INT_B
++    Package () {0xFFFF,2,0,642},         // INT_C
++    Package () {0xFFFF,3,0,643},         // INT_D
++    Package () {0x1FFFF,0,0,640},         // INT_A
++    Package () {0x1FFFF,1,0,641},         // INT_B
++    Package () {0x1FFFF,2,0,642},         // INT_C
++    Package () {0x1FFFF,3,0,643},         // INT_D
++    Package () {0x2FFFF,0,0,640},         // INT_A
++    Package () {0x2FFFF,1,0,641},         // INT_B
++    Package () {0x2FFFF,2,0,642},         // INT_C
++    Package () {0x2FFFF,3,0,643},         // INT_D
++  })
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource //                               setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0x7a,                              // AddressMinimum - Minimum Bus Number
++        0x7a,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x1                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x20c000000,                       // Min Base Address pci address
++        0x20c1fffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x200000                           // Length, 2M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++}
++
++Device (PCI3)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 3)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x78)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0x78,                              // AddressMinimum - Minimum Bus Number
++        0x79,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x2                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x208000000,                       // Min Base Address pci address
++        0x208ffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x1000000                          // Length, 16M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++}
++
++Device (PCI4)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 4)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x7c)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0x7c,                              // AddressMinimum - Minimum Bus Number
++        0x7d,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x2                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x120000000,                       // Min Base Address pci address
++        0x13fffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x20000000                         // Length, 512M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0x0F)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++}
++
++Device (PCI5)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 5)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x74)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++
++  Name (_PRT, Package (){
++    Package () {0x2FFFF,0,0,640},         // INT_A
++    Package () {0x2FFFF,1,0,641},         // INT_B
++    Package () {0x2FFFF,2,0,642},         // INT_C
++    Package () {0x2FFFF,3,0,643},         // INT_D
++    Package () {0x3FFFF,0,0,640},         // INT_A
++    Package () {0x3FFFF,1,0,641},         // INT_B
++    Package () {0x3FFFF,2,0,642},         // INT_C
++    Package () {0x3FFFF,3,0,643},         // INT_D
++  })
++
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++      ResourceProducer,
++      MinFixed,
++      MaxFixed,
++      PosDecode,
++      0,                                 // AddressGranularity
++      0x74,                              // AddressMinimum - Minimum Bus Number
++      0x76,                              // AddressMaximum - Maximum Bus Number
++      0,                                 // AddressTranslation - Set to 0
++      0x3                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++      ResourceProducer,
++      PosDecode,
++      MinFixed,
++      MaxFixed,
++      Prefetchable,
++      ReadWrite,
++      0x0,                               // Granularity
++      0x144000000,                       // Min Base Address pci address
++      0x147ffffff,                       // Max Base Address
++      0x0,                               // Translate
++      0x4000000                          // Length, 32M
++      )
++      QWordMemory (                        // 32-bit non-prefetch BAR Windows
++      ResourceProducer,
++      PosDecode,
++      MinFixed,
++      MaxFixed,
++      Cacheable,
++      ReadWrite,
++      0x0,                               // Granularity
++      0xa2000000,                        // Min Base Address pci address
++      0xa2ffffff,                        // Max Base Address
++      0x0,                               // Translate
++      0x1000000                          // Length, 16M
++      )
++    })                                 // Name(RBUF)
++    Return (RBUF)
++  }                                    // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Device (SAS0)
++  {
++    Name (_ADR, 0x00020000)
++    Name (_DSD, Package ()
++    {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package ()
++      {
++        Package (2) {"sas-addr", Package() {0x50, 0x01, 0x88, 0x20, 0x16, 0x00, 0x00, 0x00}},
++        Package ()  {"queue-count", 16},
++        Package ()  {"phy-count", 8},
++      }
++    })
++
++    OperationRegion (CTL, SystemMemory, 0x140070000, 0x1000)
++    Field (CTL, DWordAcc, NoLock, Preserve)
++    {
++      Offset (0xa18),
++      RST, 32,
++      DRST, 32,
++    }
++
++    OperationRegion (TXD, SystemMemory, 0xA2000000, 0x4000)
++    Field (TXD, DwordAcc, NoLock, Preserve)
++    {
++      Offset (0x2350),  //port0
++      ST00, 32,   //0x2350
++      ST01, 32,   //0x2354
++      ST02, 32,   //0x2358
++      ST03, 32,   //0x235c
++      ST04, 32,   //0x2360
++      ST05, 32,   //0x2364
++      ST06, 32,   //0x2368
++      ST07, 32,   //0x236c
++      Offset (0x2750),  //port1
++      ST10, 32,   //0x2750
++      ST11, 32,   //0x2754
++      ST12, 32,   //0x2758
++      ST13, 32,   //0x275c
++      ST14, 32,   //0x2760
++      ST15, 32,   //0x2764
++      ST16, 32,   //0x2768
++      ST17, 32,   //0x276c
++      Offset (0x2b50),  //port2
++      ST20, 32,   //0x2b50
++      ST21, 32,   //0x2b54
++      ST22, 32,   //0x2b58
++      ST23, 32,   //0x2b5c
++      ST24, 32,   //0x2b60
++      ST25, 32,   //0x2b64
++      ST26, 32,   //0x2b68
++      ST27, 32,   //0x2b6c
++      Offset (0x2f50),  //port3
++      ST30, 32,   //0x2f50
++      ST31, 32,   //0x2f54
++      ST32, 32,   //0x2f58
++      ST33, 32,   //0x2f5c
++      ST34, 32,   //0x2f60
++      ST35, 32,   //0x2f64
++      ST36, 32,   //0x2f68
++      ST37, 32,   //0x2f6c
++      Offset (0x3350),  //port4
++      ST40, 32,   //0x3350
++      ST41, 32,   //0x3354
++      ST42, 32,   //0x3358
++      ST43, 32,   //0x335c
++      ST44, 32,   //0x3360
++      ST45, 32,   //0x3364
++      ST46, 32,   //0x3368
++      ST47, 32,   //0x336c
++      Offset (0x3750),//port5
++      ST50, 32,   //0x3750
++      ST51, 32,   //0x3754
++      ST52, 32,   //0x3758
++      ST53, 32,   //0x375c
++      ST54, 32,   //0x3760
++      ST55, 32,   //0x3764
++      ST56, 32,   //0x3768
++      ST57, 32,   //0x376c
++      Offset (0x3b50),  //port6
++      ST60, 32,   //0x3b50
++      ST61, 32,   //0x3b54
++      ST62, 32,   //0x3b58
++      ST63, 32,   //0x3b5c
++      ST64, 32,   //0x3b60
++      ST65, 32,   //0x3b64
++      ST66, 32,   //0x3b68
++      ST67, 32,   //0x3b6c
++      Offset (0x3f50),  //port7
++      ST70, 32,   //0x3f50
++      ST71, 32,   //0x3f54
++      ST72, 32,   //0x3f58
++      ST73, 32,   //0x3f5c
++      ST74, 32,   //0x3f60
++      ST75, 32,   //0x3f64
++      ST76, 32,   //0x3f68
++      ST77, 32    //0x3f6c
++    }
++
++    Method (_RST, 0x0, Serialized)
++    {
++      Store(0x7FFFFFF, RST)
++      Sleep(1)
++      Store(0x7FFFFFF, DRST)
++      Sleep(1)
++
++      //port0
++      Store (0x8D04, ST00)
++      Sleep(1)
++      Store (0x8D04, ST01)
++      Sleep(1)
++      Store (0x8D04, ST02)
++      Sleep(1)
++      Store (0x8D04, ST03)
++      Sleep(1)
++      Store (0x8D04, ST05)
++      Sleep(1)
++      Store (0x8D04, ST06)
++      Sleep(1)
++      Store (0x8D04, ST07)
++      Sleep(1)
++
++      //port1
++      Store (0x8D04, ST10)
++      Sleep(1)
++      Store (0x8D04, ST11)
++      Sleep(1)
++      Store (0x8D04, ST12)
++      Sleep(1)
++      Store (0x8D04, ST13)
++      Sleep(1)
++      Store (0x8D04, ST15)
++      Sleep(1)
++      Store (0x8D04, ST16)
++      Sleep(1)
++      Store (0x8D04, ST17)
++      Sleep(1)
++
++      //port2
++      Store (0x8D04, ST20)
++      Sleep(1)
++      Store (0x8D04, ST21)
++      Sleep(1)
++      Store (0x8D04, ST22)
++      Sleep(1)
++      Store (0x8D04, ST23)
++      Sleep(1)
++      Store (0x8D04, ST25)
++      Sleep(1)
++      Store (0x8D04, ST26)
++      Sleep(1)
++      Store (0x8D04, ST27)
++      Sleep(1)
++
++      //port3
++      Store (0x8D04, ST30)
++      Sleep(1)
++      Store (0x8D04, ST31)
++      Sleep(1)
++      Store (0x8D04, ST32)
++      Sleep(1)
++      Store (0x8D04, ST33)
++      Sleep(1)
++      Store (0x8D04, ST35)
++      Sleep(1)
++      Store (0x8D04, ST36)
++      Sleep(1)
++      Store (0x8D04, ST37)
++      Sleep(1)
++
++      //port4
++      Store (0x8D04, ST40)
++      Sleep(1)
++      Store (0x8D04, ST41)
++      Sleep(1)
++      Store (0x8D04, ST42)
++      Sleep(1)
++      Store (0x8D04, ST43)
++      Sleep(1)
++      Store (0x8D04, ST45)
++      Sleep(1)
++      Store (0x8D04, ST46)
++      Sleep(1)
++      Store (0x8D04, ST47)
++      Sleep(1)
++
++      //port5
++      Store (0x8D04, ST50)
++      Sleep(1)
++      Store (0x8D04, ST51)
++      Sleep(1)
++      Store (0x8D04, ST52)
++      Sleep(1)
++      Store (0x8D04, ST53)
++      Sleep(1)
++      Store (0x8D04, ST55)
++      Sleep(1)
++      Store (0x8D04, ST56)
++      Sleep(1)
++      Store (0x8D04, ST57)
++      Sleep(1)
++
++      //port6
++      Store (0x8D04, ST60)
++      Sleep(1)
++      Store (0x8D04, ST61)
++      Sleep(1)
++      Store (0x8D04, ST62)
++      Sleep(1)
++      Store (0x8D04, ST63)
++      Sleep(1)
++      Store (0x8D04, ST65)
++      Sleep(1)
++      Store (0x8D04, ST66)
++      Sleep(1)
++      Store (0x8D04, ST67)
++      Sleep(1)
++
++      //port7
++      Store (0x8D04, ST70)
++      Sleep(1)
++      Store (0x8D04, ST71)
++      Sleep(1)
++      Store (0x8D04, ST72)
++      Sleep(1)
++      Store (0x8D04, ST73)
++      Sleep(1)
++      Store (0x8D04, ST75)
++      Sleep(1)
++      Store (0x8D04, ST76)
++      Sleep(1)
++      Store (0x8D04, ST77)
++      Sleep(1)
++    }
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x01)
++  }
++}
++
++Device (PCI6)
++{                                            // PCI0 indicate host bridge 0
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 6)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0x80)                          // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++
++  Name (_PRT, Package (){
++    // INTx configure for RP0, whoes device number is 0
++    // For ESL/FPGA debug, we should modify this according to
++    // specific hardware configuration.
++    Package () {0xFFFF,0,0,640},         // INT_A
++    Package () {0xFFFF,1,0,641},         // INT_B
++    Package () {0xFFFF,2,0,642},         // INT_C
++    Package () {0xFFFF,3,0,643},         // INT_D
++
++    // This is an example of RP1 INTx configure. Adding or not
++    // adding RPx INTx configure deponds on hardware board topology,
++    // if UEFI enables RPx, RPy, RPz... related INTx configure
++    // should be added
++    Package () {0x04FFFF,0,0,640},         // INT_A
++    Package () {0x04FFFF,1,0,641},         // INT_B
++    Package () {0x04FFFF,2,0,642},         // INT_C
++    Package () {0x04FFFF,3,0,643},         // INT_D
++
++    Package () {0x08FFFF,0,0,640},         // INT_A
++    Package () {0x08FFFF,1,0,641},         // INT_B
++    Package () {0x08FFFF,2,0,642},         // INT_C
++    Package () {0x08FFFF,3,0,643},         // INT_D
++
++    Package () {0x0CFFFF,0,0,640},         // INT_A
++    Package () {0x0CFFFF,1,0,641},         // INT_B
++    Package () {0x0CFFFF,2,0,642},         // INT_C
++    Package () {0x0CFFFF,3,0,643},         // INT_D
++
++    Package () {0x10FFFF,0,0,640},         // INT_A
++    Package () {0x10FFFF,1,0,641},         // INT_B
++    Package () {0x10FFFF,2,0,642},         // INT_C
++    Package () {0x10FFFF,3,0,643},         // INT_D
++  })
++
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0x80,                              // AddressMinimum - Minimum Bus Number
++        0x9f,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x20                               // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit prefetch BAR windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x480000000000,                     // Min Base Address pci address
++        0x483fffffffff,                     // Max Base Address
++        0x0,                               // Translate
++        0x4000000000                       // Length, 256G
++      )
++      QWordMemory (                        // 32-bit non-prefetch BAR windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Cacheable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0xf0000000,                        // Min Base Address pci address
++        0xfffeffff,                        // Max Base Address
++        0x0,                               // Translate
++        0xfff0000                          // Length, 256M - 64K
++      )
++      QWordIO (
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        EntireRange,
++        0x0,                               // Granularity
++        0x0,                               // Min Base Address
++        0xffff,                            // Max Base Address
++        0xffff0000,                        // Translate
++        0x10000                            // Length, 64K
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  //
++  // OS Control Handoff
++  //
++  Name(SUPP, Zero) // PCI _OSC Support Field value
++  Name(CTRL, Zero) // PCI _OSC Control Field value
++
++  Method(_OSC,4) {
++    // Check for proper UUID
++    If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
++    // Create DWord-adressable fields from the Capabilities Buffer
++    CreateDWordField(Arg3,0,CDW1)
++    CreateDWordField(Arg3,4,CDW2)
++    CreateDWordField(Arg3,8,CDW3)
++
++    // Save Capabilities DWord2 & 3
++    Store(CDW2,SUPP)
++    Store(CDW3,CTRL)
++
++    // Only allow native hot plug control if OS supports:
++    //  ASPM
++    //  Clock PM
++    //  MSI/MSI-X
++    If(LNotEqual(And(SUPP, 0x16), 0x16)) {
++      And(CTRL,0x1E,CTRL) // Mask bit 0 (and undefined bits)
++    }
++
++    // Always allow native PME, AER (no dependencies)
++
++    // Never allow SHPC (no SHPC controller in this system)
++    And(CTRL,0x1D,CTRL)
++
++    If(LNotEqual(Arg1,One)) {  // Unknown revision
++      Or(CDW1,0x08,CDW1)
++    }
++
++    If(LNotEqual(CDW3,CTRL)) {  // Capabilities bits were masked
++      Or(CDW1,0x10,CDW1)
++    }
++
++    // Update DWORD3 in the buffer
++    Store(CTRL,CDW3)
++    Return(Arg3)
++    } Else {
++    Or(CDW1,4,CDW1) // Unrecognized UUID
++    Return(Arg3)
++    }
++  } // End _OSC
++
++  Method (_HPX, 0) {
++    Return (Package(2) {
++      Package(6) { // PCI Setting Record
++        0x00, // Type 0
++        0x01, // Revision 1
++        0x08, // CacheLineSize in DWORDS
++        0x40, // LatencyTimer in PCI clocks
++        0x01, // Enable SERR (Boolean)
++        0x01  // Enable PERR (Boolean)
++       },
++
++       Package(18){ // PCI-X Setting Record
++       0x02,      // Type 2
++       0x01,      // Revision 1
++       0xFFFFFFFF,  // Uncorrectable Error Mask Register AND Mask, Keep ->1
++       0x00000000,  // Uncorrectable Error Mask Register OR Mask, keep ->0
++       0xFFFFFFFF,  // Uncorrectable Error Severity Register AND Mask
++       0x00000000,  // Uncorrectable Error Severity Register OR Mask
++       0xFFFFFFFF,  // Correctable Error Mask Register AND Mask
++       0x00000000,  // Correctable Error Mask Register OR Mask
++       0xFFFFFFFF,  // Advanced Error Capabilities and Control Register AND Mask
++       0x00000000,  // Advanced Error Capabilities and Control Register OR Mask
++       0xFFF7,    // Device Control Register AND Mask
++       0x0007,    // Device Control Register OR Mask
++       0xFFFF,    // Link Control Register AND Mask
++       0x0000,    // Link Control Register OR Mask
++       0xFFFFFFFF,  // Secondary Uncorrectable Error Severity Register AND Mask
++       0x00000000,  // Secondary Uncorrectable Error Severity Register OR Mask
++       0xFFFFFFFF,  // Secondary Uncorrectable Error Mask Register AND Mask
++       0x00000000   // Secondary Uncorrectable Error Mask Register OR Mask
++     }
++   })
++ }
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++} // Device(PCI6)
++
++
++Device (PCI7)
++{                                          // PCI1 indicate host bridge 1
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 7)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0xbb)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0xbb,                              // AddressMinimum - Minimum Bus Number
++        0xbb,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x1                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows, where to show this ??
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x400148800000,                       // Min Base Address pci address ??
++        0x400148ffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x800000                           // Length, 8M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++} // Device(PCI7)
++
++Device (PCI8)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 8)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0xba)                         // Base Bus Number
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Name (_PRT, Package (){
++    Package () {0xFFFF,0,0,640},         // INT_A
++    Package () {0xFFFF,1,0,641},         // INT_B
++    Package () {0xFFFF,2,0,642},         // INT_C
++    Package () {0xFFFF,3,0,643},         // INT_D
++    Package () {0x1FFFF,0,0,640},         // INT_A
++    Package () {0x1FFFF,1,0,641},         // INT_B
++    Package () {0x1FFFF,2,0,642},         // INT_C
++    Package () {0x1FFFF,3,0,643},         // INT_D
++    Package () {0x2FFFF,0,0,640},         // INT_A
++    Package () {0x2FFFF,1,0,641},         // INT_B
++    Package () {0x2FFFF,2,0,642},         // INT_C
++    Package () {0x2FFFF,3,0,643},         // INT_D
++  })
++
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource //                               setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0xba,                              // AddressMinimum - Minimum Bus Number
++        0xba,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x1                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x40020c000000,                       // Min Base Address pci address
++        0x40020c1fffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x200000                           // Length, 2M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++}// Device(PCI8)
++
++Device (PCI9)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 9)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0xb8)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource //                               setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0xb8,                              // AddressMinimum - Minimum Bus Number
++        0xb9,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x2                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x400208000000,                       // Min Base Address pci address
++        0x400208ffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x1000000                          // Length, 16M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++}// Device(PCI9)
++
++Device (PCIA)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 0xA)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0xbc)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0xbc,                              // AddressMinimum - Minimum Bus Number
++        0xbd,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x2                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x400120000000,                       // Min Base Address pci address
++        0x40013fffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x20000000                         // Length, 512M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0x0F)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++}// Device(PCIA)
++
++Device (PCIB)
++{
++  Name (_HID, "PNP0A08")                   // PCI Express Root Bridge
++  Name (_UID, 0xB)
++  Name (_CID, "PNP0A03")                   // Compatible PCI Root Bridge, Compatible ID
++  Name(_SEG, 0)                            // Segment of this Root complex
++  Name(_BBN, 0xb4)                         // Base Bus Number ??
++  Name(_CCA, 1)                            // cache coherence attribute ??
++
++  Name (_PRT, Package (){
++    Package () {0x2FFFF,0,0,640},         // INT_A
++    Package () {0x2FFFF,1,0,641},         // INT_B
++    Package () {0x2FFFF,2,0,642},         // INT_C
++    Package () {0x2FFFF,3,0,643},         // INT_D
++    Package () {0x3FFFF,0,0,640},         // INT_A
++    Package () {0x3FFFF,1,0,641},         // INT_B
++    Package () {0x3FFFF,2,0,642},         // INT_C
++    Package () {0x3FFFF,3,0,643},         // INT_D
++  })
++
++  Method (_CRS, 0, Serialized) {           // Root complex resources, _CRS: current resource setting
++    Name (RBUF, ResourceTemplate () {      // Name: 19.6.87, ResourceTemplate: 19.6.111,
++      WordBusNumber (                      // Bus numbers assigned to this root,
++        ResourceProducer,
++        MinFixed,
++        MaxFixed,
++        PosDecode,
++        0,                                 // AddressGranularity
++        0xb4,                              // AddressMinimum - Minimum Bus Number
++        0xb6,                              // AddressMaximum - Maximum Bus Number
++        0,                                 // AddressTranslation - Set to 0
++        0x3                                // RangeLength - Number of Busses
++      )
++      QWordMemory (                        // 64-bit BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Prefetchable,
++        ReadWrite,
++        0x0,                               // Granularity
++        0x400144000000,                       // Min Base Address pci address
++        0x400147ffffff,                       // Max Base Address
++        0x0,                               // Translate
++        0x4000000                          // Length, 32M
++      )
++      QWordMemory (                        // 32-bit non-prefetch BAR Windows
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        Cacheable,
++        ReadWrite,
++        0x0,                                // Granularity
++        0xa3000000,                        // Min Base Address pci address
++        0xa3ffffff,                        // Max Base Address
++        0x0,                                // Translate
++        0x1000000                          // Length, 16M
++      )
++    })                                      // Name(RBUF)
++    Return (RBUF)
++  }                                         // Method(_CRS), this method return RBUF!
++
++  Method (_STA, 0x0, NotSerialized)
++  {
++    Return (0xf)
++  }
++
++  Method (_PXM, 0, NotSerialized)
++  {
++    Return(0x03)
++  }
++}
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl
+new file mode 100644
+index 0000000000..39553e01af
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Power.asl
+@@ -0,0 +1,28 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2016, Linaro Limited. All rights reserved.<BR>
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  Device(PWRB) {
++    Name(_HID, "PNP0C0C")
++    Name(_UID, Zero)
++    Method(_STA, 0x0, NotSerialized) {
++      Return(0xF)
++    }
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl
+new file mode 100644
+index 0000000000..1dcf1bba7e
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Rde.asl
+@@ -0,0 +1,47 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  Device(RDE0) {
++    Name(_HID, "HISI0201")
++    Name(_UID, 0)
++    Name(_CCA, 1)
++    Name (_CRS, ResourceTemplate ()  {
++      //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++      QWordMemory (
++        ResourceConsumer,
++        ,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0,
++        0x209000000,
++        0x209ffffff,
++        0x0,
++        0x01000000
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI2")
++      { 586,587,588,589,590,591,592,593,594,595,596,597,598,599,600,601,
++        602,603,604,605,606,607,608,609,610,611,612,613,614,615,616,617
++      }
++    })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl
+new file mode 100644
+index 0000000000..bba455468e
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Sec.asl
+@@ -0,0 +1,57 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  Device(SEC0) {
++    Name (_HID, "HISI0200")
++    Name(_UID, 0)
++    Name(_CCA, 1)
++    Name (_CRS, ResourceTemplate ()  {
++      //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++      QWordMemory (
++        ResourceConsumer,
++        ,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0,
++        0x141000000,
++        0x141ffffff,
++        0x0,
++        0x01000000
++      )
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MBI3")
++      {
++        624,625,626,627,628,629,630,631,632,633,634,635,636,637,638,639,
++        640,641,642,643,644,645,646,647,648,649,650,651,652,653,654,655
++      }
++    })
++  }
++
++  Device(SEC1) {
++    Name(_HID, "HISI0200")
++    Name(_UID, 1)
++    Name (_CRS, ResourceTemplate ()  {
++      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive)
++      { 466,467
++      }
++    })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl
+new file mode 100644
+index 0000000000..622355ade0
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c100k.asl
+@@ -0,0 +1,249 @@
++/** @file
++*
++*  Copyright (c) 2018 Hisilicon Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++//
++// GPIO
++//
++
++//#include "ArmPlatform.h"
++Scope(_SB)
++{
++Device(GPO0) {
++  Name(_HID, "HISI0181")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201120000,
++      0x20112ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      476,
++    }
++  })
++
++  Device(PRTa) {
++    Name(_ADR, 0)
++    Name(_UID, 0)
++    Name(_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"reg", 0},
++        Package () {"snps,nr-gpios", 32},
++      }
++    })
++  }
++}
++
++/**
++*I2C for 100k release
++**/
++Device(I2C0) {
++  Name(_HID, "HISI02A2")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 913},
++      Package () {"i2c-scl-falling-time-ns", 303},
++      Package () {"i2c-sda-hold-time-ns", 1000},
++      Package () {"clock-frequency", 100000},
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201160000,
++      0x20116ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      480,
++    }
++  })
++}
++
++
++/**
++*I2C for 100k vtof
++**/
++Device(I2C2) {
++  Name(_HID, "HISI0182")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 913},
++      Package () {"i2c-scl-falling-time-ns", 303},
++      Package () {"i2c-sda-hold-time-ns", 1000},
++      Package () {"clock-frequency", 100000},
++    }
++    })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201160000,
++      0x20116ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      480,
++    }
++  })
++}
++
++/**
++*I2C for 400k fpga
++**/
++Device(I2C3) {
++  Name(_HID, "HISI0183")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 300},
++      Package () {"i2c-scl-falling-time-ns", 100},
++      Package () {"i2c-sda-hold-time-ns", 250},
++      Package () {"clock-frequency", 400000},
++    }
++    })
++
++  Name (_CRS, ResourceTemplate ()  {
++  //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++  QWordMemory (
++    ResourceConsumer,
++    ,
++    MinFixed,
++    MaxFixed,
++    NonCacheable,
++    ReadWrite,
++    0x0,
++    0x201160000,
++    0x20116ffff,
++    0x0,
++    0x10000
++  )
++  Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++  {
++    480,
++  }
++  })
++}
++
++Device(LPC) {
++  Name(_HID, "HISI0191")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++  Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++  {
++    484,
++    490
++  }
++  })
++}
++
++Device(NAD) {
++  Name(_HID, "HISI0192")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_CCA, 1)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"nand-bus-width", 8},
++      Package () {"nand-ecc-mode", "hw"},
++      Package () {"nand-ecc-strength", 24},
++      Package () {"nand-ecc-step-size", 1024},
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x206220000,
++      0x20622ffff,
++      0x0,
++      0x10000
++    )
++
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x206210000,
++      0x20621ffff,
++      0x0,
++      0x10000
++    )
++
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      483,
++    }
++  })
++}
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl
+new file mode 100644
+index 0000000000..5db4284467
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Hi1620Socip4_i2c400k.asl
+@@ -0,0 +1,249 @@
++/** @file
++*
++*  Copyright (c) 2018 Hisilicon Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++//
++// GPIO
++//
++
++//#include "ArmPlatform.h"
++Scope(_SB)
++{
++  Device(GPO0) {
++  Name(_HID, "HISI0181")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201120000,
++      0x20112ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      476,
++    }
++  })
++
++  Device(PRTa) {
++    Name(_ADR, 0)
++    Name(_UID, 0)
++    Name(_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"reg", 0},
++        Package () {"snps,nr-gpios", 32},
++      }
++    })
++  }
++
++  }
++
++/**
++*I2C for 400k release
++**/
++Device(I2C1) {
++  Name(_HID, "HISI02A2")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 500},
++      Package () {"i2c-scl-falling-time-ns", 100},
++      Package () {"i2c-sda-hold-time-ns", 250},
++      Package () {"clock-frequency", 400000},
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201160000,
++      0x20116ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      480,
++    }
++  })
++}
++
++/**
++*I2C for 100k vtof
++**/
++Device(I2C2) {
++  Name(_HID, "HISI0182")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 913},
++      Package () {"i2c-scl-falling-time-ns", 303},
++      Package () {"i2c-sda-hold-time-ns", 1000},
++      Package () {"clock-frequency", 100000},
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201160000,
++      0x20116ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      480,
++    }
++  })
++}
++
++/**
++*I2C for 400k fpga
++**/
++Device(I2C3) {
++  Name(_HID, "HISI0183")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"i2c-sda-falling-time-ns", 300},
++      Package () {"i2c-scl-falling-time-ns", 100},
++      Package () {"i2c-sda-hold-time-ns", 250},
++      Package () {"clock-frequency", 400000},
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x201160000,
++      0x20116ffff,
++      0x0,
++      0x10000
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      480,
++    }
++  })
++}
++
++Device(LPC) {
++  Name(_HID, "HISI0191")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++    }
++  })
++
++  Name (_CRS, ResourceTemplate ()  {
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      484,
++      490
++    }
++  })
++}
++
++Device(NAD) {
++  Name(_HID, "HISI0192")
++  Name(_ADR, 0)
++  Name(_UID, 0)
++  Name(_CCA, 1)
++  Name(_DSD, Package () {
++    ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++    Package () {
++      Package () {"nand-bus-width", 8},
++      Package () {"nand-ecc-mode", "hw"},
++      Package () {"nand-ecc-strength", 24},
++      Package () {"nand-ecc-step-size", 1024},
++    }
++    })
++
++  Name (_CRS, ResourceTemplate ()  {
++    //Memory32Fixed (ReadWrite, 0x602E0000, 0x10000)
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x206220000,
++      0x20622ffff,
++      0x0,
++      0x10000
++    )
++
++    QWordMemory (
++      ResourceConsumer,
++      ,
++      MinFixed,
++      MaxFixed,
++      NonCacheable,
++      ReadWrite,
++      0x0,
++      0x206210000,
++      0x20621ffff,
++      0x0,
++      0x10000
++    )
++
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive,,,)
++    {
++      483,
++    }
++  })
++}
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl
+new file mode 100644
+index 0000000000..14e36353ad
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/LpcUart_clk.asl
+@@ -0,0 +1,49 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2014, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2015, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++  Device(UART) {
++    Name(_HID, "PNP0501")
++    Name(_UID, 0)
++    Name(_CCA, 1)
++    Name(_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"clock-frequency", 1843200},
++      }
++    })
++    Name(_CRS, ResourceTemplate() {
++      QWordMemory (
++        ResourceConsumer,
++        ,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0,
++        0x3f00003f8,
++        0x3f00003ff,
++        0x0,
++        0x8
++      )
++      Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 484 }
++    })
++  }
++}
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl
+new file mode 100644
+index 0000000000..65c3eccf0a
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/Pv680UncorePmu.asl
+@@ -0,0 +1,1658 @@
++/** @file
++  Differentiated System Description Table Fields (DSDT)
++
++  Copyright (c) 2017, ARM Ltd. All rights reserved.<BR>
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>
++    This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++
++**/
++
++Scope(_SB)
++{
++    // L3T0 for S0_TB(DieID:3)
++    Device (L300) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x90180000, // Min Base Address
++        0x9018FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB30")
++      {
++        832,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x00},
++      }
++    })
++
++  }
++  // L3T1 for S0_TB(DieID:3)
++  Device (L301) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 1) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x90190000, // Min Base Address
++        0x9019FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB31")
++      {
++        833,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x01},
++      }
++    })
++
++  }
++
++  // L3T2 for S0_TB(DieID:3)
++  Device (L302) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 2) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x901A0000, // Min Base Address
++        0x901AFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB32")
++      {
++        834,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x02},
++      }
++    })
++
++  }
++
++  // L3T3 for S0_TB(DieID:3)
++  Device (L303) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 3) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x901B0000, // Min Base Address
++        0x901BFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB33")
++      {
++        835,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x03},
++      }
++    })
++
++  }
++  // L3T4 for S0_TB(DieID:3)
++  Device (L304) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 4) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x901C0000, // Min Base Address
++        0x901CFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB34")
++      {
++        836,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x04},
++      }
++    })
++
++  }
++  // L3T5 for S0_TB(DieID:3)
++  Device (L305) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 5) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x901D0000, // Min Base Address
++        0x901DFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB35")
++      {
++        837,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ccl-id", 0x05},
++      }
++    })
++
++  }
++
++  // DDRC0 for S0_TB(DieID:3)
++  Device (DDR0) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x94D20000, // Min Base Address
++        0x94D2FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB38")
++      {
++        844,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ch-id", 0x0},
++      }
++    })
++
++  }
++  // DDRC1 for S0_TB(DieID:3)
++  Device (DDR1) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 1) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x94D30000, // Min Base Address
++        0x94D3FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB39")
++      {
++        845,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ch-id", 0x1},
++      }
++    })
++
++  }
++  // DDRC2 for S0_TB(DieID:3)
++  Device (DDR2) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 2) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x94D40000, // Min Base Address
++        0x94D4FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3A")
++      {
++        846,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ch-id", 0x2},
++      }
++    })
++
++  }
++  // DDRC3 for S0_TB(DieID:3)
++  Device (DDR3) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 3) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x94D50000, // Min Base Address
++        0x94D5FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3B")
++      {
++        847,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03},
++        Package () {"hisilicon,ch-id", 0x3},
++      }
++    })
++
++  }
++
++  // HHA0 for S0_TB(DieID:3)
++  Device (HHA0) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 0)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x90120000, // Min Base Address
++        0x9012FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3C")
++      {
++        848,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03}
++      }
++    })
++  }
++
++  // HHA1 for S0_TB(DieID:3)
++  Device (HHA1) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 1)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x90130000, // Min Base Address
++        0x9013FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++    Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB3D")
++    {
++      849,
++    }
++  })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x03}
++      }
++    })
++  }
++
++  // L3T0 for S0_TA(DieID:1)
++  Device (L308) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x08) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x98180000, // Min Base Address
++        0x9818FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB10")
++      {
++        832,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x00},
++      }
++    })
++
++  }
++  // L3T1 for S0_TA(DieID:1)
++  Device (L309) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x09) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x98190000, // Min Base Address
++        0x9819FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB11")
++      {
++        833,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x01},
++      }
++    })
++
++  }
++
++  // L3T2 for S0_TA(DieID:1)
++  Device (L30A) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x0A) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x981A0000, // Min Base Address
++        0x981AFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB12")
++      {
++        834,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x02},
++      }
++    })
++
++  }
++
++  // L3T3 for S0_TA(DieID:1)
++  Device (L30B) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x0B) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x981B0000, // Min Base Address
++        0x981BFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB13")
++      {
++        835,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x03},
++      }
++    })
++
++  }
++  // L3T4 for S0_TA(DieID:1)
++  Device (L30C) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x0C) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x981C0000, // Min Base Address
++        0x981CFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB14")
++      {
++        836,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x04},
++      }
++    })
++
++  }
++  // L3T5 for S0_TA(DieID:1)
++  Device (L30D) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x0D) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x981D0000, // Min Base Address
++        0x981DFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB15")
++      {
++        837,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ccl-id", 0x05},
++      }
++    })
++
++  }
++
++  // DDRC0 for S0_TA(DieID:1)
++  Device (DDR4) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 4) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x9CD20000, // Min Base Address
++        0x9CD2FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB18")
++      {
++        844,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ch-id", 0x0},
++      }
++    })
++
++  }
++  // DDRC1 for S0_TA(DieID:1)
++  Device (DDR5) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 5) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x9CD30000, // Min Base Address
++        0x9CD3FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB19")
++      {
++        845,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ch-id", 0x1},
++      }
++    })
++
++  }
++  // DDRC2 for S0_TA(DieID:1)
++  Device (DDR6) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 6) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x9CD40000, // Min Base Address
++        0x9CD4FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1A")
++      {
++        846,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ch-id", 0x2},
++      }
++    })
++
++  }
++  // DDRC3 for S0_TA(DieID:1)
++  Device (DDR7) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 7) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x9CD50000, // Min Base Address
++        0x9CD5FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1B")
++      {
++        847,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01},
++        Package () {"hisilicon,ch-id", 0x3},
++      }
++    })
++  }
++
++  // HHA0 for S0_TA(DieID:1)
++  Device (HHA2) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 2)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x98120000, // Min Base Address
++        0x9812FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1C")
++      {
++        848,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01}
++      }
++    })
++  }
++
++  // HHA1 for S0_TA(DieID:1)
++  Device (HHA3) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 3)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x98130000, // Min Base Address
++        0x9813FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++    Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB1D")
++    {
++      849,
++    }
++  })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x01}
++      }
++    })
++  }
++
++  // It is the list PMU node of Socket1
++  // L3T0 for S1_TB(DieID:7)
++    Device (L310) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x10) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400090180000, // Min Base Address
++        0x40009018FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB70")
++      {
++        832,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x00},
++      }
++    })
++
++  }
++  // L3T1 for S1_TB(DieID:7)
++  Device (L311) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x11) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400090190000, // Min Base Address
++        0x40009019FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB71")
++      {
++        833,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x01},
++      }
++    })
++
++  }
++
++  // L3T2 for S1_TB(DieID:7)
++  Device (L312) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x12) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000901A0000, // Min Base Address
++        0x4000901AFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB72")
++      {
++        834,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x02},
++      }
++    })
++
++  }
++
++  // L3T3 for S1_TB(DieID:7)
++  Device (L313) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x13) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000901B0000, // Min Base Address
++        0x4000901BFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB73")
++      {
++        835,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x03},
++      }
++    })
++
++  }
++  // L3T4 for S1_TB(DieID:7)
++  Device (L314) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x14) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000901C0000, // Min Base Address
++        0x4000901CFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB74")
++      {
++        836,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x04},
++      }
++    })
++
++  }
++  // L3T5 for S1_TB(DieID:7)
++  Device (L315) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x15) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000901D0000, // Min Base Address
++        0x4000901DFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB75")
++      {
++        837,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ccl-id", 0x05},
++      }
++    })
++
++  }
++
++  // DDRC0 for S1_TB(DieID:7)
++  Device (DDR8) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 8) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400094D20000, // Min Base Address
++        0x400094D2FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB78")
++      {
++        844,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ch-id", 0x0},
++      }
++    })
++
++  }
++  // DDRC1 for S1_TB(DieID:7)
++  Device (DDR9) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 9) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400094D30000, // Min Base Address
++        0x400094D3FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB79")
++      {
++        845,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ch-id", 0x1},
++      }
++    })
++
++  }
++  // DDRC2 for S1_TB(DieID:7)
++  Device (DDRA) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xA) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400094D40000, // Min Base Address
++        0x400094D4FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7A")
++      {
++        846,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ch-id", 0x2},
++      }
++    })
++
++  }
++  // DDRC3 for S1_TB(DieID:7)
++  Device (DDRB) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xB) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // DDRC address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400094D50000, // Min Base Address
++        0x400094D5FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7B")
++      {
++        847,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07},
++        Package () {"hisilicon,ch-id", 0x3},
++      }
++    })
++
++  }
++
++  // HHA0 for S1_TB(DieID:7)
++  Device (HHA4) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 4)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400090120000, // Min Base Address
++        0x40009012FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7C")
++      {
++        848,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07}
++      }
++    })
++  }
++
++  // HHA1 for S1_TB(DieID:7)
++  Device (HHA5) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 5)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400090130000, // Min Base Address
++        0x40009013FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++    Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB7D")
++    {
++      849,
++    }
++  })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x07}
++      }
++    })
++  }
++
++  // L3T0 for S1_TA(DieID:5)
++  Device (L318) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x18) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400098180000, // Min Base Address
++        0x40009818FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB50")
++      {
++        832,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x00},
++      }
++    })
++
++  }
++  // L3T1 for S1_TA(DieID:5)
++  Device (L319) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x19) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400098190000, // Min Base Address
++        0x40009819FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB51")
++      {
++        833,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x01},
++      }
++    })
++
++  }
++
++  // L3T2 for S1_TA(DieID:5)
++  Device (L31A) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x1A) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000981A0000, // Min Base Address
++        0x4000981AFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB52")
++      {
++        834,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x02},
++      }
++    })
++
++  }
++
++  // L3T3 for S1_TA(DieID:5)
++  Device (L31B) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x1B) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000981B0000, // Min Base Address
++        0x4000981BFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB53")
++      {
++        835,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x03},
++      }
++    })
++
++  }
++  // L3T4 for S1_TA(DieID:5)
++  Device (L31C) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x1C) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000981C0000, // Min Base Address
++        0x4000981CFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB54")
++      {
++        836,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x04},
++      }
++    })
++
++  }
++  // L3T5 for S1_TA(DieID:5)
++  Device (L31D) {
++    Name (_HID, "HISI0213") // _HID: Hardware ID
++    Name (_UID, 0x1D) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x4000981D0000, // Min Base Address
++        0x4000981DFFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB55")
++      {
++        837,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ccl-id", 0x05},
++      }
++    })
++
++  }
++
++  // DDRC0 for S1_TA(DieID:5)
++  Device (DDRC) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xC) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x40009CD20000, // Min Base Address
++        0x40009CD2FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB58")
++      {
++        844,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ch-id", 0x0},
++      }
++    })
++
++  }
++  // DDRC1 for S1_TA(DieID:5)
++  Device (DDRD) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xD) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x40009CD30000, // Min Base Address
++        0x40009CD3FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB59")
++      {
++        845,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ch-id", 0x1},
++      }
++    })
++
++  }
++  // DDRC2 for S1_TA(DieID:5)
++  Device (DDRE) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xE) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x40009CD40000, // Min Base Address
++        0x40009CD4FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5A")
++      {
++        846,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ch-id", 0x2},
++      }
++    })
++
++  }
++  // DDRC3 for S1_TA(DieID:5)
++  Device (DDRF) {
++    Name (_HID, "HISI0233") // _HID: Hardware ID
++    Name (_UID, 0xF) // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // L3T address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x40009CD50000, // Min Base Address
++        0x40009CD5FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5B")
++      {
++        847,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05},
++        Package () {"hisilicon,ch-id", 0x3},
++      }
++    })
++  }
++
++    // HHA0 for S1_TA(DieID:5)
++  Device (HHA6) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 6)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400098120000, // Min Base Address
++        0x40009812FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++      Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5C")
++      {
++        848,
++      }
++    })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05}
++      }
++    })
++  }
++  // HHA1 for S0_TA(DieID:5)
++  Device (HHA7) {
++    Name (_HID, "HISI0243")  // _HID: Hardware ID
++    Name (_UID, 7)  // _UID: Unique ID
++    Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++      QWordMemory ( // HHA address base
++        ResourceProducer,
++        PosDecode,
++        MinFixed,
++        MaxFixed,
++        NonCacheable,
++        ReadWrite,
++        0x0, // Granularity
++        0x400098130000, // Min Base Address
++        0x40009813FFFF, // Max Base Address
++        0x0, // Translate
++        0x10000 // Length
++      )
++
++    Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, 0, "\\_SB.MB5D")
++    {
++      849,
++    }
++  })
++
++    Name (_DSD, Package () {
++      ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"),
++      Package () {
++        Package () {"hisilicon,scl-id", 0x05}
++      }
++    })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl
+new file mode 100644
+index 0000000000..555fe39936
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Dsdt/ipmi.asl
+@@ -0,0 +1,49 @@
++/** @file
++*
++*  Copyright (c) 2018 Hisilicon Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++//
++// LPC
++//
++
++Scope(_SB) {
++  Device (IPI0) {
++  Name (_HID, "IPI0001")
++  Name (_UID, 0)
++  Name (_STR, Unicode("IPMI_BT"))
++  Name(_CCA, 1)
++  //Name (_CID, "IPI0001")
++  Method (_IFT) {
++    Return (0x03)
++  }
++  Method (_SRV) {
++    Return (0x0200)   // IPMI Spec Revision 2.0
++  }
++  Name (_CRS, ResourceTemplate () { // _CRS: Current Resource Settings
++    QWordMemory ( // BMC memory region
++      ResourceConsumer,
++      PosDecode,
++      MinFixed,
++      MaxFixed,
++      Cacheable,
++      ReadWrite,
++      0x0, // Granularity
++      0x3f00000e4, // Min Base Address
++      0x3f00000e7, // Max Base Address
++      0x0, // Translate
++      0x4 // Length
++    )
++    Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 484 }
++  })
++  }
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc
+new file mode 100644
+index 0000000000..9e57936b85
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Facs.aslc
+@@ -0,0 +1,67 @@
++/** @file
++*  Firmware ACPI Control Structure (FACS)
++*
++*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++#include <IndustryStandard/Acpi.h>
++
++EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE Facs = {
++  EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_SIGNATURE, // UINT32  Signature
++  sizeof (EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE),  // UINT32  Length
++  0xA152,                                                 // UINT32  HardwareSignature
++  0,                                                      // UINT32  FirmwareWakingVector
++  0,                                                      // UINT32  GlobalLock
++  0,                                                      // UINT32  Flags
++  0,                                                      // UINT64  XFirmwareWakingVector
++  EFI_ACPI_6_2_FIRMWARE_ACPI_CONTROL_STRUCTURE_VERSION,   // UINT8   Version;
++    { EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved0[0]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved0[1]
++      EFI_ACPI_RESERVED_BYTE },                           // UINT8   Reserved0[2]
++  0,                                                      // UINT32  OspmFlags  "Platform firmware must
++                                                          //                    initialize this field to zero."
++    { EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[0]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[1]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[2]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[3]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[4]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[5]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[6]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[7]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[8]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[9]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[10]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[11]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[12]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[13]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[14]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[15]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[16]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[17]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[18]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[19]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[20]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[21]
++      EFI_ACPI_RESERVED_BYTE,                             // UINT8   Reserved1[22]
++      EFI_ACPI_RESERVED_BYTE },                           // UINT8   Reserved1[23]
++};
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Facs;
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc
+new file mode 100644
+index 0000000000..e7ee6981ec
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Fadt.aslc
+@@ -0,0 +1,91 @@
++/** @file
++*  Fixed ACPI Description Table (FADT)
++*
++*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++#include "Hi1620Platform.h"
++
++#include <Library/AcpiLib.h>
++#include <IndustryStandard/Acpi.h>
++
++EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
++  ARM_ACPI_HEADER (
++    EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
++    EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE,
++    EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
++  ),
++  0,                                                                        // UINT32     FirmwareCtrl
++  0,                                                                        // UINT32     Dsdt
++  EFI_ACPI_RESERVED_BYTE,                                                   // UINT8      Reserved0
++  EFI_ACPI_6_2_PM_PROFILE_UNSPECIFIED,                                      // UINT8      PreferredPmProfile
++  0,                                                                        // UINT16     SciInt
++  0,                                                                        // UINT32     SmiCmd
++  0,                                                                        // UINT8      AcpiEnable
++  0,                                                                        // UINT8      AcpiDisable
++  0,                                                                        // UINT8      S4BiosReq
++  0,                                                                        // UINT8      PstateCnt
++  0,                                                                        // UINT32     Pm1aEvtBlk
++  0,                                                                        // UINT32     Pm1bEvtBlk
++  0,                                                                        // UINT32     Pm1aCntBlk
++  0,                                                                        // UINT32     Pm1bCntBlk
++  0,                                                                        // UINT32     Pm2CntBlk
++  0,                                                                        // UINT32     PmTmrBlk
++  0,                                                                        // UINT32     Gpe0Blk
++  0,                                                                        // UINT32     Gpe1Blk
++  0,                                                                        // UINT8      Pm1EvtLen
++  0,                                                                        // UINT8      Pm1CntLen
++  0,                                                                        // UINT8      Pm2CntLen
++  0,                                                                        // UINT8      PmTmrLen
++  0,                                                                        // UINT8      Gpe0BlkLen
++  0,                                                                        // UINT8      Gpe1BlkLen
++  0,                                                                        // UINT8      Gpe1Base
++  0,                                                                        // UINT8      CstCnt
++  0,                                                                        // UINT16     PLvl2Lat
++  0,                                                                        // UINT16     PLvl3Lat
++  0,                                                                        // UINT16     FlushSize
++  0,                                                                        // UINT16     FlushStride
++  0,                                                                        // UINT8      DutyOffset
++  0,                                                                        // UINT8      DutyWidth
++  0,                                                                        // UINT8      DayAlrm
++  0,                                                                        // UINT8      MonAlrm
++  0,                                                                        // UINT8      Century
++  0,                                                                        // UINT16     IaPcBootArch
++  0,                                                                        // UINT8      Reserved1
++  EFI_ACPI_6_2_HW_REDUCED_ACPI | EFI_ACPI_6_2_LOW_POWER_S0_IDLE_CAPABLE,    // UINT32     Flags
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  ResetReg
++  0,                                                                        // UINT8      ResetValue
++  EFI_ACPI_6_2_ARM_PSCI_COMPLIANT,                                          // UINT16     ArmBootArchFlags
++  EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION,                 // UINT8      MinorRevision
++  0,                                                                        // UINT64     XFirmwareCtrl
++  0,                                                                        // UINT64     XDsdt
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1aEvtBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1bEvtBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1aCntBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm1bCntBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPm2CntBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XPmTmrBlk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XGpe0Blk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  XGpe1Blk
++  NULL_GAS,                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  SleepControlReg
++  NULL_GAS                                                                 // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  SleepStatusReg
++};
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Fadt;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc
+new file mode 100644
+index 0000000000..45f5d20704
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Gtdt.aslc
+@@ -0,0 +1,86 @@
++/** @file
++*  Generic Timer Description Table (GTDT)
++*
++*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++#include "Hi1620Platform.h"
++
++#include <Library/AcpiLib.h>
++#include <Library/PcdLib.h>
++#include <IndustryStandard/Acpi.h>
++
++#define GTDT_TIMER_EDGE_TRIGGERED   EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
++#define GTDT_TIMER_LEVEL_TRIGGERED  0
++#define GTDT_TIMER_ACTIVE_LOW       EFI_ACPI_6_2_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
++#define GTDT_TIMER_ACTIVE_HIGH      0
++#define SYSTEM_TIMER_BASE_ADDRESS     0xFFFFFFFFFFFFFFFF
++
++#define GTDT_GTIMER_FLAGS           (GTDT_TIMER_ACTIVE_LOW | GTDT_TIMER_LEVEL_TRIGGERED)
++
++#pragma pack (1)
++
++typedef struct {
++  EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE          Gtdt;
++  EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE     Watchdogs[HI1620_WATCHDOG_COUNT];
++} EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES;
++
++#pragma pack ()
++
++EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
++  {
++    ARM_ACPI_HEADER(
++      EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
++      EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE,
++      EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
++    ),
++    SYSTEM_TIMER_BASE_ADDRESS,                    // UINT64  PhysicalAddress
++    0,                                            // UINT32  Reserved
++    FixedPcdGet32 (PcdArmArchTimerSecIntrNum),    // UINT32  SecurePL1TimerGSIV
++    GTDT_GTIMER_FLAGS,                            // UINT32  SecurePL1TimerFlags
++    FixedPcdGet32 (PcdArmArchTimerIntrNum),       // UINT32  NonSecurePL1TimerGSIV
++    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL1TimerFlags
++    FixedPcdGet32 (PcdArmArchTimerVirtIntrNum),   // UINT32  VirtualTimerGSIV
++    GTDT_GTIMER_FLAGS,                            // UINT32  VirtualTimerFlags
++    FixedPcdGet32 (PcdArmArchTimerHypIntrNum),    // UINT32  NonSecurePL2TimerGSIV
++    GTDT_GTIMER_FLAGS,                            // UINT32  NonSecurePL2TimerFlags
++    0xFFFFFFFFFFFFFFFF,                           // UINT64  CntReadBasePhysicalAddress
++#ifdef notyet
++    PV660_WATCHDOG_COUNT,                          // UINT32  PlatformTimerCount
++    sizeof (EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
++  },
++  {
++    {
++      EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE),
++      EFI_ACPI_RESERVED_BYTE, 0, 0, 0, 0
++    },
++    {
++      EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG, sizeof(EFI_ACPI_6_2_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE),
++      EFI_ACPI_RESERVED_BYTE, 0, 0, 0, 0
++    }
++  }
++#else /* !notyet */
++  0, 0
++  }
++#endif
++  };
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Gtdt;
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc
+new file mode 100644
+index 0000000000..342ec33629
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Dbg2.aslc
+@@ -0,0 +1,86 @@
++/*
++ * Copyright (c) 2018 Linaro Limited
++ * Copyright (c) 2018 Hisilicon Limited
++ *
++ * All rights reserved. This program and the accompanying materials
++ * are made available under the terms of the BSD License which accompanies
++ * this distribution, and is available at
++ * http://opensource.org/licenses/bsd-license.php
++ *
++*/
++
++#include <IndustryStandard/Acpi.h>
++#include <IndustryStandard/DebugPort2Table.h>
++#include <Library/AcpiLib.h>
++#include <Library/PcdLib.h>
++#include "Hi1620Platform.h"
++
++#define NUMBER_DEBUG_DEVICE_INFO    1
++#define NUMBER_OF_GENERIC_ADDRESS   1
++#define NAMESPACE_STRING_SIZE       8
++#define UART_LENGTH                 0x1000
++
++#pragma pack(1)
++
++typedef struct {
++  EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT DdiHeader;
++  EFI_ACPI_6_1_GENERIC_ADDRESS_STRUCTURE Address[NUMBER_OF_GENERIC_ADDRESS];
++  UINT32 AddressSize[NUMBER_OF_GENERIC_ADDRESS];
++  CHAR8  NamespaceString[NAMESPACE_STRING_SIZE];
++} EFI_ACPI_DBG2_DDI_STRUCT;
++
++typedef struct {
++  EFI_ACPI_DEBUG_PORT_2_DESCRIPTION_TABLE Desc;
++  EFI_ACPI_DBG2_DDI_STRUCT Ddi[NUMBER_DEBUG_DEVICE_INFO];
++} EFI_ACPI_DEBUG_PORT_2_TABLE;
++
++#pragma pack()
++
++EFI_ACPI_DEBUG_PORT_2_TABLE Dbg2 = {
++  {
++    ARM_ACPI_HEADER(
++      EFI_ACPI_6_1_DEBUG_PORT_2_TABLE_SIGNATURE,
++      EFI_ACPI_DEBUG_PORT_2_TABLE,
++      EFI_ACPI_DEBUG_PORT_2_TABLE_REVISION
++      ),
++    OFFSET_OF(EFI_ACPI_DEBUG_PORT_2_TABLE, Ddi),
++    NUMBER_DEBUG_DEVICE_INFO
++  },
++  {
++    {
++      {
++        EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
++        sizeof(EFI_ACPI_DBG2_DDI_STRUCT),
++        NUMBER_OF_GENERIC_ADDRESS,
++        NAMESPACE_STRING_SIZE,
++        OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, NamespaceString),
++        0,  //OemDataLength
++        0,  //OemDataOffset
++        EFI_ACPI_DBG2_PORT_TYPE_SERIAL,
++         EFI_ACPI_DBG2_PORT_SUBTYPE_SERIAL_ARM_PL011_UART,
++        {EFI_ACPI_RESERVED_BYTE, EFI_ACPI_RESERVED_BYTE},
++        OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, Address),
++        OFFSET_OF(EFI_ACPI_DBG2_DDI_STRUCT, AddressSize),
++      },
++      {
++        {
++          EFI_ACPI_6_1_SYSTEM_MEMORY,
++          32,
++          0,
++          EFI_ACPI_6_1_BYTE,
++          FixedPcdGet64 (PcdSerialDbgRegisterBase)
++        }
++      },
++      {
++        UART_LENGTH
++      },
++      "COM1"
++    }
++  }
++};
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Dbg2;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
+new file mode 100644
+index 0000000000..33b5d5250b
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Iort.asl
+@@ -0,0 +1,1989 @@
++/*
++ * Intel ACPI Component Architecture
++ * iASL Compiler/Disassembler version 20151124-64
++ * Copyright (c) 2000 - 2015 Intel Corporation
++ *
++ * Template for [IORT] ACPI Table (static data table)
++ * Format: [ByteLength]  FieldName : HexFieldValue
++ */
++[0004]                          Signature : "IORT"    [IO Remapping Table]
++[0004]                       Table Length : 01c8
++[0001]                           Revision : 00
++[0001]                           Checksum : BC
++[0006]                             Oem ID : "HISI  "            // ?
++[0008]                       Oem Table ID : "HIP08   "          // ?
++[0004]                       Oem Revision : 00000000            // ?
++[0004]                    Asl Compiler ID : "INTL"
++[0004]              Asl Compiler Revision : 20150410
++
++[0004]                         Node Count : 00000005           // ITS, SMMU and RC
++[0004]                        Node Offset : 00000034           // ?
++[0004]                           Reserved : 00000000
++[0004]                   Optional Padding : 00 00 00 00
++
++/* 0x34 ITS, for PCIe */
++/* Here we use the P680/Hi1620 ACPI table which includes MADT table to help to debuge */
++[0001]                               Type : 00
++[0002]                             Length : 0018
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000000           // ?
++[0004]                     Mapping Offset : 00000000           // ?
++
++[0004]                           ItsCount : 00000001           // ?
++[0004]                        Identifiers : 00000000           // how to refer to MADT ?
++
++/* 0x4c SMMU for PCIe host bridge 0 and 1 */
++[0001]                               Type : 04
++[0002]                             Length : 0080
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000003
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 148000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 01
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 00000002
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00004000
++[0004]                        Output Base : 00000000
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00007b00
++[0004]                           ID Count : 00000100
++[0004]                        Output Base : 00007b00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F01
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* 0xCC SMMU for PCIe host bridge 4 */
++[0001]                               Type : 04
++[0002]                             Length : 006C
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 100000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 01
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 0001
++
++[0004]                         Input base : 00007c00
++[0004]                           ID Count : 00000200
++[0004]                        Output Base : 00007c00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F03
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* 0x138 */
++/* SMMU for PCIe host bridge 5 */
++[0001]                               Type : 04
++[0002]                             Length : 006C
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 140000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 01
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 00000001
++
++[0004]                         Input base : 00007400
++[0004]                           ID Count : 00000300
++[0004]                        Output Base : 00007400
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F04
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++// Here for Chip1 SMMU settings
++/* 0x1A4 SMMU for PCIe host bridge 6 and 7 */
++[0001]                               Type : 04
++[0002]                             Length : 0080
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000003
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 400148000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 03
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 00000002
++
++[0004]                         Input base : 00008000
++[0004]                           ID Count : 00002000
++[0004]                        Output Base : 00008000
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 0000bb00
++[0004]                           ID Count : 00000100
++[0004]                        Output Base : 0000bb00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF01
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* 0x224 SMMU for PCIe host bridge 10 */
++[0001]                               Type : 04
++[0002]                             Length : 006C
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 400100000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 03
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 0001
++
++[0004]                         Input base : 0000BC00
++[0004]                           ID Count : 00000200
++[0004]                        Output Base : 0000BC00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF03
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* 0x290*/
++/* SMMU for PCIe host bridge 11 */
++[0001]                               Type : 04
++[0002]                             Length : 006C
++[0001]                           Revision : 01
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000044
++
++[0008]                       Base Address : 400140000000
++[0004]              Flags (decoded below) : 00000009
++                          COHACC Override : 1
++                            HTTU Override : 0
++                   Proximity Domain Valid : 1
++[0004]                           Reserved : 00000000
++[0008]                      VATOS Address : 0
++[0004]                              Model : 00000000
++[0004]                    Event Interrupt : 00000000
++[0004]                      PRI Interrupt : 00000000
++[0004]                     GERR Interrupt : 00000000
++[0004]                     Sync Interrupt : 00000000
++[0001]                   Proximity Domain : 03
++[0001]                           Reserved : 00
++[0002]                           Reserved : 0000
++[0004]             DeviceID mapping index : 00000001
++
++[0004]                         Input base : 0000B400
++[0004]                           ID Count : 00000300
++[0004]                        Output Base : 0000B400
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++[0004]                         Input base : 00000000   //single mapping will ignore input base
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF04
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/*0x2FC RC 0 */
++[0001]                               Type : 02
++[0002]                             Length : 00A0
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 0000000C
++[0004]                     Mapping Offset : 00000028
++
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000001
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0004]                      ATS Attribute : 00000000
++[0004]                 PCI Segment Number : 00000000           // should match with above MCFG
++
++/* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00004000          // the number of IDs in range
++[0004]                        Output Base : 00000000
++[0004]                   Output Reference : 0000004c
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 1 -> stream ID of pcie 0/1 SMMU */
++[0004]                         Input base : 00007b00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 00007b00
++[0004]                   Output Reference : 0000004c
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* host2 and host3 should no open smmu for chips smmu bug *
++/* BDF of pcie host 2 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 00007a00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 00007a00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 3 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 00007800
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 00007800
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 4 -> stream ID of pcie 4 SMMU */
++[0004]                         Input base : 00007c00
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 00007c00
++[0004]                   Output Reference : 000000cc
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 5 -> stream ID of pcie 5 SMMU */
++[0004]                         Input base : 00007400
++[0004]                           ID Count : 00000300          // the number of IDs in range
++[0004]                        Output Base : 00007400
++[0004]                   Output Reference : 00000138
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 6 -> stream ID of pcie 6/7 SMMU */
++[0004]                         Input base : 00008000
++[0004]                           ID Count : 00002000          // the number of IDs in range
++[0004]                        Output Base : 00008000
++[0004]                   Output Reference : 000001A4
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 7 -> stream ID of pcie 6/7 SMMU */
++[0004]                         Input base : 0000BB00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 0000BB00
++[0004]                   Output Reference : 000001A4
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* host8 and host9 should no open smmu for chips smmu bug *
++/* BDF of pcie host 8 -> stream ID of pcie ITS */
++[0004]                         Input base : 0000BA00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 0000BA00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 9 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 0000B800
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 0000B800
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 10 -> stream ID of pcie 10 SMMU */
++[0004]                         Input base : 0000BC00
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 0000BC00
++[0004]                   Output Reference : 00000224
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* BDF of pcie host 11 -> stream ID of pcie 11 SMMU */
++[0004]                         Input base : 0000B400
++[0004]                           ID Count : 00000300          // the number of IDs in range
++[0004]                        Output Base : 0000B400
++[0004]                   Output Reference : 00000290
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB30"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD1 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB31"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD2 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB32"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD3 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB33"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD4 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB34"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD5 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB35"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD6 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB38"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDD // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB39"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDE // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDF // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC7 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC8 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC9 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB10"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F51 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB11"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F52 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB12"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F53 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB13"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F54 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB14"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F55 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB15"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F56 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB18"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5D // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB19"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5E // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5F // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F47 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F48 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F49 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB70"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD1 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB71"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD2 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB72"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD3 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB73"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD4 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB74"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD5 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB75"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD6 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB78"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDD // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB79"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDE // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDF // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC7 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC8 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC9 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB50"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF51 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB51"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF52 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB52"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF53 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB53"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF54 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB54"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF55 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB55"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF56 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB58"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5D // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB59"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5E // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5F // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF47 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF48 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF49 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++
++[320h 0800   1]                         Type : 01
++[321h 0801   2]                       Length : 0054
++[323h 0803   1]                     Revision : 00
++[324h 0804   4]                     Reserved : 00000000
++[328h 0808   4]                Mapping Count : 00000001
++[32Ch 0812   4]               Mapping Offset : 00000040
++
++[330h 0816   4]                   Node Flags : 00000000
++[334h 0820   8]            Memory Properties : [IORT Memory Access Properties]
++[334h 0820   4]              Cache Coherency : 00000000
++[338h 0824   1]        Hints (decoded below) : 00
++                                   Transient : 0
++                              Write Allocate : 0
++                               Read Allocate : 0
++                                    Override : 0
++[339h 0825   2]                     Reserved : 0000
++[33Bh 0827   1] Memory Flags (decoded below) : 00
++                                   Coherency : 0
++                            Device Attribute : 0
++[33Ch 0828   1]            Memory Size Limit : 00
++[33Dh 0829  11]                  Device Name : "\_SB_.SEC0"
++[348h 0840  24]                      Padding : \
++    00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \
++    4C 00 00 00 01 00 00 00
++
++[34Ch 0844   4]                   Input base : 00000000
++[350h 0848   4]                     ID Count : 00000001
++[354h 0852   4]                  Output Base : 00000100
++[358h 0856   4]             Output Reference : 00000100
++[35Ch 0860   4]        Flags (decoded below) : 00000001
++                              Single Mapping : 1
++/* RDE device report++.*/
++[320h 0800   1]                         Type : 01
++[321h 0801   2]                       Length : 0054
++[323h 0803   1]                     Revision : 00
++[324h 0804   4]                     Reserved : 00000000
++[328h 0808   4]                Mapping Count : 00000001
++[32Ch 0812   4]               Mapping Offset : 00000040
++
++[330h 0816   4]                   Node Flags : 00000000
++[334h 0820   8]            Memory Properties : [IORT Memory Access Properties]
++[334h 0820   4]              Cache Coherency : 00000000
++[338h 0824   1]        Hints (decoded below) : 00
++                                   Transient : 0
++                              Write Allocate : 0
++                               Read Allocate : 0
++                                    Override : 0
++[339h 0825   2]                     Reserved : 0000
++[33Bh 0827   1] Memory Flags (decoded below) : 00
++                                   Coherency : 0
++                            Device Attribute : 0
++[33Ch 0828   1]            Memory Size Limit : 00
++[33Dh 0829  11]                  Device Name : "\_SB_.RDE0"
++[348h 0840  24]                      Padding : \
++    00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \
++    4C 00 00 00 01 00 00 00
++
++[34Ch 0844   4]                   Input base : 00000000
++[350h 0848   4]                     ID Count : 00000001
++[354h 0852   4]                  Output Base : 00007f13
++[358h 0856   4]             Output Reference : 00000034
++[35Ch 0860   4]        Flags (decoded below) : 00000001
++                              Single Mapping : 1
++
++/* mbi-gen for MCTP, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MBI4"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F18 // MCTP device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
+new file mode 100644
+index 0000000000..63d11b83eb
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620IortNoSmmu.asl
+@@ -0,0 +1,1736 @@
++/*
++ * Intel ACPI Component Architecture
++ * iASL Compiler/Disassembler version 20151124-64
++ * Copyright (c) 2000 - 2015 Intel Corporation
++ *
++ * Template for [IORT] ACPI Table (static data table)
++ * Format: [ByteLength]  FieldName : HexFieldValue
++ */
++[0004]                          Signature : "IORT"    [IO Remapping Table]
++[0004]                       Table Length : 01c8
++[0001]                           Revision : 00
++[0001]                           Checksum : BC
++[0006]                             Oem ID : "HISI  "            // ?
++[0008]                       Oem Table ID : "HIP08   "          // ?
++[0004]                       Oem Revision : 00000000            // ?
++[0004]                    Asl Compiler ID : "INTL"
++[0004]              Asl Compiler Revision : 20150410
++
++[0004]                         Node Count : 00000005           // ITS, SMMU and RC
++[0004]                        Node Offset : 00000034           // ?
++[0004]                           Reserved : 00000000
++[0004]                   Optional Padding : 00 00 00 00
++
++/* 0x34 ITS, for PCIe */
++/* Here we use the P680/Hi1620 ACPI table which includes MADT table to help to debuge */
++[0001]                               Type : 00
++[0002]                             Length : 0018
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000000           // ?
++[0004]                     Mapping Offset : 00000000           // ?
++
++[0004]                           ItsCount : 00000001           // ?
++[0004]                        Identifiers : 00000000           // how to refer to MADT ?
++
++/*0x4c RC 0 */
++[0001]                               Type : 02
++[0002]                             Length : 00A0
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 0000000C
++[0004]                     Mapping Offset : 00000028
++
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000001
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0004]                      ATS Attribute : 00000000
++[0004]                 PCI Segment Number : 00000000           // should match with above MCFG
++
++/* BDF of pcie host 0 -> stream ID of pcie 0/1 SMMU */
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00004000          // the number of IDs in range
++[0004]                        Output Base : 00000000
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 1 -> stream ID of pcie 0/1 SMMU */
++[0004]                         Input base : 00007b00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 00007b00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 2 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 00007a00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 00007a00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 3 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 00007800
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 00007800
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 4 -> stream ID of pcie 4 SMMU */
++[0004]                         Input base : 00007c00
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 00007c00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 5 -> stream ID of pcie 5 SMMU */
++[0004]                         Input base : 00007400
++[0004]                           ID Count : 00000300          // the number of IDs in range
++[0004]                        Output Base : 00007400
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 6 -> stream ID of pcie 6/7 SMMU */
++[0004]                         Input base : 00008000
++[0004]                           ID Count : 00002000          // the number of IDs in range
++[0004]                        Output Base : 00008000
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 7 -> stream ID of pcie 6/7 SMMU */
++[0004]                         Input base : 0000BB00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 0000BB00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 8 -> stream ID of pcie ITS */
++[0004]                         Input base : 0000BA00
++[0004]                           ID Count : 00000100          // the number of IDs in range
++[0004]                        Output Base : 0000BA00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 9 -> stream ID of pcie 0/1 ITS */
++[0004]                         Input base : 0000B800
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 0000B800
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 10 -> stream ID of pcie 10 SMMU */
++[0004]                         Input base : 0000BC00
++[0004]                           ID Count : 00000200          // the number of IDs in range
++[0004]                        Output Base : 0000BC00
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* BDF of pcie host 11 -> stream ID of pcie 11 SMMU */
++[0004]                         Input base : 0000B400
++[0004]                           ID Count : 00000300          // the number of IDs in range
++[0004]                        Output Base : 0000B400
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000000
++                           Single Mapping : 0
++
++/* mbi-gen for S0-TB-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB30"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD1 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB31"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD2 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB32"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD3 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB33"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD4 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB34"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD5 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB35"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FD6 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB38"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDD // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB39"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDE // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FDF // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC7 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC8 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TB-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB3D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007FC9 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB10"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F51 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB11"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F52 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB12"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F53 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB13"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F54 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB14"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F55 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB15"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F56 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB18"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5D // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB19"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5E // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F5F // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F47 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F48 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S0-TA-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB1D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F49 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB70"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD1 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB71"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD2 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB72"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD3 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB73"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD4 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB74"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD5 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB75"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFD6 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB78"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDD // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB79"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDE // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFDF // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC7 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC8 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TB-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB7D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BFC9 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB50"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF51 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB51"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF52 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB52"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF53 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB53"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF54 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T4, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB54"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF55 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-L3T5, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB55"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF56 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB58"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5D // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB59"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5E // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC2, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5A"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF5F // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-DDRC3, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5B"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF47 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-HHA0, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5C"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF48 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++/* mbi-gen for S1-TA-HHA1, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MB5D"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 0000BF49 // PMU device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
++
++
++[320h 0800   1]                         Type : 01
++[321h 0801   2]                       Length : 0054
++[323h 0803   1]                     Revision : 00
++[324h 0804   4]                     Reserved : 00000000
++[328h 0808   4]                Mapping Count : 00000001
++[32Ch 0812   4]               Mapping Offset : 00000040
++
++[330h 0816   4]                   Node Flags : 00000000
++[334h 0820   8]            Memory Properties : [IORT Memory Access Properties]
++[334h 0820   4]              Cache Coherency : 00000000
++[338h 0824   1]        Hints (decoded below) : 00
++                                   Transient : 0
++                              Write Allocate : 0
++                               Read Allocate : 0
++                                    Override : 0
++[339h 0825   2]                     Reserved : 0000
++[33Bh 0827   1] Memory Flags (decoded below) : 00
++                                   Coherency : 0
++                            Device Attribute : 0
++[33Ch 0828   1]            Memory Size Limit : 00
++[33Dh 0829  11]                  Device Name : "\_SB_.SEC0"
++[348h 0840  24]                      Padding : \
++    00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \
++    4C 00 00 00 01 00 00 00
++
++[34Ch 0844   4]                   Input base : 00000000
++[350h 0848   4]                     ID Count : 00000001
++[354h 0852   4]                  Output Base : 00000100
++[358h 0856   4]             Output Reference : 00000034
++[35Ch 0860   4]        Flags (decoded below) : 00000001
++                              Single Mapping : 1
++/* RDE device report++.*/
++[320h 0800   1]                         Type : 01
++[321h 0801   2]                       Length : 0054
++[323h 0803   1]                     Revision : 00
++[324h 0804   4]                     Reserved : 00000000
++[328h 0808   4]                Mapping Count : 00000001
++[32Ch 0812   4]               Mapping Offset : 00000040
++
++[330h 0816   4]                   Node Flags : 00000000
++[334h 0820   8]            Memory Properties : [IORT Memory Access Properties]
++[334h 0820   4]              Cache Coherency : 00000000
++[338h 0824   1]        Hints (decoded below) : 00
++                                   Transient : 0
++                              Write Allocate : 0
++                               Read Allocate : 0
++                                    Override : 0
++[339h 0825   2]                     Reserved : 0000
++[33Bh 0827   1] Memory Flags (decoded below) : 00
++                                   Coherency : 0
++                            Device Attribute : 0
++[33Ch 0828   1]            Memory Size Limit : 00
++[33Dh 0829  11]                  Device Name : "\_SB_.RDE0"
++[348h 0840  24]                      Padding : \
++    00 00 00 00 00 00 00 00 01 00 00 00 80 00 04 00 \
++    4C 00 00 00 01 00 00 00
++
++[34Ch 0844   4]                   Input base : 00000000
++[350h 0848   4]                     ID Count : 00000001
++[354h 0852   4]                  Output Base : 00007f13
++[358h 0856   4]             Output Reference : 00000034
++[35Ch 0860   4]        Flags (decoded below) : 00000001
++                              Single Mapping : 1
++
++/* mbi-gen for MCTP, named component */
++[0001]                               Type : 01
++[0002]                             Length : 0046
++[0001]                           Revision : 00
++[0004]                           Reserved : 00000000
++[0004]                      Mapping Count : 00000001
++[0004]                     Mapping Offset : 00000032
++
++[0004]                         Node Flags : 00000000
++[0008]                  Memory Properties : [IORT Memory Access Properties]
++[0004]                    Cache Coherency : 00000000
++[0001]              Hints (decoded below) : 00
++                                Transient : 0
++                           Write Allocate : 0
++                            Read Allocate : 0
++                                 Override : 0
++[0002]                           Reserved : 0000
++[0001]       Memory Flags (decoded below) : 00
++                                Coherency : 0
++                         Device Attribute : 0
++[0001]                  Memory Size Limit : 00
++[0016]                        Device Name : "\_SB_.MBI4"
++[0004]                            Padding : 00 00 00 00
++
++[0004]                         Input base : 00000000
++[0004]                           ID Count : 00000001
++[0004]                        Output Base : 00007F18 // MCTP device id
++[0004]                   Output Reference : 00000034
++[0004]              Flags (decoded below) : 00000001
++                           Single Mapping : 1
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc
+new file mode 100644
+index 0000000000..2d719ef562
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Mcfg.aslc
+@@ -0,0 +1,64 @@
++/*
++ * Copyright (c) 2018 Hisilicon Limited
++ *
++ * All rights reserved. This program and the accompanying materials
++ * are made available under the terms of the BSD License which accompanies
++ * this distribution, and is available at
++ * http://opensource.org/licenses/bsd-license.php
++ *
++ */
++
++#include <IndustryStandard/Acpi.h>
++#include "Hi1620Platform.h"
++
++#define MCFG_VERSION  0x1
++
++#pragma pack(1)
++typedef struct
++{
++   UINT64 ullBaseAddress;
++   UINT16 usSegGroupNum;
++   UINT8  ucStartBusNum;
++   UINT8  ucEndBusNum;
++   UINT32 Reserved2;
++}EFI_MCFG_CONFIG_STRUCTURE;
++
++typedef struct
++{
++   EFI_ACPI_DESCRIPTION_HEADER Header;
++   UINT64 Reserved1;
++}EFI_MCFG_TABLE_CONFIG;
++
++typedef struct
++{
++   EFI_MCFG_TABLE_CONFIG Acpi_Table_Mcfg;
++   EFI_MCFG_CONFIG_STRUCTURE Config_Structure;
++}EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE;
++#pragma pack()
++
++EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE Mcfg=
++{
++  {
++      {
++        EFI_ACPI_6_1_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
++        sizeof (EFI_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_TABLE),
++        MCFG_VERSION,
++        0x00,                                                     // Checksum will be updated at runtime
++        {EFI_ACPI_ARM_OEM_ID},
++        EFI_ACPI_ARM_OEM_TABLE_ID,
++        EFI_ACPI_ARM_OEM_REVISION,
++        EFI_ACPI_ARM_CREATOR_ID,
++        EFI_ACPI_ARM_CREATOR_REVISION
++      },
++      0x0000000000000000,                                 //Reserved
++  },
++  {
++    0xd0000000,                                         //Base Address
++    0x0,                                                //Segment Group Number
++    0x0,                                                //Start Bus Number
++    0xff,                                               //End Bus Number
++    0x00000000,                                         //Reserved
++  }
++};
++
++VOID* CONST ReferenceAcpiTable = &Mcfg;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc
+new file mode 100644
+index 0000000000..53ae9a9235
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Slit.aslc
+@@ -0,0 +1,64 @@
++/*
++ * Copyright (c) 2013 Linaro Limited
++ *
++ * All rights reserved. This program and the accompanying materials
++ * are made available under the terms of the BSD License which accompanies
++ * this distribution, and is available at
++ * http://opensource.org/licenses/bsd-license.php
++ *
++ * Contributors:
++ *     Yi Li - yi.li@linaro.org
++*/
++
++#include <IndustryStandard/Acpi.h>
++#include "Hi1620Platform.h"
++
++#define EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT 0x0000000000000004
++
++#pragma pack(1)
++typedef struct {
++  UINT8   Entry[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
++} EFI_ACPI_6_2_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE;
++
++typedef struct {
++  EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_HEADER    Header;
++  EFI_ACPI_6_2_NUMBER_OF_SYSTEM_LOCALITIES_STRUCTURE                NumSlit[EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT];
++
++} EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE;
++#pragma pack()
++
++//
++// System Locality Information Table
++// Please modify all values in Slit.h only.
++//
++EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE Slit = {
++  {
++    {
++      EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE,
++      sizeof (EFI_ACPI_6_2_SYSTEM_LOCALITY_INFORMATION_TABLE),
++      EFI_ACPI_6_2_SYSTEM_LOCALITY_DISTANCE_INFORMATION_TABLE_REVISION,
++      0x00,                                                     // Checksum will be updated at runtime
++      {EFI_ACPI_ARM_OEM_ID},
++      EFI_ACPI_ARM_OEM_TABLE_ID,
++      EFI_ACPI_ARM_OEM_REVISION,
++      EFI_ACPI_ARM_CREATOR_ID,
++      EFI_ACPI_ARM_CREATOR_REVISION,
++    },
++    //
++    // Beginning of SLIT specific fields
++    //
++    EFI_ACPI_SYSTEM_LOCALITIES_ENTRY_COUNT,
++  },
++  {
++    {{0x0A, 0x10, 0x20, 0x21}}, //Locality   0
++    {{0x10, 0x0A, 0x19, 0x20}}, //Locality   1
++    {{0x20, 0x19, 0x0A, 0x10}}, //Locality   2
++    {{0x21, 0x20, 0x10, 0x0A}}, //Locality   3
++  },
++};
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Slit;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc
+new file mode 100644
+index 0000000000..a9768d4ba2
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Spcr.aslc
+@@ -0,0 +1,81 @@
++/** @file
++*  Serial Port Console Redirection Table (SPCR)
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2016 Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++#include <Library/AcpiLib.h>
++#include <Library/PcdLib.h>
++#include <IndustryStandard/Acpi.h>
++#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
++#include "Hi1620Platform.h"
++
++#define SPCR_FLOW_CONTROL_NONE           0
++
++STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
++  ARM_ACPI_HEADER (EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
++                     EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
++                     EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
++  // UINT8                                   InterfaceType;
++  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
++  // UINT8                                   Reserved1[3];
++  {
++    EFI_ACPI_RESERVED_BYTE,
++    EFI_ACPI_RESERVED_BYTE,
++    EFI_ACPI_RESERVED_BYTE
++  },
++  // EFI_ACPI_6_2_GENERIC_ADDRESS_STRUCTURE  BaseAddress;
++  ARM_GAS32 (FixedPcdGet64 (PcdSerialRegisterBase)),
++  // UINT8                                   InterruptType;
++  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
++  // UINT8                                   Irq;
++  0,                                         // Not used on ARM
++  // UINT32                                  GlobalSystemInterrupt;
++  141,
++  // UINT8                                   BaudRate;
++  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
++  // UINT8                                   Parity;
++  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
++  // UINT8                                   StopBits;
++  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
++  // UINT8                                   FlowControl;
++  SPCR_FLOW_CONTROL_NONE,
++  // UINT8                                   TerminalType;
++  EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
++  // UINT8                                   Reserved2;
++  EFI_ACPI_RESERVED_BYTE,
++  // UINT16                                  PciDeviceId;
++  0xFFFF,
++  // UINT16                                  PciVendorId;
++  0xFFFF,
++  // UINT8                                   PciBusNumber;
++  0x00,
++  // UINT8                                   PciDeviceNumber;
++  0x00,
++  // UINT8                                   PciFunctionNumber;
++  0x00,
++  // UINT32                                  PciFlags;
++  0x00000000,
++  // UINT8                                   PciSegment;
++  0x00,
++  // UINT32                                  Reserved3;
++  EFI_ACPI_RESERVED_DWORD
++};
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Spcr;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc
+new file mode 100644
+index 0000000000..aea4c21858
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/Hi1620Srat.aslc
+@@ -0,0 +1,166 @@
++/*
++ * Copyright (c) 2013 Linaro Limited
++ *
++ * All rights reserved. This program and the accompanying materials
++ * are made available under the terms of the BSD License which accompanies
++ * this distribution, and is available at
++ * http://opensource.org/licenses/bsd-license.php
++ *
++ * Contributors:
++ *     Yi Li - yi.li@linaro.org
++ *
++ *  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*/
++
++#include <IndustryStandard/Acpi.h>
++#include "Hi1620Platform.h"
++#include <Library/AcpiLib.h>
++#include <Library/AcpiNextLib.h>
++
++
++//
++// Static Resource Affinity Table definition
++//
++EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE Srat = {
++  {
++    {EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_SIGNATURE,
++    sizeof (EFI_ACPI_STATIC_RESOURCE_AFFINITY_TABLE),
++    EFI_ACPI_6_2_SYSTEM_RESOURCE_AFFINITY_TABLE_REVISION,
++    0x00,                                                     // Checksum will be updated at runtime
++    {EFI_ACPI_ARM_OEM_ID},
++    EFI_ACPI_ARM_OEM_TABLE_ID,
++    EFI_ACPI_ARM_OEM_REVISION,
++    EFI_ACPI_ARM_CREATOR_ID,
++    EFI_ACPI_ARM_CREATOR_REVISION},
++    /*Reserved*/
++    0x00000001,                                  // Reserved to be 1 for backward compatibility
++    EFI_ACPI_RESERVED_QWORD
++  },
++
++  //
++  //
++  // Memory Affinity
++  //
++  {
++    EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
++    EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
++    EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
++    EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
++    EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
++    EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
++    EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
++    EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
++    EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
++    EFI_ACPI_6_1_MEMORY_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000001),
++  },
++
++  {
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000000,0x00000001,0x00000000),   //GICC Affinity Processor 0
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000001,0x00000001,0x00000000),   //GICC Affinity Processor 1
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000002,0x00000001,0x00000000),   //GICC Affinity Processor 2
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000003,0x00000001,0x00000000),   //GICC Affinity Processor 3
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000004,0x00000001,0x00000000),   //GICC Affinity Processor 4
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000005,0x00000001,0x00000000),   //GICC Affinity Processor 5
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000006,0x00000001,0x00000000),   //GICC Affinity Processor 6
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000007,0x00000001,0x00000000),   //GICC Affinity Processor 7
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000008,0x00000001,0x00000000),   //GICC Affinity Processor 8
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000009,0x00000001,0x00000000),   //GICC Affinity Processor 9
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000A,0x00000001,0x00000000),   //GICC Affinity Processor 10
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000B,0x00000001,0x00000000),   //GICC Affinity Processor 11
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000C,0x00000001,0x00000000),   //GICC Affinity Processor 12
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000D,0x00000001,0x00000000),   //GICC Affinity Processor 13
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000E,0x00000001,0x00000000),   //GICC Affinity Processor 14
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x0000000F,0x00000001,0x00000000),   //GICC Affinity Processor 15
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000010,0x00000001,0x00000000),   //GICC Affinity Processor 16
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000011,0x00000001,0x00000000),   //GICC Affinity Processor 17
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000012,0x00000001,0x00000000),   //GICC Affinity Processor 18
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000013,0x00000001,0x00000000),   //GICC Affinity Processor 19
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000014,0x00000001,0x00000000),   //GICC Affinity Processor 20
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000015,0x00000001,0x00000000),   //GICC Affinity Processor 21
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000016,0x00000001,0x00000000),   //GICC Affinity Processor 22
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000001,0x00000017,0x00000001,0x00000000),   //GICC Affinity Processor 23
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000018,0x00000001,0x00000000),   //GICC Affinity Processor 24
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000019,0x00000001,0x00000000),   //GICC Affinity Processor 25
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001A,0x00000001,0x00000000),   //GICC Affinity Processor 26
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001B,0x00000001,0x00000000),   //GICC Affinity Processor 27
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001C,0x00000001,0x00000000),   //GICC Affinity Processor 28
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001D,0x00000001,0x00000000),   //GICC Affinity Processor 29
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001E,0x00000001,0x00000000),   //GICC Affinity Processor 30
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000001F,0x00000001,0x00000000),   //GICC Affinity Processor 31
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000020,0x00000001,0x00000000),   //GICC Affinity Processor 32
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000021,0x00000001,0x00000000),   //GICC Affinity Processor 33
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000022,0x00000001,0x00000000),   //GICC Affinity Processor 34
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000023,0x00000001,0x00000000),   //GICC Affinity Processor 35
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000024,0x00000001,0x00000000),   //GICC Affinity Processor 36
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000025,0x00000001,0x00000000),   //GICC Affinity Processor 37
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000026,0x00000001,0x00000000),   //GICC Affinity Processor 38
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000027,0x00000001,0x00000000),   //GICC Affinity Processor 39
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000028,0x00000001,0x00000000),   //GICC Affinity Processor 40
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x00000029,0x00000001,0x00000000),   //GICC Affinity Processor 41
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002A,0x00000001,0x00000000),   //GICC Affinity Processor 42
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002B,0x00000001,0x00000000),   //GICC Affinity Processor 43
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002C,0x00000001,0x00000000),   //GICC Affinity Processor 44
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002D,0x00000001,0x00000000),   //GICC Affinity Processor 45
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002E,0x00000001,0x00000000),   //GICC Affinity Processor 46
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000000,0x0000002F,0x00000001,0x00000000),   //GICC Affinity Processor 47
++
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000030,0x00000001,0x00000000),   //GICC Affinity Processor 48
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000031,0x00000001,0x00000000),   //GICC Affinity Processor 49
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000032,0x00000001,0x00000000),   //GICC Affinity Processor 50
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000033,0x00000001,0x00000000),   //GICC Affinity Processor 51
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000034,0x00000001,0x00000000),   //GICC Affinity Processor 52
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000035,0x00000001,0x00000000),   //GICC Affinity Processor 53
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000036,0x00000001,0x00000000),   //GICC Affinity Processor 54
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000037,0x00000001,0x00000000),   //GICC Affinity Processor 55
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000038,0x00000001,0x00000000),   //GICC Affinity Processor 56
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000039,0x00000001,0x00000000),   //GICC Affinity Processor 57
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003A,0x00000001,0x00000000),   //GICC Affinity Processor 58
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003B,0x00000001,0x00000000),   //GICC Affinity Processor 59
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003C,0x00000001,0x00000000),   //GICC Affinity Processor 60
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003D,0x00000001,0x00000000),   //GICC Affinity Processor 61
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003E,0x00000001,0x00000000),   //GICC Affinity Processor 62
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x0000003F,0x00000001,0x00000000),   //GICC Affinity Processor 63
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000040,0x00000001,0x00000000),   //GICC Affinity Processor 64
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000041,0x00000001,0x00000000),   //GICC Affinity Processor 65
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000042,0x00000001,0x00000000),   //GICC Affinity Processor 66
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000043,0x00000001,0x00000000),   //GICC Affinity Processor 67
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000044,0x00000001,0x00000000),   //GICC Affinity Processor 68
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000045,0x00000001,0x00000000),   //GICC Affinity Processor 69
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000046,0x00000001,0x00000000),   //GICC Affinity Processor 70
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000003,0x00000047,0x00000001,0x00000000),   //GICC Affinity Processor 71
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000048,0x00000001,0x00000000),   //GICC Affinity Processor 72
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000049,0x00000001,0x00000000),   //GICC Affinity Processor 73
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004A,0x00000001,0x00000000),   //GICC Affinity Processor 74
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004B,0x00000001,0x00000000),   //GICC Affinity Processor 75
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004C,0x00000001,0x00000000),   //GICC Affinity Processor 76
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004D,0x00000001,0x00000000),   //GICC Affinity Processor 77
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004E,0x00000001,0x00000000),   //GICC Affinity Processor 78
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000004F,0x00000001,0x00000000),   //GICC Affinity Processor 79
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000050,0x00000001,0x00000000),   //GICC Affinity Processor 80
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000051,0x00000001,0x00000000),   //GICC Affinity Processor 81
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000052,0x00000001,0x00000000),   //GICC Affinity Processor 82
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000053,0x00000001,0x00000000),   //GICC Affinity Processor 83
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000054,0x00000001,0x00000000),   //GICC Affinity Processor 84
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000055,0x00000001,0x00000000),   //GICC Affinity Processor 85
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000056,0x00000001,0x00000000),   //GICC Affinity Processor 86
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000057,0x00000001,0x00000000),   //GICC Affinity Processor 87
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000058,0x00000001,0x00000000),   //GICC Affinity Processor 88
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x00000059,0x00000001,0x00000000),   //GICC Affinity Processor 89
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005A,0x00000001,0x00000000),   //GICC Affinity Processor 90
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005B,0x00000001,0x00000000),   //GICC Affinity Processor 91
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005C,0x00000001,0x00000000),   //GICC Affinity Processor 92
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005D,0x00000001,0x00000000),   //GICC Affinity Processor 93
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005E,0x00000001,0x00000000),   //GICC Affinity Processor 94
++    EFI_ACPI_6_1_GICC_AFFINITY_STRUCTURE_INIT(0x00000002,0x0000005F,0x00000001,0x00000000),   //GICC Affinity Processor 95
++  },
++  {
++    EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000001, 0x00000000),
++   // EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_INIT(0x00000003, 0x00000001),
++  },
++};
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Srat;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc
+new file mode 100644
+index 0000000000..43b43142af
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/MadtHi1620.aslc
+@@ -0,0 +1,375 @@
++/** @file
++*  Multiple APIC Description Table (MADT)
++*
++*  Copyright (c) 2012 - 2014, ARM Limited. All rights reserved.
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2015, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
++*
++**/
++
++#include "Hi1620Platform.h"
++
++#include <Library/AcpiLib.h>
++#include <Library/ArmLib.h>
++#include <Library/PcdLib.h>
++#include <IndustryStandard/Acpi.h>
++#include <Library/AcpiNextLib.h>
++
++// Differs from Juno, we have another affinity level beyond cluster and core
++// 0x20000 is only for socket 0
++#define PLATFORM_GET_MPID_TA(ClusterId, CoreId)   (0x10000 | ((ClusterId) << 8) | (CoreId))
++#define PLATFORM_GET_MPID_TB(ClusterId, CoreId)   (0x30000 | ((ClusterId) << 8) | (CoreId))
++#define PLATFORM_GET_MPID_TA_2(ClusterId, CoreId)   (0x50000 | ((ClusterId) << 8) | (CoreId))
++#define PLATFORM_GET_MPID_TB_2(ClusterId, CoreId)   (0x70000 | ((ClusterId) << 8) | (CoreId))
++
++//
++// Multiple APIC Description Table
++//
++#pragma pack (1)
++
++typedef struct {
++  EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER   Header;
++  EFI_ACPI_6_2_GIC_STRUCTURE                            GicInterfaces[EFI_ACPI_PROCESSOR_LOCAL_GICC_AFFINITY_STRUCTURE_COUNT];
++  EFI_ACPI_6_2_GIC_DISTRIBUTOR_STRUCTURE                GicDistributor;
++  EFI_ACPI_6_2_GIC_ITS_STRUCTURE                      GicITS[EFI_ACPI_6_2_ITS_AFFINITY_STRUCTURE_COUNT];
++} EFI_ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE;
++
++#pragma pack ()
++
++EFI_ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
++  {
++    ARM_ACPI_HEADER (
++      EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
++      EFI_ACPI_MULTIPLE_APIC_DESCRIPTION_TABLE,
++      EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
++    ),
++    //
++    // MADT specific fields
++    //
++    0, // LocalApicAddress
++    0, // Flags
++  },
++  {
++    // Format: EFI_ACPI_6_1_GICC_STRUCTURE_INIT(GicId, AcpiCpuUid, Flags, PmuIrq, GicBase, GicVBase, GicHBase,
++    //                                          GsivId, GicRBase, Mpidr)
++    // Note: The GIC Structure of the primary CPU must be the first entry (see note in 5.2.12.14 GICC Structure of
++    //       ACPI v5.1).
++    //       The cores from a same cluster are kept together. It is not an ACPI requirement but in case the OSPM uses
++    //       the ACPI ARM Parking protocol, it might want to wake up the cores in the order of this table.
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        0, 0, PLATFORM_GET_MPID_TA(0, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x100000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        1, 1, PLATFORM_GET_MPID_TA(0, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x140000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        2, 2, PLATFORM_GET_MPID_TA(0, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x180000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        3, 3, PLATFORM_GET_MPID_TA(0, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x1C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        4, 4, PLATFORM_GET_MPID_TA(1, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x200000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        5, 5, PLATFORM_GET_MPID_TA(1, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x240000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        6, 6, PLATFORM_GET_MPID_TA(1, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x280000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        7, 7, PLATFORM_GET_MPID_TA(1, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x2C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        8, 8, PLATFORM_GET_MPID_TA(2, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x300000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        9, 9, PLATFORM_GET_MPID_TA(2, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x340000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        10, 10, PLATFORM_GET_MPID_TA(2, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x380000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        11, 11, PLATFORM_GET_MPID_TA(2, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x3C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        12, 12, PLATFORM_GET_MPID_TA(3, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x400000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        13, 13, PLATFORM_GET_MPID_TA(3, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x440000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        14, 14, PLATFORM_GET_MPID_TA(3, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x480000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        15, 15, PLATFORM_GET_MPID_TA(3, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x4C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        16, 16, PLATFORM_GET_MPID_TA(4, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x500000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        17, 17, PLATFORM_GET_MPID_TA(4, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x540000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        18, 18, PLATFORM_GET_MPID_TA(4, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x580000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        19, 19, PLATFORM_GET_MPID_TA(4, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x5C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        20, 20, PLATFORM_GET_MPID_TA(5, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x600000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        21, 21, PLATFORM_GET_MPID_TA(5, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x640000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        22, 22, PLATFORM_GET_MPID_TA(5, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x680000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        23, 23, PLATFORM_GET_MPID_TA(5, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAE000000 + 0x6C0000 /* GicRBase */, 0),
++
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        24, 24, PLATFORM_GET_MPID_TB(0, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x100000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        25, 25, PLATFORM_GET_MPID_TB(0, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x140000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        26, 26, PLATFORM_GET_MPID_TB(0, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x180000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        27, 27, PLATFORM_GET_MPID_TB(0, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x1C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        28, 28, PLATFORM_GET_MPID_TB(1, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x200000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        29, 29, PLATFORM_GET_MPID_TB(1, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x240000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        30, 30, PLATFORM_GET_MPID_TB(1, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x280000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        31, 31, PLATFORM_GET_MPID_TB(1, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x2C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        32, 32, PLATFORM_GET_MPID_TB(2, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x300000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        33, 33, PLATFORM_GET_MPID_TB(2, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x340000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        34, 34, PLATFORM_GET_MPID_TB(2, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x380000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        35, 35, PLATFORM_GET_MPID_TB(2, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x3C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        36, 36, PLATFORM_GET_MPID_TB(3, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x400000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        37, 37, PLATFORM_GET_MPID_TB(3, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x440000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        38, 38, PLATFORM_GET_MPID_TB(3, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x480000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        39, 39, PLATFORM_GET_MPID_TB(3, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x4C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        40, 40, PLATFORM_GET_MPID_TB(4, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x500000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        41, 41, PLATFORM_GET_MPID_TB(4, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x540000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        42, 42, PLATFORM_GET_MPID_TB(4, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x580000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        43, 43, PLATFORM_GET_MPID_TB(4, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x5C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        44, 44, PLATFORM_GET_MPID_TB(5, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x600000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        45, 45, PLATFORM_GET_MPID_TB(5, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x640000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        46, 46, PLATFORM_GET_MPID_TB(5, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x680000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        47, 47, PLATFORM_GET_MPID_TB(5, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0xAA000000 + 0x6C0000 /* GicRBase */, 0),
++
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        48, 48, PLATFORM_GET_MPID_TA_2(0, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x100000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        49, 49, PLATFORM_GET_MPID_TA_2(0, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x140000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        50, 50, PLATFORM_GET_MPID_TA_2(0, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x180000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        51, 51, PLATFORM_GET_MPID_TA_2(0, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x1C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        52, 52, PLATFORM_GET_MPID_TA_2(1, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x200000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        53, 53, PLATFORM_GET_MPID_TA_2(1, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x240000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        54, 54, PLATFORM_GET_MPID_TA_2(1, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x280000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        55, 55, PLATFORM_GET_MPID_TA_2(1, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x2C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        56, 56, PLATFORM_GET_MPID_TA_2(2, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x300000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        57, 57, PLATFORM_GET_MPID_TA_2(2, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x340000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        58, 58, PLATFORM_GET_MPID_TA_2(2, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x380000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        59, 59, PLATFORM_GET_MPID_TA_2(2, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x3C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        60, 60, PLATFORM_GET_MPID_TA_2(3, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x400000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        61, 61, PLATFORM_GET_MPID_TA_2(3, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x440000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        62, 62, PLATFORM_GET_MPID_TA_2(3, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x480000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        63, 63, PLATFORM_GET_MPID_TA_2(3, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x4C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        64, 64, PLATFORM_GET_MPID_TA_2(4, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x500000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        65, 65, PLATFORM_GET_MPID_TA_2(4, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x540000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        66, 66, PLATFORM_GET_MPID_TA_2(4, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x580000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        67, 67, PLATFORM_GET_MPID_TA_2(4, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x5C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        68, 68, PLATFORM_GET_MPID_TA_2(5, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x600000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        69, 69, PLATFORM_GET_MPID_TA_2(5, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x640000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        70, 70, PLATFORM_GET_MPID_TA_2(5, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x680000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        71, 71, PLATFORM_GET_MPID_TA_2(5, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AE000000 + 0x6C0000 /* GicRBase */, 0),
++
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        72, 72, PLATFORM_GET_MPID_TB_2(0, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x100000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        73, 73, PLATFORM_GET_MPID_TB_2(0, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x140000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        74, 74, PLATFORM_GET_MPID_TB_2(0, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x180000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        75, 75, PLATFORM_GET_MPID_TB_2(0, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x1C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        76, 76, PLATFORM_GET_MPID_TB_2(1, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x200000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        77, 77, PLATFORM_GET_MPID_TB_2(1, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x240000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        78, 78, PLATFORM_GET_MPID_TB_2(1, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x280000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        79, 79, PLATFORM_GET_MPID_TB_2(1, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x2C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        80, 80, PLATFORM_GET_MPID_TB_2(2, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x300000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        81, 81, PLATFORM_GET_MPID_TB_2(2, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x340000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        82, 82, PLATFORM_GET_MPID_TB_2(2, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x380000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        83, 83, PLATFORM_GET_MPID_TB_2(2, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x3C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        84, 84, PLATFORM_GET_MPID_TB_2(3, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x400000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        85, 85, PLATFORM_GET_MPID_TB_2(3, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x440000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        86, 86, PLATFORM_GET_MPID_TB_2(3, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x480000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        87, 87, PLATFORM_GET_MPID_TB_2(3, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x4C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        88, 88, PLATFORM_GET_MPID_TB_2(4, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x500000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        89, 89, PLATFORM_GET_MPID_TB_2(4, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x540000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        90, 90, PLATFORM_GET_MPID_TB_2(4, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x580000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        91, 91, PLATFORM_GET_MPID_TB_2(4, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x5C0000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        92, 92, PLATFORM_GET_MPID_TB_2(5, 0),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x600000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        93, 93, PLATFORM_GET_MPID_TB_2(5, 1),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x640000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        94, 94, PLATFORM_GET_MPID_TB_2(5, 2),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x680000 /* GicRBase */, 0),
++    EFI_ACPI_6_1_GICC_STRUCTURE_INIT(
++        95, 95, PLATFORM_GET_MPID_TB_2(5, 3),  EFI_ACPI_6_2_GIC_ENABLED, 23, FixedPcdGet32 (PcdGicInterruptInterfaceBase),
++        0x0, 0x0, 25, 0x4000AA000000 + 0x6C0000 /* GicRBase */, 0),
++  },
++
++  EFI_ACPI_6_1_GIC_DISTRIBUTOR_INIT(0, 0xAA000000, 0, 0x4),
++  {
++    EFI_ACPI_6_1_GIC_ITS_INIT(0,0x202100000), //peri a
++//    EFI_ACPI_6_1_GIC_ITS_INIT(1,0x400202100000), //peri a
++  }
++};
++
++//
++// Reference the table being generated to prevent the optimizer from removing the
++// data structure from the executable
++//
++VOID* CONST ReferenceAcpiTable = &Madt;
+-- 
+2.17.0
+
diff --git a/v2/v2-0018-Hisilicon-D06-Add-Hi1620OemConfigUiLib.patch b/v2/v2-0018-Hisilicon-D06-Add-Hi1620OemConfigUiLib.patch
new file mode 100644
index 0000000000..0c8703998e
--- /dev/null
+++ b/v2/v2-0018-Hisilicon-D06-Add-Hi1620OemConfigUiLib.patch
@@ -0,0 +1,2268 @@
+From e7bbff5e9afebfe4842da32fe705dfd60a773465 Mon Sep 17 00:00:00 2001
+From: Yang XinYi <yangxingyi@huawei.com>
+Date: Tue, 26 Jun 2018 11:01:45 +0800
+Subject: [PATCH edk2-platforms v2 18/43] Hisilicon/D06: Add
+ Hi1620OemConfigUiLib
+
+This library is added for oem setup menu item.
+Setup item include:
+1 DDR option item;
+2 BMC option item;
+3 Ras option item;
+4 Misc option item;
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Yang XinYi <yangxingyi@huawei.com>
+---
+ Silicon/Hisilicon/HisiPkg.dec                                           |   1 +
+ Platform/Hisilicon/D06/D06.dsc                                          |   5 +-
+ Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf       |   2 +-
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf        |  68 ++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h               | 142 ++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h             |  64 ++++
+ Silicon/Hisilicon/Include/Library/OemConfigData.h                       |  84 +++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c               | 363 ++++++++++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr          | 154 +++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni          | 103 ++++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr            |  41 +++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni            |  27 ++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni        |  24 ++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni |  42 +++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.Vfr          |  89 +++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr            | 219 ++++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni     | 111 ++++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr        | 167 +++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr             | 172 ++++++++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni             |  85 +++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr            |  81 +++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni            |  34 ++
+ 22 files changed, 2076 insertions(+), 2 deletions(-)
+
+diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec
+index b56a6a6af7..858b840a57 100644
+--- a/Silicon/Hisilicon/HisiPkg.dec
++++ b/Silicon/Hisilicon/HisiPkg.dec
+@@ -44,6 +44,7 @@
+   gHisiTokenSpaceGuid = {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, 0xf7, 0x7c, 0xfd, 0x52, 0x1d}}
+ 
+   gHisiEfiMemoryMapGuid  = {0xf8870015, 0x6994, 0x4b98, {0x95, 0xa2, 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f}}
++  gOemConfigGuid = {0x42927b59, 0x58fc, 0x41be, {0x8f, 0x59, 0xd1, 0x7c, 0x02, 0x1a, 0x70, 0x13}}
+   gVersionInfoHobGuid = {0xe13a14c, 0x859c, 0x4f22, {0x82, 0xbd, 0x18, 0xe, 0xe1, 0x42, 0x12, 0xbf}}
+   gHisiOemVariableGuid = {0xac62b9a5, 0x9939, 0x41d3, {0xff, 0x5c, 0xc5, 0x80, 0x32, 0x7d, 0x9b, 0x29}}
+   gOemBootVariableGuid = {0xb7784577, 0x5aaf, 0x4557, {0xa1, 0x99, 0xd4, 0xa4, 0x2f, 0x45, 0x06, 0xf8}}
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 9d4a86a4f4..bec422670d 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -330,7 +330,10 @@
+   #ACPI
+   #
+   MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
+-  Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
++  Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf {
++    <LibraryClasses>
++    NULL|Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf
++  }
+ 
+   Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+   Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+index e268a56bbd..281a4f2ebd 100644
+--- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
++++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+@@ -56,7 +56,7 @@
+   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile    ## CONSUMES
+ 
+ [Depex]
+-  gEfiAcpiTableProtocolGuid
++  gEfiAcpiTableProtocolGuid AND gEfiVariableWriteArchProtocolGuid
+ 
+ [UserExtensions.TianoCore."ExtraFiles"]
+   AcpiPlatformExtra.uni
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf
+new file mode 100644
+index 0000000000..fba619e9ba
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.inf
+@@ -0,0 +1,68 @@
++## @file
++#  OEM config Library used by BDS
++#
++#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#  Copyright (c) 2018, Linaro Limited. All rights reserved.
++#  This program and the accompanying materials are licensed and made available under
++#  the terms and conditions of the BSD License that accompanies this distribution.
++#  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php.
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++##
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = OemConfigUiLib
++  MODULE_UNI_FILE                = OemConfigUiLib.uni
++  FILE_GUID                      = 32B373AC-00B6-471b-B3AE-6E4A4501F6BA
++  MODULE_TYPE                    = DXE_DRIVER
++  VERSION_STRING                 = 1.0
++  LIBRARY_CLASS                  = NULL|DXE_DRIVER UEFI_APPLICATION
++  CONSTRUCTOR                    = OemConfigUiLibConstructor
++  DESTRUCTOR                     = OemConfigUiLibDestructor
++
++[Sources]
++  iBMCConfig.hfr
++  iBMCConfig.uni
++  MemoryConfig.hfr
++  MemoryConfig.uni
++  MiscConfig.hfr
++  MiscConfig.uni
++  OemConfig.c
++  OemConfig.h
++  OemConfigUiLibStrings.uni
++  OemConfigVfr.Vfr
++  PcieConfig.hfr
++  PcieConfigStrings.uni
++  PciePortConfig.hfr
++  RasConfig.hfr
++  RasConfig.uni
++
++[Packages]
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  BaseLib
++  BaseMemoryLib
++  DebugLib
++  DevicePathLib
++  HiiLib
++  MemoryAllocationLib
++  PrintLib
++  UefiBootServicesTableLib
++  UefiHiiServicesLib
++  UefiRuntimeServicesTableLib
++
++[Guids]
++  gEfiHiiPlatformSetupFormsetGuid               ## CONSUMES ## GUID (Indicate the formset class guid to be displayed)
++  gEfiIfrFrontPageGuid                          ## CONSUMES ## GUID (Indicate the formset in this library need to dispaly in which page)
++  gEfiIfrTianoGuid                              ## CONSUMES ## GUID (Extended IFR Guid Opcode)
++  gOemConfigGuid
++  gVersionInfoHobGuid
++
++[Protocols]
++  gEfiHiiConfigAccessProtocolGuid               ## CONSUMES
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h
+new file mode 100644
+index 0000000000..f91400150c
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.h
+@@ -0,0 +1,142 @@
++/** @file
++The Oem config reference implement
++
++Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++Copyright (c) 2018, Linaro Limited. All rights reserved.
++This program and the accompanying materials
++are licensed and made available under the terms and conditions of the BSD License
++which accompanies this distribution.  The full text of the license may be found at
++http://opensource.org/licenses/bsd-license.php
++
++THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#ifndef _OEM_CONFIG_H_
++#define _OEM_CONFIG_H_
++
++#include <Guid/HiiPlatformSetupFormset.h>
++#include <Guid/MdeModuleHii.h>
++#include <Guid/VersionInfoHobGuid.h>
++#include <Library/BaseMemoryLib.h>
++#include <Library/BaseLib.h>
++#include <Library/DebugLib.h>
++#include <Library/DevicePathLib.h>
++#include <Library/HiiLib.h>
++#include <Library/HobLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include "Library/OemConfigData.h"
++#include <Library/PcdLib.h>
++#include <Library/PrintLib.h>
++#include <Library/UefiBootServicesTableLib.h>
++#include <Library/UefiHiiServicesLib.h>
++#include <Library/UefiRuntimeServicesTableLib.h>
++#include <Pi/PiFirmwareVolume.h>
++#include <Protocol/HiiConfigAccess.h>
++
++//
++// These are the VFR compiler generated data representing our VFR data.
++//
++extern UINT8  OemConfigVfrBin[];
++
++//
++// HII specific Vendor Device Path definition.
++//
++typedef struct {
++  VENDOR_DEVICE_PATH          VendorDevicePath;
++  EFI_DEVICE_PATH_PROTOCOL    End;
++} HII_VENDOR_DEVICE_PATH;
++
++#define OEM_CONFIG_CALLBACK_DATA_SIGNATURE  SIGNATURE_32 ('O', 'E', 'M', 'C')
++typedef struct {
++  UINTN                             Signature;
++  EFI_HII_HANDLE                    HiiHandle;
++  EFI_HANDLE                        DriverHandle;
++  EFI_HII_CONFIG_ACCESS_PROTOCOL    ConfigAccess;
++} OEM_CONFIG_CALLBACK_DATA;
++
++/**
++  This function allows a caller to extract the current configuration for one
++  or more named elements from the target driver.
++
++
++  @param This            Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
++  @param Request         A null-terminated Unicode string in <ConfigRequest> format.
++  @param Progress        On return, points to a character in the Request string.
++                         Points to the string's null terminator if request was successful.
++                         Points to the most recent '&' before the first failing name/value
++                         pair (or the beginning of the string if the failure is in the
++                         first name/value pair) if the request was not successful.
++  @param Results         A null-terminated Unicode string in <ConfigAltResp> format which
++                         has all values filled in for the names in the Request string.
++                         String to be allocated by the called function.
++
++  @retval  EFI_SUCCESS            The Results is filled with the requested values.
++  @retval  EFI_OUT_OF_RESOURCES   Not enough memory to store the results.
++  @retval  EFI_INVALID_PARAMETER  Request is illegal syntax, or unknown name.
++  @retval  EFI_NOT_FOUND          Routing data doesn't match any storage in this driver.
++
++**/
++EFI_STATUS
++EFIAPI
++OemExtractConfig (
++  IN  CONST EFI_HII_CONFIG_ACCESS_PROTOCOL   *This,
++  IN  CONST EFI_STRING                       Request,
++  OUT       EFI_STRING                       *Progress,
++  OUT       EFI_STRING                       *Results
++  );
++
++/**
++  This function processes the results of changes in configuration.
++
++
++  @param This            Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
++  @param Configuration   A null-terminated Unicode string in <ConfigResp> format.
++  @param Progress        A pointer to a string filled in with the offset of the most
++                         recent '&' before the first failing name/value pair (or the
++                         beginning of the string if the failure is in the first
++                         name/value pair) or the terminating NULL if all was successful.
++
++  @retval  EFI_SUCCESS            The Results is processed successfully.
++  @retval  EFI_INVALID_PARAMETER  Configuration is NULL.
++  @retval  EFI_NOT_FOUND          Routing data doesn't match any storage in this driver.
++
++**/
++EFI_STATUS
++EFIAPI
++OemRouteConfig (
++  IN  CONST EFI_HII_CONFIG_ACCESS_PROTOCOL   *This,
++  IN  CONST EFI_STRING                       Configuration,
++  OUT       EFI_STRING                       *Progress
++  );
++
++/**
++  This function is invoked if user selected a interactive opcode from Device Manager's
++  Formset. If user set VBIOS, the new value is saved to EFI variable.
++
++  @param This            Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
++  @param Action          Specifies the type of action taken by the browser.
++  @param QuestionId      A unique value which is sent to the original exporting driver
++                         so that it can identify the type of data to expect.
++  @param Type            The type of value for the question.
++  @param Value           A pointer to the data being sent to the original exporting driver.
++  @param ActionRequest   On return, points to the action requested by the callback function.
++
++  @retval  EFI_SUCCESS           The callback successfully handled the action.
++  @retval  EFI_INVALID_PARAMETER The setup browser call this function with invalid parameters.
++
++**/
++EFI_STATUS
++EFIAPI
++OemCallback (
++  IN  CONST EFI_HII_CONFIG_ACCESS_PROTOCOL   *This,
++  IN        EFI_BROWSER_ACTION               Action,
++  IN        EFI_QUESTION_ID                  QuestionId,
++  IN        UINT8                            Type,
++  IN        EFI_IFR_TYPE_VALUE               *Value,
++  OUT       EFI_BROWSER_ACTION_REQUEST       *ActionRequest
++  );
++
++VOID GetReleaseTime (EFI_TIME *Time);
++#endif
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h
+new file mode 100644
+index 0000000000..792e544c22
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUi.h
+@@ -0,0 +1,64 @@
++/** @file
++
++Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++Copyright (c) 2018, Linaro Limited. All rights reserved.
++This program and the accompanying materials
++are licensed and made available under the terms and conditions of the BSD License
++which accompanies this distribution.  The full text of the license may be found at
++http://opensource.org/licenses/bsd-license.php
++
++THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++Module Name:
++
++  OemConfigUi.h
++
++Abstract:
++
++  NVData structure used by the OEM Config.
++
++Revision History:
++
++
++**/
++
++#ifndef _OEM_CONFIG_UI_H_
++#define _OEM_CONFIG_UI_H_
++
++#include <Uefi/UefiMultiPhase.h>
++
++#define OEM_CONFIG_FORM_ID                   1
++#define MEMORY_CONFIG_FORM_ID                2
++#define IBMC_CONFIG_FORM_ID                  3
++#define PCIE_CONFIG_FORM_ID                  4
++#define MISC_CONFIG_FORM_ID                  5
++#define RAS_CONFIG_FORM_ID                   6
++
++#define VFR_FORMID_PCIE_SOCKET0              0x4100
++#define VFR_FORMID_PCIE_SOCKET1              0x4200
++#define VFR_FORMID_PCIE_PORT0                0x4000
++#define VFR_FORMID_PCIE_PORT1                0x4001
++#define VFR_FORMID_PCIE_PORT2                0x4002
++#define VFR_FORMID_PCIE_PORT3                0x4003
++#define VFR_FORMID_PCIE_PORT4                0x4004
++#define VFR_FORMID_PCIE_PORT5                0x4005
++#define VFR_FORMID_PCIE_PORT6                0x4006
++#define VFR_FORMID_PCIE_PORT7                0x4007
++#define VFR_FORMID_PCIE_PORT8                0x4008
++#define VFR_FORMID_PCIE_PORT9                0x4009
++#define VFR_FORMID_PCIE_PORT10               0x4010
++#define VFR_FORMID_PCIE_PORT11               0x4011
++#define VFR_FORMID_PCIE_PORT12               0x4012
++#define VFR_FORMID_PCIE_PORT13               0x4013
++#define VFR_FORMID_PCIE_PORT14               0x4014
++#define VFR_FORMID_PCIE_PORT15               0x4015
++
++#define VFR_FORMID_MEMORY_RAS                0x6100
++#define VFR_FORMID_CORRECT_ERROR             0x6101
++#define VFR_FORMID_PCIE_RAS                  0x6200
++
++#define RMT_PATTERN_LENGTH                   256
++
++
++#endif
+diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h
+new file mode 100644
+index 0000000000..478821ae2c
+--- /dev/null
++++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h
+@@ -0,0 +1,84 @@
++/** @file
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++
++#ifndef _OEM_CONFIG_DATA_H_
++#define _OEM_CONFIG_DATA_H_
++
++#define PCIE_MAX_TOTAL_PORTS                 16
++#define OEM_CONFIG_NAME                      L"OemConfig"
++#define PLATFORM_SETUP_VARIABLE_FLAG         (EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE)
++
++#pragma pack(1)
++typedef struct {
++  /*Memory Config*/
++  UINT8         DdrDebugLevel;
++  UINT8         DdrFreqLimit;
++  UINT8         DdrRefreshSupport;
++  UINT8         DdrRefreshRate;
++  UINT8         RankMargin;
++  UINT8         RankMarginMode;
++  UINT32        rmtPatternLength;
++  UINT8         perbitmargin;
++  UINT8         CaMargin;
++  UINT8         CaVrefMarginOption;
++  UINT8         NumaEn;
++  UINT8         HwMemTest;
++  UINT8         DieInterleaving;
++  UINT8         ChannelInterleaving;
++  UINT8         RankInterleaving;
++  UINT8         EccSupport;
++  /*iBMC Config*/
++  UINT8         BmcWdtEnable;
++  UINT8         BmcWdtTimeout;
++  UINT8         BmcWdtAction;
++  UINT8         OSWdtEnable;
++  UINT8         OSWdtTimeout;
++  UINT8         OSWdtAction;
++  /*PCIe Config*/
++  UINT8         PcieSRIOVSupport;
++  UINT8         PciePort[PCIE_MAX_TOTAL_PORTS];
++  UINT8         PcieLinkSpeedPort[PCIE_MAX_TOTAL_PORTS];
++  UINT8         PcieLinkDeEmphasisPort[PCIE_MAX_TOTAL_PORTS];
++  UINT8         PcieLinkStatusPort[PCIE_MAX_TOTAL_PORTS];
++  UINT8         PcieLinkSpeedRateStatusPort[PCIE_MAX_TOTAL_PORTS];
++  UINT8         PcieLinkMaxPort[PCIE_MAX_TOTAL_PORTS];
++  UINT8         PcieMaxPayloadSizePort[PCIE_MAX_TOTAL_PORTS];
++  UINT8         PcieAspmPort[PCIE_MAX_TOTAL_PORTS];
++  /*Misc Config*/
++  UINT8         EnableSmmu;
++  UINT8         EnableFdtTable;
++  UINT8         EnableSpcr;
++  /*RAS Config*/
++  UINT8         EnRasSupport;
++  UINT8         EnPoison;
++  UINT8         CheckAlgorithm;
++  UINT8         PatrolScrub;
++  UINT8         PatrolScrubDuration;
++  UINT8         DemandScrubMode;
++  UINT8         CorrectErrorThreshold;
++  UINT8         AdvanceDeviceCorrection;
++  UINT8         RankSparing;
++  UINT8         FunnelPeriod;
++  UINT8         DpcFeature;
++  UINT8         EcrcFeature;
++  UINT8         CompletionTimeout;
++  UINT8         CompletionTimeoutValue;
++  UINT8         HotPlug;
++
++} OEM_CONFIG_DATA;
++#pragma pack()
++
++#endif
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c
+new file mode 100644
+index 0000000000..1e3635307c
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c
+@@ -0,0 +1,363 @@
++/** @file
++The OEM config reference implementation
++
++Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++Copyright (c) 2018, Linaro Limited. All rights reserved.
++This program and the accompanying materials
++are licensed and made available under the terms and conditions of the BSD License
++which accompanies this distribution.  The full text of the license may be found at
++http://opensource.org/licenses/bsd-license.php
++
++THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#include "OemConfig.h"
++
++OEM_CONFIG_CALLBACK_DATA    mOemConfigPrivate = {
++  OEM_CONFIG_CALLBACK_DATA_SIGNATURE,
++  NULL,
++  NULL,
++  {
++    OemExtractConfig,
++    OemRouteConfig,
++    OemCallback
++  }
++};
++
++HII_VENDOR_DEVICE_PATH  mOemHiiVendorDevicePath = {
++  {
++    {
++      HARDWARE_DEVICE_PATH,
++      HW_VENDOR_DP,
++      {
++        (UINT8) (sizeof (VENDOR_DEVICE_PATH)),
++        (UINT8) ((sizeof (VENDOR_DEVICE_PATH)) >> 8)
++      }
++    },
++    { 0x874c4dcb, 0x08ec, 0x4fe6, { 0xb5, 0x8e, 0x3a, 0x9e, 0x1c, 0x26, 0x70, 0xb9 } }
++  },
++  {
++    END_DEVICE_PATH_TYPE,
++    END_ENTIRE_DEVICE_PATH_SUBTYPE,
++    {
++      (UINT8) (END_DEVICE_PATH_LENGTH),
++      (UINT8) ((END_DEVICE_PATH_LENGTH) >> 8)
++    }
++  }
++};
++
++
++
++
++
++
++/**
++  This function allows a caller to extract the current configuration for one
++  or more named elements from the target driver.
++
++
++  @param This            Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
++  @param Request         A null-terminated Unicode string in <ConfigRequest> format.
++  @param Progress        On return, points to a character in the Request string.
++                         Points to the string's null terminator if request was successful.
++                         Points to the most recent '&' before the first failing name/value
++                         pair (or the beginning of the string if the failure is in the
++                         first name/value pair) if the request was not successful.
++  @param Results         A null-terminated Unicode string in <ConfigAltResp> format which
++                         has all values filled in for the names in the Request string.
++                         String to be allocated by the called function.
++
++  @retval  EFI_INVALID_PARAMETER  Request is illegal syntax, or unknown name.
++  @retval  EFI_NOT_FOUND          Routing data doesn't match any storage in this driver.
++
++**/
++EFI_STATUS
++EFIAPI
++OemExtractConfig (
++  IN  CONST EFI_HII_CONFIG_ACCESS_PROTOCOL   *This,
++  IN  CONST EFI_STRING                       Request,
++  OUT EFI_STRING                             *Progress,
++  OUT EFI_STRING                             *Results
++  )
++{
++  if (Progress == NULL || Results == NULL) {
++    return EFI_INVALID_PARAMETER;
++  }
++  *Progress = Request;
++  return EFI_NOT_FOUND;
++}
++
++/**
++  This function processes the results of changes in configuration.
++
++  @param This            Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
++  @param Configuration   A null-terminated Unicode string in <ConfigResp> format.
++  @param Progress        A pointer to a string filled in with the offset of the most
++                         recent '&' before the first failing name/value pair (or the
++                         beginning of the string if the failure is in the first
++                         name/value pair) or the terminating NULL if all was successful.
++
++  @retval  EFI_INVALID_PARAMETER  Configuration is NULL.
++  @retval  EFI_NOT_FOUND          Routing data doesn't match any storage in this driver.
++
++**/
++EFI_STATUS
++EFIAPI
++OemRouteConfig (
++  IN  CONST EFI_HII_CONFIG_ACCESS_PROTOCOL   *This,
++  IN  CONST EFI_STRING                       Configuration,
++  OUT EFI_STRING                             *Progress
++  )
++{
++  if (Configuration == NULL || Progress == NULL) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  *Progress = Configuration;
++
++  return EFI_NOT_FOUND;
++}
++
++/**
++  This function is invoked if user selected a interactive opcode from Device Manager's
++  Formset. If user set VBIOS, the new value is saved to EFI variable.
++
++  @param This            Points to the EFI_HII_CONFIG_ACCESS_PROTOCOL.
++  @param Action          Specifies the type of action taken by the browser.
++  @param QuestionId      A unique value which is sent to the original exporting driver
++                         so that it can identify the type of data to expect.
++  @param Type            The type of value for the question.
++  @param Value           A pointer to the data being sent to the original exporting driver.
++  @param ActionRequest   On return, points to the action requested by the callback function.
++
++  @retval  EFI_SUCCESS           The callback successfully handled the action.
++  @retval  EFI_INVALID_PARAMETER The setup browser call this function with invalid parameters.
++
++**/
++EFI_STATUS
++EFIAPI
++OemCallback (
++  IN  CONST EFI_HII_CONFIG_ACCESS_PROTOCOL   *This,
++  IN  EFI_BROWSER_ACTION                     Action,
++  IN  EFI_QUESTION_ID                        QuestionId,
++  IN  UINT8                                  Type,
++  IN  EFI_IFR_TYPE_VALUE                     *Value,
++  OUT EFI_BROWSER_ACTION_REQUEST             *ActionRequest
++  )
++{
++  if (Action != EFI_BROWSER_ACTION_CHANGING) {
++    //
++    // Do nothing for other UEFI Action. Only do call back when data is changed.
++    //
++    return EFI_UNSUPPORTED;
++  }
++  if ((Value == NULL) || (ActionRequest == NULL)) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  return EFI_SUCCESS;
++}
++
++/**
++  Install Boot Manager Menu driver.
++
++  @param ImageHandle     The image handle.
++  @param SystemTable     The system table.
++
++  @retval  EFI_SUCEESS  Install Boot manager menu success.
++  @retval  Other        Return error status.
++
++**/
++EFI_STATUS
++EFIAPI
++OemConfigUiLibConstructor (
++  IN EFI_HANDLE                            ImageHandle,
++  IN EFI_SYSTEM_TABLE                      *SystemTable
++  )
++{
++  EFI_STATUS                  Status;
++  OEM_CONFIG_DATA             Configuration;
++  VOID                        *Hob;
++  VERSION_INFO                *VersionInfo;
++  UINTN                       BufSize;
++  BOOLEAN                     Action;
++  EFI_STRING                  ConfigRequestHdr;
++  EFI_TIME                    Time = {0};
++  CHAR16                      TmpString[0x100] = {0};
++
++  mOemConfigPrivate.DriverHandle = NULL;
++  Status = gBS->InstallMultipleProtocolInterfaces (
++                  &mOemConfigPrivate.DriverHandle,
++                  &gEfiDevicePathProtocolGuid,
++                  &mOemHiiVendorDevicePath,
++                  &gEfiHiiConfigAccessProtocolGuid,
++                  &mOemConfigPrivate.ConfigAccess,
++                  NULL
++                  );
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++
++  //
++  // Publish our HII data.
++  //
++  mOemConfigPrivate.HiiHandle = HiiAddPackages (
++                                   &gOemConfigGuid,
++                                   mOemConfigPrivate.DriverHandle,
++                                   OemConfigVfrBin,
++                                   OemConfigUiLibStrings,
++                                   NULL
++                                   );
++  if (mOemConfigPrivate.HiiHandle == NULL) {
++    DEBUG ((DEBUG_ERROR, "OemConfigUiLibConstructor(), Fail to Add Oem Hii Package.\n"));
++    return EFI_INVALID_PARAMETER;
++  }
++  //
++  //BIOS Build Time Init
++  //
++  Hob = GetFirstGuidHob (&gVersionInfoHobGuid);
++  if (Hob == NULL) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%d] Version information HOB not found!\n",
++      __FILE__, __LINE__));
++    return EFI_NOT_FOUND;
++  }
++  VersionInfo = GET_GUID_HOB_DATA (Hob);
++  Time = VersionInfo->BuildTime;
++  UnicodeSPrint (
++    TmpString,
++    sizeof (TmpString),
++    L"%02d/%02d/%04d %02d:%02d",
++    Time.Month,
++    Time.Day,
++    Time.Year,
++    Time.Hour,
++    Time.Minute
++    );
++  HiiSetString (
++    mOemConfigPrivate.HiiHandle,
++    STRING_TOKEN (STR_MISC_BIOS_BUILDTIME),
++    TmpString,
++    "en-US"
++    );
++  //
++  // Check Oem Config Variable.
++  //
++  ConfigRequestHdr = HiiConstructConfigHdr (
++                       &gOemConfigGuid,
++                       OEM_CONFIG_NAME,
++                       mOemConfigPrivate.DriverHandle
++                       );
++  ZeroMem (&Configuration, sizeof (OEM_CONFIG_DATA));
++  BufSize = sizeof (OEM_CONFIG_DATA);
++  Status = gRT->GetVariable (
++                  OEM_CONFIG_NAME,
++                  &gOemConfigGuid,
++                  NULL,
++                  &BufSize,
++                  &Configuration
++                  );
++  if (EFI_ERROR (Status)) {
++    Action = HiiSetToDefaults (ConfigRequestHdr, EFI_HII_DEFAULT_CLASS_STANDARD);
++    if (!Action) {
++      //
++      //Set the default value of the DDR option
++      //
++      Configuration.DdrDebugLevel = 0;
++      Configuration.DdrFreqLimit = 0;
++      Configuration.DdrRefreshSupport = 0;
++      Configuration.DdrRefreshRate = 0;
++      Configuration.RankMargin = 0;
++      Configuration.RankMarginMode = 2;
++      Configuration.rmtPatternLength = 256;
++      Configuration.perbitmargin = 0x0;
++      Configuration.CaMargin = 0x0;
++      Configuration.CaVrefMarginOption = 0x0;
++      Configuration.NumaEn = 1;
++      Configuration.HwMemTest = 0;
++      Configuration.DieInterleaving = 0;
++      Configuration.ChannelInterleaving = 1;
++      Configuration.RankInterleaving = 2;
++      Configuration.EccSupport = 0;
++      //
++      //Set the default value of the BMC option
++      //
++      Configuration.BmcWdtEnable = 0;
++      Configuration.BmcWdtTimeout = 15;
++      Configuration.BmcWdtAction = 1;
++      Configuration.OSWdtEnable = 0;
++      Configuration.OSWdtTimeout = 5;
++      Configuration.OSWdtAction = 1;
++      //
++      //Set the default value of the Misc option
++      //
++      Configuration.EnableSmmu = 1;
++      Configuration.EnableFdtTable = 0;
++      Configuration.EnableSpcr = 0;
++      //
++      //Set the default value of the Ras option
++      //
++      Configuration.EnRasSupport = 1;
++      Configuration.EnPoison = 1;
++      Configuration.CheckAlgorithm = 0;
++      Configuration.PatrolScrub = 1;
++      Configuration.PatrolScrubDuration = 24;
++      Configuration.DemandScrubMode = 0;
++      Configuration.CorrectErrorThreshold = 0;
++      Configuration.AdvanceDeviceCorrection = 0;
++      Configuration.RankSparing = 0;
++      Configuration.FunnelPeriod = 0;
++      Configuration.DpcFeature = 0;
++      Configuration.EcrcFeature = 0;
++      Configuration.CompletionTimeout = 1;
++      Configuration.CompletionTimeoutValue = 0;
++      Configuration.HotPlug = 1;
++      Status = gRT->SetVariable (
++                      OEM_CONFIG_NAME,
++                      &gOemConfigGuid,
++                      EFI_VARIABLE_NON_VOLATILE | EFI_VARIABLE_BOOTSERVICE_ACCESS,
++                      sizeof (OEM_CONFIG_DATA),
++                      &Configuration
++                      );
++    }
++  } else {
++    Action = HiiValidateSettings (ConfigRequestHdr);
++    if (!Action) {
++      return EFI_INVALID_PARAMETER;
++    }
++  }
++  return EFI_SUCCESS;
++}
++
++/**
++  Unloads the application and its installed protocol.
++
++  @param  ImageHandle     Handle that identifies the image to be unloaded.
++  @param  SystemTable     The system table.
++
++  @retval EFI_SUCCESS           The image has been unloaded.
++**/
++EFI_STATUS
++EFIAPI
++OemConfigUiLibDestructor (
++  IN EFI_HANDLE                            ImageHandle,
++  IN EFI_SYSTEM_TABLE                      *SystemTable
++  )
++{
++  EFI_STATUS                  Status;
++
++  Status = gBS->UninstallMultipleProtocolInterfaces (
++                  mOemConfigPrivate.DriverHandle,
++                  &gEfiDevicePathProtocolGuid,
++                  &mOemHiiVendorDevicePath,
++                  &gEfiHiiConfigAccessProtocolGuid,
++                  &mOemConfigPrivate.ConfigAccess,
++                  NULL
++                  );
++
++  HiiRemovePackages (mOemConfigPrivate.HiiHandle);
++
++  return Status;
++}
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr
+new file mode 100644
+index 0000000000..c709975c38
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.hfr
+@@ -0,0 +1,154 @@
++/** @file
++*
++*  Memory Config form at Oem Config fromset.
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++form formid = MEMORY_CONFIG_FORM_ID,
++  title  = STRING_TOKEN(STR_MEMORY_CONFIG_FORM_TITLE);
++
++  oneof varid  = OEM_CONFIG_DATA.DdrDebugLevel,
++        prompt   = STRING_TOKEN (STR_MEM_PRINT_LEVEL_PROMPT),
++        help     = STRING_TOKEN (STR_MEM_PRINT_LEVEL_HELP),
++        option text = STRING_TOKEN (STR_MEM_PRINT_LEVEL_DISABLE),  value = 0, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN (STR_MEM_PRINT_LEVEL_MINIMUM), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++        option text = STRING_TOKEN (STR_MEM_PRINT_LEVEL_MINMAX),  value = 2, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN (STR_MEM_PRINT_LEVEL_MAXIMUM),  value = 3, flags = RESET_REQUIRED;
++  endoneof;
++
++  oneof varid = OEM_CONFIG_DATA.DdrFreqLimit,
++        prompt  = STRING_TOKEN(STR_XMP_DDR_FREQ_LIMIT_PROMPT),
++        help    = STRING_TOKEN(STR_XMP_DDR_FREQ_LIMIT_HELP),
++        option text = STRING_TOKEN(STR_AUTO), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_DDR_FREQ_1333_STRING), value = 5, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_DDR_FREQ_1600_STRING), value = 7, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_DDR_FREQ_1866_STRING), value = 9, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_DDR_FREQ_2133_STRING), value = 11, flags = RESET_REQUIRED ;
++        option text = STRING_TOKEN(STR_DDR_FREQ_2400_STRING), value = 13, flags = RESET_REQUIRED ;
++        option text = STRING_TOKEN(STR_DDR_FREQ_2667_STRING), value = 15, flags = RESET_REQUIRED ;
++        option text = STRING_TOKEN(STR_DDR_FREQ_2933_STRING), value = 17, flags = RESET_REQUIRED ;
++        option text = STRING_TOKEN(STR_DDR_FREQ_3200_STRING), value = 19, flags = RESET_REQUIRED ;
++  endoneof;
++
++  suppressif TRUE;
++    oneof varid = OEM_CONFIG_DATA.DdrRefreshSupport,
++          prompt  = STRING_TOKEN(STR_DDR_REFRESH_SUPPORT_PROMPT),
++          help    = STRING_TOKEN(STR_DDR_REFRESH_SUPPORT_HELP),
++          option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++          option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
++    endoneof;
++
++    suppressif ideqval OEM_CONFIG_DATA.DdrRefreshSupport == 0;
++      oneof varid = OEM_CONFIG_DATA.DdrRefreshRate,
++            prompt  = STRING_TOKEN(STR_DDR_REFRESH_PROMPT),
++            help    = STRING_TOKEN(STR_DDR_REFRESH_HELP),
++            option text = STRING_TOKEN(STR_32MS), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++            option text = STRING_TOKEN(STR_64MS), value = 1, flags = RESET_REQUIRED;
++      endoneof;
++    endif;
++
++    oneof varid  = OEM_CONFIG_DATA.RankMargin,
++          prompt   = STRING_TOKEN (STR_RMT_PROMPT),
++          help     = STRING_TOKEN (STR_RMT_HELP),
++          option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;
++          option text = STRING_TOKEN (STR_ENABLE),  value = 1, flags = RESET_REQUIRED;
++    endoneof;
++
++    suppressif  ideqval OEM_CONFIG_DATA.RankMargin == 0;
++      oneof varid  = OEM_CONFIG_DATA.RankMarginMode,
++            prompt   = STRING_TOKEN (STR_RMTM_PROMPT),
++            help     = STRING_TOKEN (STR_RMTM_HELP),
++            option text = STRING_TOKEN (STR_RMTM_SFC),     value = 1, flags = RESET_REQUIRED;
++            option text = STRING_TOKEN (STR_RMTM_EXMBIST), value = 2, flags = DEFAULT | MANUFACTURING |RESET_REQUIRED;
++      endoneof;
++
++      numeric varid = OEM_CONFIG_DATA.rmtPatternLength,
++              prompt    = STRING_TOKEN (STR_RMT_PATTERN_PROMPT),
++              help      = STRING_TOKEN (STR_RMT_PATTERN_HELP),
++              flags     = RESET_REQUIRED,
++              minimum   = 1,
++              maximum   = 32767,
++              step      = 1,
++              default   = RMT_PATTERN_LENGTH,
++      endnumeric;
++
++      oneof varid  = OEM_CONFIG_DATA.perbitmargin,
++            prompt   = STRING_TOKEN (STR_PER_BIT_MARGIN_PROMPT),
++            help     = STRING_TOKEN (STR_PER_BIT_MARGIN_HELP),
++            option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++            option text = STRING_TOKEN (STR_ENABLE),  value = 1, flags = RESET_REQUIRED;
++      endoneof;
++
++      oneof varid  = OEM_CONFIG_DATA.CaMargin,
++            prompt   = STRING_TOKEN (STR_CA_MARGINS_PROMPT),
++            help     = STRING_TOKEN (STR_CA_MARGINS_HELP),
++            option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++            option text = STRING_TOKEN (STR_ENABLE),  value = 1, flags = RESET_REQUIRED;
++      endoneof;
++
++      oneof varid  = OEM_CONFIG_DATA.CaVrefMarginOption,
++            prompt   = STRING_TOKEN (STR_CAVREF_MARGINS_PROMPT),
++            help     = STRING_TOKEN (STR_CAVREF_MARGINS_HELP),
++            option text = STRING_TOKEN (STR_CAVREF_MARGINS_OPTION0), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++            option text = STRING_TOKEN (STR_CAVREF_MARGINS_OPTION2),  value = 1, flags = RESET_REQUIRED;
++      endoneof;
++    endif;
++
++    oneof varid = OEM_CONFIG_DATA.DieInterleaving,
++          prompt  = STRING_TOKEN(STR_DIE_INTERLEAVING_PROMPT),
++          help    = STRING_TOKEN(STR_DIE_INTERLEAVING_HELP),
++          option text = STRING_TOKEN(STR_DISABLE),               value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++          option text = STRING_TOKEN(STR_ENABLE),                value = 1, flags = RESET_REQUIRED;
++    endoneof;
++
++    oneof varid = OEM_CONFIG_DATA.ChannelInterleaving,
++          prompt  = STRING_TOKEN(STR_CHANNEL_INTERLEAVING_PROMPT),
++          help    = STRING_TOKEN(STR_CHANNEL_INTERLEAVING_HELP),
++          option text = STRING_TOKEN(STR_DISABLE),               value = 0, flags = RESET_REQUIRED;
++          option text = STRING_TOKEN(STR_ENABLE),                value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++    endoneof;
++
++    oneof varid = OEM_CONFIG_DATA.RankInterleaving,
++          prompt  = STRING_TOKEN(STR_RANK_INTERLEAVING_PROMPT),
++          help    = STRING_TOKEN(STR_RANK_INTERLEAVING_HELP),
++          option text = STRING_TOKEN(STR_1WAY_STRING),           value = 1, flags = RESET_REQUIRED;
++          option text = STRING_TOKEN(STR_2WAY_STRING),           value = 2, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++          option text = STRING_TOKEN(STR_4WAY_STRING),           value = 4, flags = RESET_REQUIRED;
++    endoneof;
++
++    oneof varid = OEM_CONFIG_DATA.NumaEn,
++          prompt  = STRING_TOKEN(STR_NUMA_PROMPT),
++          help    = STRING_TOKEN(STR_NUMA_HELP),
++          option text = STRING_TOKEN(STR_DISABLE),      value = 0,  flags = RESET_REQUIRED;
++          option text = STRING_TOKEN(STR_ENABLE),       value = 1,  flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++    endoneof;
++
++    oneof varid  = OEM_CONFIG_DATA.HwMemTest,
++          prompt   = STRING_TOKEN (STR_MEM_TEST_PROMPT),
++          help     = STRING_TOKEN (STR_MEM_TEST_HELP),
++          option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++          option text = STRING_TOKEN (STR_ENABLE),  value = 1, flags = RESET_REQUIRED;
++    endoneof;
++
++    oneof varid  = OEM_CONFIG_DATA.EccSupport,
++          prompt   = STRING_TOKEN (STR_ECC_SUPPORT_PROMPT),
++          help     = STRING_TOKEN (STR_ECC_SUPPORT_HELP),
++          option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++          option text = STRING_TOKEN (STR_ECC_EN),  value = 1, flags = RESET_REQUIRED;
++          option text = STRING_TOKEN (STR_SDEC_EN),  value = 2, flags = RESET_REQUIRED;
++    endoneof;
++  endif;
++
++endform;
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni
+new file mode 100644
+index 0000000000..0ecf5e59cf
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MemoryConfig.uni
+@@ -0,0 +1,103 @@
++/** @file
++*
++*  String definitions for the Memory Config.
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++/=#
++
++#langdef   en-US "English"
++
++#string STR_MEMORY_CONFIG_FORM_TITLE        #language en-US "Memory Configuration"
++#string STR_MEMORY_CONFIG_FORM_HELP         #language en-US "Displays and provides option to change the Memory Settings"
++#string STR_MEMORY_RAS_CONFIG_FORM_TITLE    #language en-US "Memory RAS Configuration"
++#string STR_MEMORY_RAS_CONFIG_FORM_HELP     #language en-US "Displays and provides option to change the Ras Configuration"
++#string STR_MEM_PRINT_LEVEL_PROMPT          #language en-US "Memory Print Level"
++#string STR_MEM_PRINT_LEVEL_HELP            #language en-US "Memory Print Level Set. Disable: Do not print any MRC statement/ Minimum: Print the most important(High level) MRC statement/ Minmax: Print the Mid-important(Mid level) and most important MRC statement/ Maximum: Print all of the MRC statement"
++#string STR_ENABLE                          #language en-US  "Enabled"
++#string STR_DISABLE                         #language en-US  "Disabled"
++
++#string STR_MEM_PRINT_LEVEL_MINIMUM         #language en-US "Minimum"
++#string STR_MEM_PRINT_LEVEL_MINMAX          #language en-US "Minmax"
++#string STR_MEM_PRINT_LEVEL_MAXIMUM         #language en-US "Maximum"
++#string STR_MEM_PRINT_LEVEL_DISABLE         #language en-US "Disable"
++
++#string STR_XMP_DDR_FREQ_LIMIT_PROMPT       #language en-US "Memory Frequency"
++#string STR_XMP_DDR_FREQ_LIMIT_HELP         #language en-US "Maximum Memory Frequency Selections in Mhz. Do not select Reserved"
++#string STR_AUTO                            #language en-US "Auto"
++#string STR_DDR_FREQ_1333_STRING            #language en-US "1333"
++#string STR_DDR_FREQ_1600_STRING            #language en-US "1600"
++#string STR_DDR_FREQ_1866_STRING            #language en-US "1866"
++#string STR_DDR_FREQ_2133_STRING            #language en-US "2133"
++#string STR_DDR_FREQ_2400_STRING            #language en-US "2400"
++#string STR_DDR_FREQ_2600_STRING            #language en-US "2600"
++#string STR_DDR_FREQ_2667_STRING            #language en-US "2667"
++#string STR_DDR_FREQ_2800_STRING            #language en-US "2800"
++#string STR_DDR_FREQ_2933_STRING            #language en-US "2993"
++#string STR_DDR_FREQ_3000_STRING            #language en-US "3000"
++#string STR_DDR_FREQ_3200_STRING            #language en-US "3200"
++
++#string STR_DDR_REFRESH_SUPPORT_PROMPT      #language en-US "Custom Refresh Enable"
++#string STR_DDR_REFRESH_SUPPORT_HELP        #language en-US "Memory Custom Refresh Enable "
++#string STR_DDR_REFRESH_PROMPT              #language en-US "Custom Refresh Rate"
++#string STR_DDR_REFRESH_HELP                #language en-US "Memory Custom Refresh Rate "
++#string STR_32MS                            #language en-US "32ms"
++#string STR_64MS                            #language en-US "64ms"
++
++#string STR_RMT_PROMPT                      #language en-US "Rank Margin Tool"
++#string STR_RMT_HELP                        #language en-US "Enable the rank margin tool to run after DDR memory training"
++#string STR_RMTM_PROMPT                     #language en-US "Rank Margin Mode"
++#string STR_RMTM_HELP                       #language en-US "Select test mode for rank margin test"
++#string STR_RMTM_SFC                        #language en-US "SFC"
++#string STR_RMTM_EXMBIST                    #language en-US "EXMBIST"
++#string STR_RMT_PATTERN_PROMPT              #language en-US "RMT Pattern Length"
++#string STR_RMT_PATTERN_HELP                #language en-US "Set the pattern length(1-32767) for the Rank Margin Tool"
++#string STR_PER_BIT_MARGIN_PROMPT           #language en-US "Per Bit Margin"
++#string STR_PER_BIT_MARGIN_HELP             #language en-US "Enables the logging from the serial port of DDR Per Bit Margin Data"
++#string STR_CA_MARGINS_PROMPT               #language en-US "CA Margin"
++#string STR_CA_MARGINS_HELP                 #language en-US "Enables CA margin"
++#string STR_CAVREF_MARGINS_PROMPT           #language en-US "CAVref Margin"
++#string STR_CAVREF_MARGINS_HELP             #language en-US "CAVref margin Options"
++#string STR_CAVREF_MARGINS_OPTION0          #language en-US "VDD/2^2 connected to QVrefVA and BVrefCA"
++#string STR_CAVREF_MARGINS_OPTION2          #language en-US "Internally generated Vref connected to QVrefCA^3 VDD/2^2 connected to BVrefCA"
++
++#string STR_DIE_INTERLEAVING_PROMPT         #language en-US "Die Interleaving"
++#string STR_DIE_INTERLEAVING_HELP           #language en-US "Select Die Interleaving setting"
++#string STR_CHANNEL_INTERLEAVING_PROMPT     #language en-US "Channel Interleaving"
++#string STR_CHANNEL_INTERLEAVING_HELP       #language en-US "Select Channel Interleaving setting"
++#string STR_RANK_INTERLEAVING_PROMPT        #language en-US "Rank Interleaving"
++#string STR_RANK_INTERLEAVING_HELP          #language en-US "Select Rank Interleaving setting"
++
++#string STR_1WAY_STRING                     #language en-US "1-way Interleave"
++#string STR_2WAY_STRING                     #language en-US "2-way Interleave"
++#string STR_3WAY_STRING                     #language en-US "3-way Interleave"
++#string STR_4WAY_STRING                     #language en-US "4-way Interleave"
++#string STR_6WAY_STRING                     #language en-US "6-way Interleave"
++#string STR_8WAY_STRING                     #language en-US "8-way Interleave"
++
++#string STR_NUMA_PROMPT                     #language en-US "NUMA"
++#string STR_NUMA_HELP                       #language en-US "Enable or Disable Non uniform Memory Access (NUMA)."
++
++#string STR_MEM_TEST_PROMPT                 #language en-US "Memory Test"
++#string STR_MEM_TEST_HELP                   #language en-US "Enable/disable memory test during normal boot"
++
++#string STR_ECC_SUPPORT_PROMPT              #language en-US "ECC/SDEC Support"
++#string STR_ECC_SUPPORT_HELP                #language en-US "Enable/disable DDR Ecc/SDEC Support"
++#string STR_ECC_EN                          #language en-US "Ecc Enable"
++#string STR_SDEC_EN                         #language en-US "SDEC Enable"
++
++
++
++
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr
+new file mode 100644
+index 0000000000..9e3ac73116
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr
+@@ -0,0 +1,41 @@
++/** @file
++*
++*  Misc Config form at Oem Config fromset.
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++form formid = MISC_CONFIG_FORM_ID,
++  title  = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE);
++
++    oneof varid   = OEM_CONFIG_DATA.EnableSmmu,
++      prompt      = STRING_TOKEN(STR_OEM_TABLE),
++      help        = STRING_TOKEN(STR_OEM_CONFIG_HELP),
++      option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = 0;
++      option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = DEFAULT;
++    endoneof;
++
++    oneof varid   = OEM_CONFIG_DATA.EnableFdtTable,
++      prompt      = STRING_TOKEN(STR_FDT_TABLE),
++      help        = STRING_TOKEN(STR_FDT_CONFIG_HELP),
++      option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT;
++      option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = 0;
++    endoneof;
++
++    oneof varid   = OEM_CONFIG_DATA.EnableSpcr,
++      prompt      = STRING_TOKEN(STR_ENABLE_SPCR_TABLE),
++      help        = STRING_TOKEN(STR_ENABLE_SPCR_HELP),
++      option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT;
++      option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = 0;
++    endoneof;
++
++endform;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni
+new file mode 100644
+index 0000000000..53eb1622c4
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni
+@@ -0,0 +1,27 @@
++/** @file
++*
++*  String definitions for the Misc Config form.
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#langdef   en-US "English"
++
++#string STR_OEM_TABLE                  #language en-US  "Support Smmu"
++#string STR_OEM_CONFIG_HELP            #language en-US  "Enable or Disable Smmu."
++#string STR_FDT_TABLE                  #language en-US  "Install DTB Table"
++#string STR_FDT_CONFIG_HELP            #language en-US  "Enable or Disable Fdt Table."
++#string STR_ENABLE_SPCR_TABLE          #language en-US  "Support SPCR"
++#string STR_ENABLE_SPCR_HELP           #language en-US  "Enable or Disable SPCR Table."
++#string STR_ENABLE_GOP_FRAME_BUFFER    #language en-US  "Support GOP FB"
++#string STR_ENABLE_GOP_FRAME_BUFFER_HELP     #language en-US  "Enable or Disable GOP frame buffer."
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni
+new file mode 100644
+index 0000000000..0b2c63a625
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLib.uni
+@@ -0,0 +1,24 @@
++/** @file
++*
++*  OEM Config Library used by UiApp
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#string STR_MODULE_ABSTRACT
++#language en-US              "OEM Config Library used by BDS"
++
++#string STR_MODULE_DESCRIPTION
++#language en-US              "OEM Config Library used by BDS"
++
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni
+new file mode 100644
+index 0000000000..afc048e6cd
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigUiLibStrings.uni
+@@ -0,0 +1,42 @@
++/** @file
++*
++*  String definitions for the OEM Config.
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++/=#
++
++#langdef   en-US "English"
++
++#string STR_EMPTY_STRING               #language en-US  ""
++#string STR_BIOS_BUILDTIME_STRING      #language en-US  "Build Date"
++#string STR_MISC_BIOS_BUILDTIME        #language en-US  ""
++#string SYSTEM_TIME                    #language en-US  "System Time"
++#string SYSTEM_TIME_HELP               #language en-US  "System Time (HH:MM:SS)"
++#string SYSTEM_DATE                    #language en-US  "System Date"
++#string SYSTEM_DATE_HELP               #language en-US  "System Date (MM/DD/YYYY) Use [ENTER],[TAB] or [SHIFT-TAB] to select a field. Use [+] or [-] to configure system Time."
++#string STR_OEM_CONFIG                 #language en-US  "Oem Config"
++#string STR_ENABLED                    #language en-US  "Enabled"
++#string STR_DISABLED                   #language en-US  "Disabled"
++#string STR_MEMORY_CONFIG_FORM_TITLE   #language en-US  "Memory Config"
++#string STR_MEMORY_CONFIG_FORM_HELP    #language en-US  "Display Memory DIMM information."
++#string STR_PCIE_CONFIG_FORM_TITLE     #language en-US  "PCIe Config"
++#string STR_PCIE_CONFIG_FORM_HELP      #language en-US  "Display PCIe information."
++#string STR_MISC_CONFIG_FORM_TITLE     #language en-US  "MISC Config"
++#string STR_MISC_CONFIG_FORM_HELP      #language en-US  "Include SMMU Support Enable and Change the boot manner of DTB/ACPI."
++#string STR_IBMC_CONFIG_FORM_TITLE     #language en-US  "IBMC Config"
++#string STR_IBMC_CONFIG_FORM_HELP      #language en-US  "Include IBMC WDT(Watchdog Timer) Config."
++#string STR_RAS_CONFIG_FORM_TITLE      #language en-US  "RAS Config"
++#string STR_RAS_CONFIG_FORM_HELP       #language en-US  "Displays and provides option to change the Ras Configuration"
++#string STR_EXIT_STRING                #language en-US  "Press ESC to exit."
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.Vfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.Vfr
+new file mode 100644
+index 0000000000..470e9ace3d
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfigVfr.Vfr
+@@ -0,0 +1,89 @@
++/** @file
++*
++*  OEM Config formset.
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++#include "OemConfigUi.h"
++#include "Library/OemConfigData.h"
++
++formset
++  guid      = gOemConfigGuid,
++  title     = STRING_TOKEN(STR_OEM_CONFIG),
++  help      = STRING_TOKEN(STR_OEM_CONFIG),
++  classguid = gEfiIfrFrontPageGuid,  // for MdeModule Bds.
++  efivarstore OEM_CONFIG_DATA,
++    attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_NON_VOLATILE,
++    name  = OemConfig,
++    guid  = gOemConfigGuid;
++
++  form formid = OEM_CONFIG_FORM_ID,
++    title  = STRING_TOKEN(STR_OEM_CONFIG);
++
++    grayoutif  TRUE;
++      text
++        help   = STRING_TOKEN(STR_EMPTY_STRING),
++        text   = STRING_TOKEN(STR_BIOS_BUILDTIME_STRING),
++        text   = STRING_TOKEN(STR_MISC_BIOS_BUILDTIME),
++        flags  = 0,
++        key    = 0;
++    endif;
++
++    date
++      prompt  = STRING_TOKEN(SYSTEM_DATE),
++      help    = STRING_TOKEN(SYSTEM_DATE_HELP),
++      flags   = 0x10,
++      default = 2017/1/1,
++    enddate;
++
++    time
++      prompt  = STRING_TOKEN(SYSTEM_TIME),
++      help    = STRING_TOKEN(SYSTEM_TIME_HELP),
++      flags   = 0x10,
++    endtime;
++
++    subtitle text = STRING_TOKEN(STR_EMPTY_STRING);
++
++    goto MEMORY_CONFIG_FORM_ID,
++      prompt = STRING_TOKEN(STR_MEMORY_CONFIG_FORM_TITLE),
++      help   = STRING_TOKEN(STR_MEMORY_CONFIG_FORM_HELP);
++
++    goto IBMC_CONFIG_FORM_ID,
++      prompt = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE),
++      help   = STRING_TOKEN(STR_IBMC_CONFIG_FORM_HELP);
++
++    suppressif TRUE;
++    goto PCIE_CONFIG_FORM_ID,
++      prompt  = STRING_TOKEN(STR_PCIE_CONFIG_FORM_TITLE),
++      help    = STRING_TOKEN(STR_PCIE_CONFIG_FORM_HELP);
++    endif;
++
++    goto MISC_CONFIG_FORM_ID,
++      prompt  = STRING_TOKEN(STR_MISC_CONFIG_FORM_TITLE),
++      help    = STRING_TOKEN(STR_MISC_CONFIG_FORM_HELP);
++
++    goto RAS_CONFIG_FORM_ID,
++      prompt  = STRING_TOKEN(STR_RAS_CONFIG_FORM_TITLE),
++      help    = STRING_TOKEN(STR_RAS_CONFIG_FORM_HELP);
++
++    subtitle text = STRING_TOKEN(STR_EMPTY_STRING);
++    subtitle text = STRING_TOKEN(STR_EXIT_STRING);
++
++  endform;
++
++#include "MemoryConfig.hfr"
++#include "iBMCConfig.hfr"
++#include "PcieConfig.hfr"
++#include "MiscConfig.hfr"
++#include "RasConfig.hfr"
++endformset;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr
+new file mode 100644
+index 0000000000..7cf7cdd29b
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfig.hfr
+@@ -0,0 +1,219 @@
++/** @file
++*
++*  PCIe Config form at Oem Config fromset.
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++form formid = PCIE_CONFIG_FORM_ID,
++  title   = STRING_TOKEN (STR_PCIE_CONFIG_FORM_TITLE);
++
++  goto VFR_FORMID_PCIE_SOCKET0,
++    prompt  = STRING_TOKEN (STR_PCIE_CPU_0_PROMPT),
++    help    = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP);
++
++  goto VFR_FORMID_PCIE_SOCKET1,
++    prompt  = STRING_TOKEN (STR_PCIE_CPU_1_PROMPT),
++    help    = STRING_TOKEN (STR_PCIE_CPU_PROMPT_HELP);
++
++  oneof varid  = OEM_CONFIG_DATA.PcieSRIOVSupport,
++        prompt   = STRING_TOKEN (STR_SRIOV_SUPPORT_PROMPT),
++        help     = STRING_TOKEN (STR_SRIOV_SUPPORT_HELP),
++        option text = STRING_TOKEN (STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++        option text = STRING_TOKEN (STR_ENABLE),  value = 1, flags = RESET_REQUIRED;
++  endoneof;
++
++endform;
++
++form formid = VFR_FORMID_PCIE_SOCKET0,
++  title = STRING_TOKEN(STR_PCIE_CPU_0_PROMPT);
++
++  goto VFR_FORMID_PCIE_PORT2,
++    prompt  = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT),
++    help    = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
++
++  goto VFR_FORMID_PCIE_PORT4,
++    prompt  = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT),
++    help    = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
++
++  goto VFR_FORMID_PCIE_PORT5,
++    prompt  = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT),
++    help    = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
++
++  goto VFR_FORMID_PCIE_PORT6,
++    prompt  = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT),
++    help    = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
++
++  goto VFR_FORMID_PCIE_PORT7,
++    prompt  = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT),
++    help    = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
++
++endform;
++
++form formid = VFR_FORMID_PCIE_SOCKET1,
++  title = STRING_TOKEN(STR_PCIE_CPU_1_PROMPT);
++  goto VFR_FORMID_PCIE_PORT10,
++    prompt  = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT),
++    help    = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
++
++  goto VFR_FORMID_PCIE_PORT12,
++    prompt  = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT),
++    help    = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
++
++  goto VFR_FORMID_PCIE_PORT13,
++    prompt  = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT),
++    help    = STRING_TOKEN(STR_PCIE_PORT_PROMPT_HELP);
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT0,
++  title = STRING_TOKEN(STR_PCIE_PORT_0_PROMPT);
++  #undef  INDEX
++  #define INDEX   0
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT1,
++  title = STRING_TOKEN(STR_PCIE_PORT_1_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   1
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT2,
++  title = STRING_TOKEN(STR_PCIE_PORT_2_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   2
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT3,
++  title = STRING_TOKEN(STR_PCIE_PORT_3_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   3
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT4,
++  title = STRING_TOKEN(STR_PCIE_PORT_4_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   4
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT5,
++  title = STRING_TOKEN(STR_PCIE_PORT_5_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   5
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT6,
++  title = STRING_TOKEN(STR_PCIE_PORT_6_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   6
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT7,
++  title = STRING_TOKEN(STR_PCIE_PORT_7_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   7
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT8,
++  title = STRING_TOKEN(STR_PCIE_PORT_8_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   8
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT9,
++  title = STRING_TOKEN(STR_PCIE_PORT_9_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   9
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT10,
++  title = STRING_TOKEN(STR_PCIE_PORT_10_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   10
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT11,
++  title = STRING_TOKEN(STR_PCIE_PORT_11_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   11
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT12,
++  title = STRING_TOKEN(STR_PCIE_PORT_12_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   12
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT13,
++  title = STRING_TOKEN(STR_PCIE_PORT_13_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   13
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT14,
++  title = STRING_TOKEN(STR_PCIE_PORT_14_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   14
++  #include "PciePortConfig.hfr"
++
++endform;
++
++form formid = VFR_FORMID_PCIE_PORT15,
++  title = STRING_TOKEN(STR_PCIE_PORT_15_PROMPT);
++
++  #undef  INDEX
++  #define INDEX   15
++  #include "PciePortConfig.hfr"
++
++endform;
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni
+new file mode 100644
+index 0000000000..d87d30f975
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PcieConfigStrings.uni
+@@ -0,0 +1,111 @@
++/** @file
++*
++*  String definitions for the PCIe Config form.
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++/=#
++
++#langdef   en-US "English"
++
++#string STR_BLANK_STRING                #language en-US ""
++#string STR_PCIE_CPU_PROMPT_HELP        #language en-US "Press <Enter> to config this CPU."
++#string STR_PCIE_CPU_0_NULL_PROMPT      #language en-US ""
++#string STR_PCIE_CPU_0_PROMPT           #language en-US "CPU 0 PCIE Configuration"
++#string STR_PCIE_CPU_1_PROMPT           #language en-US "CPU 1 PCIE Configuration"
++#string STR_SRIOV_SUPPORT_PROMPT        #language en-US "SRIOV"
++#string STR_SRIOV_SUPPORT_HELP          #language en-US "This option enables / disables the SRIOV function"
++
++#string STR_PCIE_PORT_PROMPT_HELP       #language en-US "Press <Enter> to config this port."
++#string STR_PCIE_PORT_0_NULL_PROMPT     #language en-US ""
++#string STR_PCIE_PORT_0_PROMPT          #language en-US "CPU 0 Pcie - Port 0"
++#string STR_PCIE_PORT_1_PROMPT          #language en-US "CPU 0 Pcie - Port 1"
++#string STR_PCIE_PORT_2_PROMPT          #language en-US "CPU 0 Pcie - Port 2"
++#string STR_PCIE_PORT_3_PROMPT          #language en-US "CPU 0 Pcie - Port 3"
++#string STR_PCIE_PORT_4_PROMPT          #language en-US "CPU 0 Pcie - Port 4"
++#string STR_PCIE_PORT_5_PROMPT          #language en-US "CPU 0 Pcie - Port 5"
++#string STR_PCIE_PORT_6_PROMPT          #language en-US "CPU 0 Pcie - Port 6"
++#string STR_PCIE_PORT_7_PROMPT          #language en-US "CPU 0 Pcie - Port 7"
++#string STR_PCIE_PORT_8_PROMPT          #language en-US "CPU 1 Pcie - Port 0"
++#string STR_PCIE_PORT_9_PROMPT          #language en-US "CPU 1 Pcie - Port 1"
++#string STR_PCIE_PORT_10_PROMPT         #language en-US "CPU 1 Pcie - Port 2"
++#string STR_PCIE_PORT_11_PROMPT         #language en-US "CPU 1 Pcie - Port 3"
++#string STR_PCIE_PORT_12_PROMPT         #language en-US "CPU 1 Pcie - Port 4"
++#string STR_PCIE_PORT_13_PROMPT         #language en-US "CPU 1 Pcie - Port 5"
++#string STR_PCIE_PORT_14_PROMPT         #language en-US "CPU 1 Pcie - Port 6"
++#string STR_PCIE_PORT_15_PROMPT         #language en-US "CPU 1 Pcie - Port 7"
++
++#string STR_PCIE_PORT_ENABLE_PROMPT_0   #language en-US "PCI-E Port"
++#string STR_PCIE_PORT_ENABLE_HELP       #language en-US "Disable is used to disable the port and hide its CFG space."
++
++#string STR_LINK_STATUS                 #language en-US "PCI-E Port Link Status"
++#string STR_LINK_STATUS_NG              #language en-US "Link Training Error"
++#string STR_LINK_STATUS_OK              #language en-US "Link Up"
++#string STR_MAXLINK_STATUS              #language en-US "PCI-E Port Link Max"
++#string STR_WIDTH1_STRING               #language en-US "X1"
++#string STR_WIDTH2_STRING               #language en-US "X2"
++#string STR_WIDTH4_STRING               #language en-US "X4"
++#string STR_WIDTH8_STRING               #language en-US "X8"
++#string STR_WIDTH16_STRING              #language en-US "X16"
++#string STR_WIDTH32_STRING              #language en-US "X32"
++
++#string STR_PCIESPEED_STATUS            #language en-US "PCI-E Port Link Speed"
++#string STR_PCIE_LINK_SPEED1_STRING     #language en-US "Gen 1 (2.5 GT/s)"
++#string STR_PCIE_LINK_SPEED2_STRING     #language en-US "Gen 2 (5 GT/s)"
++#string STR_PCIE_LINK_SPEED3_STRING     #language en-US "Gen 3 (8 GT/s)"
++
++#string STR_PCIE_PORT_DEEMPHASIS_PROMPT_0  #language en-US "PCI-E Port DeEmphasis"
++
++#string STR_PCIE_PORT_DEEMPHASIS_HELP   #language en-US "De-Emphais control for this PCIe port."
++
++#string STR_35DB                        #language en-US "-3.5 dB"
++#string STR_60DB                        #language en-US "-6.0 dB"
++
++#string STR_PCIE_PORT_ASPM_PROMPT_G     #language en-US "PCI-E ASPM Support"
++
++#string STR_PCIE_GLOBAL_ASPM_HELP       #language en-US "This option enables / disables the ASPM support for all downstream devices."
++#string STR_PCIE_PORT_ASPM_HELP         #language en-US "This option enables / disables the ASPM (L1) support for the downstream devices."
++
++#string STR_L0S_ONLY                    #language en-US "L0s Only"
++#string STR_L0S_L1_BOTH                 #language en-US "L0s & L1 Both"
++#string STR_L1_ONLY                     #language en-US "L1 Only"
++
++#string STR_PCIE_PORT_MAX_PAYLOAD_REQUEST_PROMPT    #language en-US "Max Payload Size"
++#string STR_PCIE_PORT_MAX_PAYLOAD_REQUEST_HELP      #language en-US "Set Maxpayload size to 512B if possible"
++//
++// Common Strings
++//
++#string STR_AUTO                        #language en-US "Auto"
++#string STR_X1                          #language en-US "x1"
++#string STR_X2                          #language en-US "x2"
++#string STR_X4                          #language en-US "x4"
++#string STR_X8                          #language en-US "x8"
++#string STR_X16                         #language en-US "x16"
++
++#string STR_128B                        #language en-US "128B"
++#string STR_256B                        #language en-US "256B"
++#string STR_512B                        #language en-US "512B"
++#string STR_1024B                       #language en-US "1024B"
++#string STR_2048B                       #language en-US "2048B"
++#string STR_4096B                       #language en-US "4096B"
++
++#string STR_CLEAR                       #language en-US "Clear"
++#string STR_SET                         #language en-US "Set"
++
++#string STR_PCIE_PORT_LINK_SPEED_PROMPT_0       #language en-US "Link Speed"
++#string STR_PCIE_PORT_LINK_SPEED_HELP           #language en-US "Link Speed:Gen1(2.5 GT/s)/Gen2(5 GT/s)/Gen3(8 GT/s)/GEN 4 (16 gt/s)"
++#string STR_PCIE_GEN1                           #language en-US "Gen 1 (2.5 GT/s)"
++#string STR_PCIE_GEN2                           #language en-US "Gen 2 (5 GT/s)"
++#string STR_PCIE_GEN3                           #language en-US "Gen 3 (8 GT/s)"
++#string STR_PCIE_GEN4                           #language en-US "Gen 4 (16 GT/s)"
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr
+new file mode 100644
+index 0000000000..1a8942157c
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/PciePortConfig.hfr
+@@ -0,0 +1,167 @@
++/** @file
++*
++*  PCIe Config form at Oem Config fromset.
++*
++*  Copyright (c) 2017 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017 - 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++oneof varid = OEM_CONFIG_DATA.PciePort[INDEX],
++  prompt  = STRING_TOKEN(STR_PCIE_PORT_ENABLE_PROMPT_0),
++  help    = STRING_TOKEN(STR_PCIE_PORT_ENABLE_HELP),
++  option text = STRING_TOKEN(STR_ENABLE),  value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++  option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
++endoneof;
++
++suppressif ideqval OEM_CONFIG_DATA.PciePort[INDEX] == 0x00;
++  oneof varid     = OEM_CONFIG_DATA.PcieLinkSpeedPort[INDEX],
++    prompt          = STRING_TOKEN(STR_PCIE_PORT_LINK_SPEED_PROMPT_0),
++    help            = STRING_TOKEN(STR_PCIE_PORT_LINK_SPEED_HELP),
++    option text     = STRING_TOKEN(STR_PCIE_GEN1),  value = 1, flags = DEFAULT | MANUFACTURING | RESET_REQUIRED;
++    option text     = STRING_TOKEN(STR_PCIE_GEN2),  value = 2, flags = RESET_REQUIRED;
++    option text     = STRING_TOKEN(STR_PCIE_GEN3),  value = 3, flags = RESET_REQUIRED;
++    option text     = STRING_TOKEN(STR_PCIE_GEN4),  value = 4, flags = RESET_REQUIRED;
++  endoneof;
++
++  suppressif NOT ideqval OEM_CONFIG_DATA.PcieLinkSpeedPort[INDEX] == 2;
++    oneof varid = OEM_CONFIG_DATA.PcieLinkDeEmphasisPort[INDEX],
++      prompt  = STRING_TOKEN(STR_PCIE_PORT_DEEMPHASIS_PROMPT_0),
++      help    = STRING_TOKEN(STR_PCIE_PORT_DEEMPHASIS_HELP),
++    #if ( INDEX == 0)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 1)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 3)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 4)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 6)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 7)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 8)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 9)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 11)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 14)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 15)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED;
++    #endif
++
++    #if ( INDEX == 2)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED ;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED| MANUFACTURING | DEFAULT;
++    #endif
++
++    #if ( INDEX == 5)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++    #endif
++
++    #if ( INDEX == 10)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++    #endif
++
++    #if ( INDEX == 12)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++    #endif
++
++    #if ( INDEX == 13)
++      option text = STRING_TOKEN(STR_60DB), value = 0, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_35DB), value = 1, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++    #endif
++
++    endoneof;
++  endif;
++
++  grayoutif  TRUE;
++    oneof varid = OEM_CONFIG_DATA.PcieLinkStatusPort[INDEX],
++      prompt  = STRING_TOKEN(STR_LINK_STATUS),
++      help    = STRING_TOKEN(STR_BLANK_STRING),
++      option text = STRING_TOKEN(STR_LINK_STATUS_NG), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_LINK_STATUS_OK), value = 1, flags = RESET_REQUIRED;
++    endoneof;
++
++    oneof varid = OEM_CONFIG_DATA.PcieLinkMaxPort[INDEX],
++      prompt  = STRING_TOKEN(STR_MAXLINK_STATUS),
++      help    = STRING_TOKEN(STR_BLANK_STRING),
++      option text = STRING_TOKEN(STR_WIDTH1_STRING), value = 1, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_WIDTH2_STRING), value = 2, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_WIDTH4_STRING), value = 4, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_WIDTH8_STRING), value = 8, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++    endoneof;
++
++    suppressif NOT ideqval OEM_CONFIG_DATA.PcieLinkStatusPort[INDEX] == 1;
++      oneof varid = OEM_CONFIG_DATA.PcieLinkSpeedRateStatusPort[INDEX],
++        prompt  = STRING_TOKEN(STR_PCIESPEED_STATUS),
++        help    = STRING_TOKEN(STR_BLANK_STRING),
++        option text = STRING_TOKEN(STR_PCIE_LINK_SPEED1_STRING), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_PCIE_LINK_SPEED2_STRING), value = 1, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_PCIE_LINK_SPEED3_STRING), value = 2, flags = RESET_REQUIRED;
++      endoneof;
++    endif;
++  endif;
++
++  oneof varid = OEM_CONFIG_DATA.PcieMaxPayloadSizePort[INDEX],
++    prompt  = STRING_TOKEN(STR_PCIE_PORT_MAX_PAYLOAD_REQUEST_PROMPT),
++    help    = STRING_TOKEN(STR_PCIE_PORT_MAX_PAYLOAD_REQUEST_HELP),
++      option text = STRING_TOKEN(STR_128B), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_256B), value = 1, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_512B), value = 2, flags = RESET_REQUIRED;
++  endoneof;
++
++  oneof varid = OEM_CONFIG_DATA.PcieAspmPort[INDEX],
++    prompt   = STRING_TOKEN (STR_PCIE_PORT_ASPM_PROMPT_G),
++    help     = STRING_TOKEN (STR_PCIE_GLOBAL_ASPM_HELP),
++    option text = STRING_TOKEN(STR_DISABLE),      value = 0, flags = RESET_REQUIRED | MANUFACTURING | DEFAULT;
++    option text = STRING_TOKEN(STR_L0S_ONLY),     value = 1, flags = RESET_REQUIRED;
++    option text = STRING_TOKEN(STR_L1_ONLY),      value = 2, flags = RESET_REQUIRED;
++    option text = STRING_TOKEN(STR_L0S_L1_BOTH),  value = 3, flags = RESET_REQUIRED;
++  endoneof;
++
++endif;
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr
+new file mode 100644
+index 0000000000..7c0ea53061
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.hfr
+@@ -0,0 +1,172 @@
++ ///** @file
++//
++//  Memory RAS Config form.
++//
++//  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++//  Copyright (c) 2018, Linaro Limited. All rights reserved.
++//  This program and the accompanying materials
++//  are licensed and made available under the terms and conditions of the BSD License
++//  which accompanies this distribution.  The full text of the license may be found at
++//  http://opensource.org/licenses/bsd-license.php
++//
++//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++//
++//**/
++  form formid = RAS_CONFIG_FORM_ID,
++       title  = STRING_TOKEN(STR_RAS_CONFIG_FORM_TITLE);
++
++    oneof varid = OEM_CONFIG_DATA.EnRasSupport,
++      prompt  = STRING_TOKEN(STR_SUPPORT_RAS_TITLE),
++      help    = STRING_TOKEN(STR_SUPPORT_RAS_HELP),
++      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++    endoneof;
++
++    suppressif TRUE;
++      goto VFR_FORMID_MEMORY_RAS,
++        prompt = STRING_TOKEN(STR_MEMORY_RAS_CONFIG_FORM_TITLE),
++        help   = STRING_TOKEN(STR_MEMORY_RAS_CONFIG_FORM_HELP);
++
++      goto VFR_FORMID_PCIE_RAS,
++        prompt  = STRING_TOKEN(STR_PCIE_RAS_CONFIG_FORM_TITLE),
++        help    = STRING_TOKEN(STR_PCIE_RAS_CONFIG_FORM_HELP);
++    endif;
++  endform;
++
++  form formid = VFR_FORMID_MEMORY_RAS,
++       title  = STRING_TOKEN(STR_MEMORY_RAS_CONFIG_FORM_TITLE);
++
++    oneof varid = OEM_CONFIG_DATA.CheckAlgorithm,
++      prompt  = STRING_TOKEN(STR_CHECK_ALGORITHM_PROMPT),
++      help    = STRING_TOKEN(STR_CHECK_ALGORITHM_HELP),
++      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_ECC), value = 1, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_SDEC), value = 2, flags = RESET_REQUIRED;
++    endoneof;
++
++    grayoutif ideqval OEM_CONFIG_DATA.CheckAlgorithm == 0;
++      oneof varid = OEM_CONFIG_DATA.EnPoison,
++        prompt  = STRING_TOKEN(STR_ENABLE_POISON_PROMPT),
++        help    = STRING_TOKEN(STR_ENABLE_POISON_HELP),
++        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++      endoneof;
++
++      oneof varid = OEM_CONFIG_DATA.PatrolScrub,
++        prompt  = STRING_TOKEN(STR_PATROL_SCRUB_PROMPT),
++        help    = STRING_TOKEN(STR_PATROL_SCRUB_HELP),
++        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++      endoneof;
++    endif;
++
++    grayoutif ideqval OEM_CONFIG_DATA.CheckAlgorithm == 0 OR ideqval OEM_CONFIG_DATA.PatrolScrub == 0;
++      numeric varid   = OEM_CONFIG_DATA.PatrolScrubDuration,
++        prompt  = STRING_TOKEN(STR_PATROL_SCRUB_DURATION_PROMPT),
++        help    = STRING_TOKEN(STR_PATROL_SCRUB_DURATION_HELP),
++        flags   = 0 | RESET_REQUIRED,
++        minimum = 0,
++        maximum = 24,
++        step    = 1,
++        default = 24,
++      endnumeric;
++    endif;
++
++    grayoutif ideqval OEM_CONFIG_DATA.CheckAlgorithm == 0;
++      oneof varid = OEM_CONFIG_DATA.DemandScrubMode,
++        prompt  = STRING_TOKEN(STR_DEMAND_SCRUB_PROMPT),
++        help    = STRING_TOKEN(STR_DEMAND_SCRUB_HELP),
++        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;
++      endoneof;
++    endif;
++
++    suppressif ideqval OEM_CONFIG_DATA.CheckAlgorithm == 0 OR ideqval OEM_CONFIG_DATA.CheckAlgorithm == 1;
++      goto VFR_FORMID_CORRECT_ERROR,
++        prompt = STRING_TOKEN(STR_CORRECT_ERROR_FORM_TITLE),
++        help   = STRING_TOKEN(STR_CORRECT_ERROR_FORM_HELP);
++    endif;
++  endform;
++
++
++  form formid = VFR_FORMID_CORRECT_ERROR,
++       title  = STRING_TOKEN(STR_CORRECT_ERROR_FORM_TITLE);
++
++    oneof varid = OEM_CONFIG_DATA.CorrectErrorThreshold,
++      prompt  = STRING_TOKEN(STR_CORRECT_ERROR_THRESHOLD_PROMPT),
++      help    = STRING_TOKEN(STR_CORRECT_ERROR_THRESHOLD_HELP),
++      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_500), value = 1, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_1000), value = 2, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_2000), value = 3, flags = RESET_REQUIRED;
++    endoneof;
++
++    oneof varid = OEM_CONFIG_DATA.FunnelPeriod,
++      prompt  = STRING_TOKEN(STR_FUNNEL_PERIOD_PROMPT),
++      help    = STRING_TOKEN(STR_FUNNEL_PERIOD_HELP),
++      option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_30), value = 1, flags = RESET_REQUIRED;
++      option text = STRING_TOKEN(STR_60), value = 2, flags = RESET_REQUIRED;
++    endoneof;
++
++    suppressif ideqval OEM_CONFIG_DATA.CorrectErrorThreshold == 0;
++      oneof varid = OEM_CONFIG_DATA.AdvanceDeviceCorrection ,
++        prompt  = STRING_TOKEN(STR_ADVANCE_DEVICE_CORRECTION_PROMPT),
++        help    = STRING_TOKEN(STR_ADVANCE_DEVICE_CORRECTION_HELP),
++        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_SR), value = 1, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_MR), value = 2, flags = RESET_REQUIRED;
++      endoneof;
++
++      oneof varid = OEM_CONFIG_DATA.RankSparing,
++        prompt  = STRING_TOKEN(STR_RANK_SPARING_PROMPT),
++        help    = STRING_TOKEN(STR_RANK_SPARING_HELP),
++        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;
++      endoneof;
++    endif;
++  endform;
++
++  form formid = VFR_FORMID_PCIE_RAS,
++       title  = STRING_TOKEN(STR_PCIE_RAS_CONFIG_FORM_TITLE);
++
++      oneof varid = OEM_CONFIG_DATA.DpcFeature,
++        prompt  = STRING_TOKEN(STR_DPC_FEARURE),
++        help    = STRING_TOKEN(STR_DPC_FEARURE_HELP),
++        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;
++      endoneof;
++
++      oneof varid = OEM_CONFIG_DATA.EcrcFeature,
++        prompt  = STRING_TOKEN(STR_ECRC_FEARURE),
++        help    = STRING_TOKEN(STR_ECRC_FEARURE_HELP),
++        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = RESET_REQUIRED;
++      endoneof;
++
++      oneof varid = OEM_CONFIG_DATA.CompletionTimeout,
++        prompt  = STRING_TOKEN(STR_COMPLETION_TIMEOUT),
++        help    = STRING_TOKEN(STR_COMPLETION_TIMEOUT_HELP),
++        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++      endoneof;
++
++    suppressif ideqval OEM_CONFIG_DATA.CompletionTimeout == 0;
++      oneof varid = OEM_CONFIG_DATA.CompletionTimeoutValue,
++        prompt  = STRING_TOKEN(STR_COMPLETION_TIMEOUT_VALUE),
++        help    = STRING_TOKEN(STR_COMPLETION_TIMEOUT_VALUE_HELP),
++        option text = STRING_TOKEN(STR_50US_TO_50MS), value = 0, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_50US_TO_100US), value = 1, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_1MS_TO_10MS), value = 2, flags = RESET_REQUIRED;
++      endoneof;
++    endif;
++
++      oneof varid = OEM_CONFIG_DATA.HotPlug,
++        prompt  = STRING_TOKEN(STR_HOT_PLUG),
++        help    = STRING_TOKEN(STR_HOT_PLUG_HELP),
++        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = RESET_REQUIRED;
++        option text = STRING_TOKEN(STR_ENABLE), value = 1, flags = MANUFACTURING | DEFAULT | RESET_REQUIRED;
++      endoneof;
++  endform;
++
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni
+new file mode 100644
+index 0000000000..551c65fa5f
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/RasConfig.uni
+@@ -0,0 +1,85 @@
++// /** @file
++// OEM Config Library used by UiApp
++//
++//
++//  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++//  Copyright (c) 2018, Linaro Limited. All rights reserved.
++//
++// This program and the accompanying materials are licensed and made available under
++// the terms and conditions of the BSD License that accompanies this distribution.
++// The full text of the license may be found at
++// http://opensource.org/licenses/bsd-license.php.
++//
++// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++//
++// **/
++#langdef   en-US "English"
++
++#string STR_SUPPORT_RAS_TITLE                     #language en-US  "Support RAS"
++#string STR_SUPPORT_RAS_HELP                      #language en-US  "Support memory/PCIe/CPU RAS funtions."
++
++#string STR_MEMORY_RAS_CONFIG_FORM_TITLE          #language en-US  "Memory RAS Config"
++#string STR_MEMORY_RAS_CONFIG_FORM_HELP           #language en-US  "Memory RAS Config"
++
++#string STR_PCIE_RAS_CONFIG_FORM_TITLE            #language en-US  "PCIe RAS Config"
++#string STR_PCIE_RAS_CONFIG_FORM_HELP             #language en-US  "PCIe RAS Config"
++
++#string STR_CPU_RAS_CONFIG_FORM_TITLE             #language en-US  "CPU RAS Config"
++#string STR_CPU_RAS_CONFIG_FORM_HELP              #language en-US  "CPU RAS Config"
++
++#string STR_ENABLE_POISON_PROMPT                  #language en-US  "Poison"
++#string STR_ENABLE_POISON_HELP                    #language en-US  "Enable/Disable Poison flag"
++
++#string STR_CHECK_ALGORITHM_PROMPT                #language en-US  "Check Algorithm"
++#string STR_CHECK_ALGORITHM_HELP                  #language en-US  "Set the memory check algorithm"
++#string STR_ECC                                   #language en-US  "ECC"
++#string STR_SDEC                                  #language en-US  "SDEC"
++
++#string STR_PATROL_SCRUB_PROMPT                   #language en-US  "Active Scrub"
++#string STR_PATROL_SCRUB_HELP                     #language en-US  "Enable/Disable Active Scrub"
++
++#string STR_PATROL_SCRUB_DURATION_PROMPT          #language en-US  "Active Scrub Interval"
++#string STR_PATROL_SCRUB_DURATION_HELP            #language en-US  "Selects the number of hours (0-24) required to complete full scrub. A value of zero means auto!"
++
++#string STR_DEMAND_SCRUB_PROMPT                   #language en-US  "Passive Scrub"
++#string STR_DEMAND_SCRUB_HELP                     #language en-US  "Enable/Disable Passive Scrub"
++
++#string STR_CORRECT_ERROR_FORM_TITLE              #language en-US  "Correct Error handle"
++#string STR_CORRECT_ERROR_FORM_HELP               #language en-US  "Correctable error-related configuration"
++
++#string STR_CORRECT_ERROR_THRESHOLD_PROMPT        #language en-US  "Correct Error Threshold"
++#string STR_CORRECT_ERROR_THRESHOLD_HELP          #language en-US  "Correctable error-related configuration"
++#string STR_500                                   #language en-US  "500"
++#string STR_1000                                  #language en-US  "1000"
++#string STR_2000                                  #language en-US  "2000"
++
++#string STR_FUNNEL_PERIOD_PROMPT                  #language en-US  "Funnel Period(min)"
++#string STR_FUNNEL_PERIOD_HELP                    #language en-US  "Set the Funnel function time period"
++#string STR_30                                    #language en-US  "30"
++#string STR_60                                    #language en-US  "60"
++
++#string STR_ADVANCE_DEVICE_CORRECTION_PROMPT      #language en-US  "Advance Device Correction"
++#string STR_ADVANCE_DEVICE_CORRECTION_HELP        #language en-US  "Configure the correctable error threshold alarm handling solution"
++#string STR_SR                                    #language en-US  "SR"
++#string STR_MR                                    #language en-US  "MR"
++
++#string STR_RANK_SPARING_PROMPT                   #language en-US  "Rank Sparing"
++#string STR_RANK_SPARING_HELP                     #language en-US  "Enable/Disable Rank Sparing"
++
++#string STR_DPC_FEARURE                           #language en-US  "DPC Feature"
++#string STR_DPC_FEARURE_HELP                      #language en-US  "Enable/Disable PCIE DPC(DownStream Port Containment) feature."
++
++#string STR_ECRC_FEARURE                          #language en-US  "ECRC Feature"
++#string STR_ECRC_FEARURE_HELP                     #language en-US  "Enable/Disable ECRC check feature"
++#string STR_COMPLETION_TIMEOUT                    #language en-US  "Completion Timeout"
++#string STR_COMPLETION_TIMEOUT_HELP               #language en-US  "Enable/Disable PCIE Completion Timeout feature."
++
++#string STR_COMPLETION_TIMEOUT_VALUE              #language en-US  "Completion Timeout Value"
++#string STR_COMPLETION_TIMEOUT_VALUE_HELP         #language en-US  "Set the corresponding Completion Timeout value."
++
++#string STR_HOT_PLUG                              #language en-US  "Hot-Plug"
++#string STR_HOT_PLUG_HELP                         #language en-US  "Enable/Disable PCIE Hot-plug feature."
++#string STR_50US_TO_50MS                          #language en-US  "50 us to 50 ms"
++#string STR_50US_TO_100US                         #language en-US  "50 us to 100 us"
++#string STR_1MS_TO_10MS                           #language en-US  "1 ms to 10 ms"
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr
+new file mode 100644
+index 0000000000..4d295a8593
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.hfr
+@@ -0,0 +1,81 @@
++ ///** @file
++//
++// IBMC Config form.
++//
++//  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++//  Copyright (c) 2018, Linaro Limited. All rights reserved.
++//  This program and the accompanying materials
++//  are licensed and made available under the terms and conditions of the BSD License
++//  which accompanies this distribution.  The full text of the license may be found at
++//  http://opensource.org/licenses/bsd-license.php
++//
++//  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++//  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++//
++//**/
++  form formid = IBMC_CONFIG_FORM_ID,
++       title  = STRING_TOKEN(STR_IBMC_CONFIG_FORM_TITLE);
++
++    oneof
++        varid       = OEM_CONFIG_DATA.BmcWdtEnable,
++        prompt      = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER),
++        help        = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_HELP),
++        option text = STRING_TOKEN(STR_DISABLE),  value = 0, flags = DEFAULT;
++        option text = STRING_TOKEN(STR_ENABLE),   value = 1, flags = 0;
++    endoneof;
++
++    suppressif ideqval OEM_CONFIG_DATA.BmcWdtEnable == 0;
++      numeric
++        varid       = OEM_CONFIG_DATA.BmcWdtTimeout,
++        prompt      = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_TIMEOUT),
++        help        = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_TIMEOUT_C10_HELP),
++        minimum     = 15,
++        maximum     = 25,
++        step        = 1,
++        default     = 15,
++      endnumeric;
++
++      oneof
++        varid       = OEM_CONFIG_DATA.BmcWdtAction,
++        prompt      = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_ACTION),
++        help        = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_ACTION_HELP),
++        option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_NO_ACTION),   value = 0, flags = 0;
++        option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_HARD_RESET),  value = 1, flags = DEFAULT;
++        option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_POWER_DOWN),  value = 2, flags = 0;
++        option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_POWER_CYCLE), value = 3, flags = 0;
++      endoneof;
++    endif;
++
++    suppressif TRUE;
++      oneof
++        varid       = OEM_CONFIG_DATA.OSWdtEnable,
++        prompt      = STRING_TOKEN(STR_BMC_OS_WATCHDOG_TIMER),
++        help        = STRING_TOKEN(STR_BMC_OS_WATCHDOG_TIMER_HELP),
++        option text = STRING_TOKEN(STR_DISABLE), value = 0, flags = DEFAULT;
++        option text = STRING_TOKEN(STR_ENABLE),  value = 1, flags = 0;
++      endoneof;
++    endif;
++
++    suppressif ideqval OEM_CONFIG_DATA.OSWdtEnable == 0;
++      numeric
++        varid       = OEM_CONFIG_DATA.OSWdtTimeout,
++        prompt      = STRING_TOKEN(STR_BMC_OS_WDT_TIMEOUT),
++        help        = STRING_TOKEN(STR_BMC_OS_WDT_TIMEOUT_HELP),
++        minimum     = 5,
++        maximum     = 8,
++        step        = 1,
++        default     = 5,
++      endnumeric;
++
++      oneof
++        varid       = OEM_CONFIG_DATA.OSWdtAction,
++        prompt      = STRING_TOKEN(STR_BMC_OS_WDT_ACTION),
++        help        = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_ACTION_HELP),
++        option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_NO_ACTION),   value = 0, flags = 0;
++        option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_HARD_RESET),  value = 1, flags = DEFAULT;
++        option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_POWER_DOWN),  value = 2, flags = 0;
++        option text = STRING_TOKEN(STR_BMC_WATCHDOG_TIMER_POWER_CYCLE), value = 3, flags = 0;
++      endoneof;
++    endif;
++
++  endform;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni
+new file mode 100644
+index 0000000000..e12e433760
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/iBMCConfig.uni
+@@ -0,0 +1,34 @@
++// /** @file
++// OEM Config Library used by UiApp
++//
++//
++//  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++//  Copyright (c) 2018, Linaro Limited. All rights reserved.
++//
++// This program and the accompanying materials are licensed and made available under
++// the terms and conditions of the BSD License that accompanies this distribution.
++// The full text of the license may be found at
++// http://opensource.org/licenses/bsd-license.php.
++//
++// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++//
++// **/
++#langdef   en-US "English"
++
++#string STR_BMC_WATCHDOG_TIMER                      #language en-US  "iBMC WDT Support For POST"
++#string STR_BMC_WATCHDOG_TIMER_HELP                 #language en-US  "Enable/Disable iBMC watchdog timer at start of POST."
++#string STR_BMC_WATCHDOG_TIMER_TIMEOUT              #language en-US  "iBMC WDT TimeOut For POST"
++#string STR_BMC_WATCHDOG_TIMER_TIMEOUT_C10_HELP     #language en-US  "Enter the number of minutes the system firmware has to boot the OS before it takes the Timeout Action. Valid values are from 15 to 25 minutes."
++#string STR_BMC_WATCHDOG_TIMER_ACTION               #language en-US  "iBMC WDT Action For POST"
++#string STR_BMC_WATCHDOG_TIMER_ACTION_HELP          #language en-US  "Timeout Action Choices: No Action, Hard Reset, Power Down or Power Cycle"
++#string STR_BMC_WATCHDOG_TIMER_NO_ACTION            #language en-US  "No Action"
++#string STR_BMC_WATCHDOG_TIMER_HARD_RESET           #language en-US  "Hard Reset"
++#string STR_BMC_WATCHDOG_TIMER_POWER_DOWN           #language en-US  "Power Down"
++#string STR_BMC_WATCHDOG_TIMER_POWER_CYCLE          #language en-US  "Power Cycle"
++#string STR_BMC_OS_WATCHDOG_TIMER                   #language en-US  "iBMC WDT Support For OS"
++#string STR_BMC_OS_WATCHDOG_TIMER_HELP              #language en-US  "Enable/Disable OS Watchdog Timer When OS Load"
++#string STR_BMC_OS_WDT_TIMEOUT                      #language en-US  "iBMC WDT TimeOut For OS"
++#string STR_BMC_OS_WDT_TIMEOUT_HELP                 #language en-US  "Enter the number of minutes the system firmware \n has to OS Load before it takes the Timeout Action. Valid values are from 5 to 8 minutes."
++#string STR_BMC_OS_WDT_ACTION                       #language en-US  "iBMC WDT Action For OS"
++
+-- 
+2.17.0
+
diff --git a/v2/v2-0019-Silicon-Hisilicon-D06-Stop-watchdog.patch b/v2/v2-0019-Silicon-Hisilicon-D06-Stop-watchdog.patch
new file mode 100644
index 0000000000..1ac65dd794
--- /dev/null
+++ b/v2/v2-0019-Silicon-Hisilicon-D06-Stop-watchdog.patch
@@ -0,0 +1,125 @@
+From 0574cd888599f1641a88ef5fea667dcd306c1489 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Thu, 28 Jun 2018 11:20:44 +0800
+Subject: [PATCH edk2-platforms v2 19/43] Silicon/Hisilicon/D06: Stop watchdog
+
+according as watchdog design on D06, watchdog should be
+stopped before boot a option.
+
+This is an out of band watchdog timer in BMC; it is used
+to monitor the whole BIOS boot process and reset the system
+in case BIOS hangs somewhere, i.e. it is armed when system
+is power on, and disabled before handling system control to
+OS, while UEFI boot services watchdog is only armed before
+invoking a boot option. So they are two different watchdogs.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf |  2 ++
+ Silicon/Hisilicon/Include/Library/IpmiCmdLib.h                              | 16 ++++++++++++++
+ Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c               | 22 ++++++++++++++++++++
+ 3 files changed, 40 insertions(+)
+
+diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+index a093f13fb0..b9458b0ade 100644
+--- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
++++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBootManagerLib.inf
+@@ -46,6 +46,7 @@
+   DebugLib
+   DevicePathLib
+   DxeServicesLib
++  IpmiCmdLib
+   MemoryAllocationLib
+   PcdLib
+   PrintLib
+@@ -69,6 +70,7 @@
+   gEfiEndOfDxeEventGroupGuid
+   gEfiTtyTermGuid
+   gHisiOemVariableGuid
++  gOemConfigGuid
+ 
+ [Protocols]
+   gEfiGenericMemTestProtocolGuid
+diff --git a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h
+index 8868b76135..b956ee6d07 100644
+--- a/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h
++++ b/Silicon/Hisilicon/Include/Library/IpmiCmdLib.h
+@@ -19,6 +19,17 @@
+ #define BOOT_OPTION_BOOT_FLAG_VALID         1
+ #define BOOT_OPTION_BOOT_FLAG_INVALID       0
+ 
++typedef enum {
++  EfiReserved,
++  EfiBiosFrb2,
++  EfiBiosPost,
++  EfiOsLoad,
++  EfiSmsOs,
++  EfiOem,
++  EfiFrbReserved1,
++  EfiFrbReserved2
++} EFI_WDT_USER_TYPE;
++
+ typedef enum {
+   NoOverride = 0x0,
+   ForcePxe,
+@@ -91,4 +102,9 @@ IpmiCmdGetSysBootOptions (
+   IN IPMI_GET_BOOT_OPTION   *BootOption
+   );
+ 
++EFI_STATUS
++IpmiCmdStopWatchdogTimer (
++  IN EFI_WDT_USER_TYPE  UserType
++  );
++
+ #endif
+diff --git a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
+index d5f6d78fa4..b63818cbe4 100644
+--- a/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
++++ b/Silicon/Hisilicon/Library/PlatformBootManagerLib/PlatformBm.c
+@@ -19,6 +19,8 @@
+ #include <Library/BootLogoLib.h>
+ #include <Library/BmcConfigBootLib.h>
+ #include <Library/DevicePathLib.h>
++#include <Library/IpmiCmdLib.h>
++#include <Library/OemConfigData.h>
+ #include <Library/PcdLib.h>
+ #include <Library/TimerLib.h>
+ #include <Library/UefiBootManagerLib.h>
+@@ -615,6 +617,8 @@ PlatformBootManagerAfterConsole (
+ {
+   EFI_STATUS Status;
+   ESRT_MANAGEMENT_PROTOCOL           *EsrtManagement = NULL;
++  OEM_CONFIG_DATA                    SetupData;
++  UINTN                              DataSize = sizeof (OEM_CONFIG_DATA);
+ 
+   //
+   // Show the splash screen.
+@@ -651,6 +655,24 @@ PlatformBootManagerAfterConsole (
+     );
+ 
+   HandleBmcBootType ();
++
++  //Disable POST Watch Dog before attempting boot
++  Status = gRT->GetVariable (
++                  OEM_CONFIG_NAME,
++                  &gOemConfigGuid,
++                  NULL,
++                  &DataSize,
++                  &SetupData
++                  );
++
++  if (!EFI_ERROR (Status)) {
++    if (SetupData.BmcWdtEnable) {
++      Status = IpmiCmdStopWatchdogTimer (EfiBiosPost);
++      if (EFI_ERROR (Status)) {
++        DEBUG ((DEBUG_ERROR, "%a:%r\n", __FUNCTION__, Status));
++      }
++    }
++  }
+ }
+ 
+ /**
+-- 
+2.17.0
+
diff --git a/v2/v2-0020-Hisilicon-I2C-Modify-I2CLib.c-for-coding-style.patch b/v2/v2-0020-Hisilicon-I2C-Modify-I2CLib.c-for-coding-style.patch
new file mode 100644
index 0000000000..38efbda0b9
--- /dev/null
+++ b/v2/v2-0020-Hisilicon-I2C-Modify-I2CLib.c-for-coding-style.patch
@@ -0,0 +1,1161 @@
+From 7a93e039780d74df08e08b774d0939b066673a2e Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sat, 11 Aug 2018 20:41:09 +0800
+Subject: [PATCH edk2-platforms v2 20/43] Hisilicon/I2C: Modify I2CLib.c for
+ coding style
+
+Correct coding style for I2CLib.c before adding other I2CLib patches.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Library/I2CLib/I2CLib.c | 1034 ++++++++++----------
+ 1 file changed, 499 insertions(+), 535 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+index b5b388d756..f03d55d6b2 100644
+--- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
++++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+@@ -16,640 +16,604 @@
+ 
+ 
+ #include <PiDxe.h>
+-#include <Library/DebugLib.h>
+-#include <Library/UefiBootServicesTableLib.h>
+ #include <Library/ArmLib.h>
+ #include <Library/BaseLib.h>
++#include <Library/DebugLib.h>
+ #include <Library/I2CLib.h>
+ #include <Library/TimerLib.h>
++#include <Library/UefiBootServicesTableLib.h>
+ 
+ #include <Library/PlatformSysCtrlLib.h>
+ 
+ #include "I2CLibInternal.h"
+ #include "I2CHw.h"
+ 
+-VOID I2C_Delay(UINT32 ulCount)
++VOID
++I2C_Delay (
++  UINT32 Count
++  )
+ {
+-    MicroSecondDelay(ulCount);
+-    return;
++  MicroSecondDelay (Count);
++  return;
+ }
+ 
+ 
+ EFI_STATUS
+ EFIAPI
+-I2C_Disable(UINT32 Socket,UINT8 Port)
++I2C_Disable (
++  UINT32 Socket,
++  UINT8  Port
++  )
+ {
+-    UINT32                  ulTimeCnt = I2C_READ_TIMEOUT;
+-    I2C0_STATUS_U           I2cStatusReg;
+-    I2C0_ENABLE_U           I2cEnableReg;
+-    I2C0_ENABLE_STATUS_U    I2cEnableStatusReg;
++  UINT32                  TimeCnt = I2C_READ_TIMEOUT;
++  I2C0_STATUS_U           I2cStatusReg;
++  I2C0_ENABLE_U           I2cEnableReg;
++  I2C0_ENABLE_STATUS_U    I2cEnableStatusReg;
+ 
+-    UINTN Base = GetI2cBase(Socket, Port);
++  UINTN Base = GetI2cBase (Socket, Port);
+ 
+-    I2C_REG_READ((Base + I2C_STATUS_OFFSET), I2cStatusReg.Val32);
++  I2C_REG_READ ((Base + I2C_STATUS_OFFSET), I2cStatusReg.Val32);
+ 
+-    while (I2cStatusReg.bits.activity)
+-    {
+-        I2C_Delay(10000);
++  while (I2cStatusReg.bits.activity) {
++    I2C_Delay (10000);
+ 
+-        ulTimeCnt--;
+-        I2C_REG_READ(Base + I2C_STATUS_OFFSET, I2cStatusReg.Val32);
+-        if (0 == ulTimeCnt)
+-        {
+-            return EFI_DEVICE_ERROR;
+-        }
++    TimeCnt--;
++    I2C_REG_READ (Base + I2C_STATUS_OFFSET, I2cStatusReg.Val32);
++    if (TimeCnt == 0) {
++      return EFI_DEVICE_ERROR;
+     }
++  }
+ 
++  I2C_REG_READ (Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
++  I2cEnableReg.bits.enable = 0;
++  I2C_REG_WRITE (Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+ 
+-    I2C_REG_READ(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+-    I2cEnableReg.bits.enable = 0;
+-    I2C_REG_WRITE(Base + I2C_ENABLE_OFFSET,I2cEnableReg.Val32);
+-
+-    I2C_REG_READ(Base + I2C_ENABLE_OFFSET,I2cEnableStatusReg.Val32);
+-    if (0 == I2cEnableStatusReg.bits.ic_en)
+-    {
+-        return EFI_SUCCESS;
+-    }
+-    else
+-    {
+-        return EFI_DEVICE_ERROR;
+-    }
++  I2C_REG_READ (Base + I2C_ENABLE_OFFSET, I2cEnableStatusReg.Val32);
++  if (I2cEnableStatusReg.bits.ic_en == 0) {
++    return EFI_SUCCESS;
++  } else {
++    return EFI_DEVICE_ERROR;
++  }
+ }
+ 
+ 
+ EFI_STATUS
+ EFIAPI
+-I2C_Enable(UINT32 Socket,UINT8 Port)
++I2C_Enable (
++  UINT32 Socket,
++  UINT8  Port
++  )
+ {
+-    I2C0_ENABLE_U           I2cEnableReg;
+-    I2C0_ENABLE_STATUS_U    I2cEnableStatusReg;
++  I2C0_ENABLE_U           I2cEnableReg;
++  I2C0_ENABLE_STATUS_U    I2cEnableStatusReg;
+ 
+-    UINTN Base = GetI2cBase(Socket, Port);
++  UINTN Base = GetI2cBase (Socket, Port);
+ 
++  I2C_REG_READ (Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
++  I2cEnableReg.bits.enable = 1;
++  I2C_REG_WRITE (Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+ 
+-    I2C_REG_READ(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+-    I2cEnableReg.bits.enable = 1;
+-    I2C_REG_WRITE(Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+ 
+-
+-    I2C_REG_READ(Base + I2C_ENABLE_STATUS_OFFSET, I2cEnableStatusReg.Val32);
+-    if (1 == I2cEnableStatusReg.bits.ic_en)
+-    {
+-        return EFI_SUCCESS;
+-    }
+-    else
+-    {
+-        return EFI_DEVICE_ERROR;
+-    }
++  I2C_REG_READ (Base + I2C_ENABLE_STATUS_OFFSET, I2cEnableStatusReg.Val32);
++  if (I2cEnableStatusReg.bits.ic_en == 1) {
++    return EFI_SUCCESS;
++  } else {
++    return EFI_DEVICE_ERROR;
++  }
+ }
+ 
+-void I2C_SetTarget(UINT32 Socket,UINT8 Port,UINT32 I2cDeviceAddr)
++VOID
++I2C_SetTarget (
++  UINT32 Socket,
++  UINT8  Port,
++  UINT32 I2cDeviceAddr
++  )
+ {
+-    I2C0_TAR_U    I2cTargetReg;
+-    UINTN Base = GetI2cBase(Socket, Port);
++  I2C0_TAR_U    I2cTargetReg;
+ 
++  UINTN Base = GetI2cBase (Socket, Port);
+ 
+-    I2C_REG_READ(Base + I2C_TAR_OFFSET, I2cTargetReg.Val32);
+-    I2cTargetReg.bits.ic_tar = I2cDeviceAddr;
+-    I2C_REG_WRITE(Base + I2C_TAR_OFFSET, I2cTargetReg.Val32);
++  I2C_REG_READ (Base + I2C_TAR_OFFSET, I2cTargetReg.Val32);
++  I2cTargetReg.bits.ic_tar = I2cDeviceAddr;
++  I2C_REG_WRITE (Base + I2C_TAR_OFFSET, I2cTargetReg.Val32);
+ 
+-    return;
++  return;
+ }
+ 
+ 
+ EFI_STATUS
+ EFIAPI
+-I2CInit(UINT32 Socket, UINT32 Port, SPEED_MODE SpeedMode)
++I2CInit (
++  UINT32     Socket,
++  UINT32     Port,
++  SPEED_MODE SpeedMode
++  )
+ {
+-    I2C0_CON_U              I2cControlReg;
+-    I2C0_SS_SCL_HCNT_U      I2cStandardSpeedSclHighCount;
+-    I2C0_SS_SCL_LCNT_U      I2cStandardSpeedSclLowCount;
+-    I2C0_RX_TL_U            I2cRxFifoReg;
+-    I2C0_TX_TL_U            I2cTxFifoReg;
+-    I2C0_INTR_MASK_U        I2cIntrMask;
+-    EFI_STATUS              Status;
+-
+-    UINTN Base = GetI2cBase(Socket, Port);
+-
+-    if((Socket >= MAX_SOCKET) || (Port >= I2C_PORT_MAX) || (SpeedMode >= SPEED_MODE_MAX)){
+-        return EFI_INVALID_PARAMETER;
+-    }
+-
+-
+-    Status = I2C_Disable(Socket,Port);
+-    if(EFI_ERROR(Status))
+-    {
+-        return EFI_DEVICE_ERROR;
+-    }
+-
+-
+-    I2C_REG_READ(Base + I2C_CON_OFFSET, I2cControlReg.Val32);
+-    I2cControlReg.bits.master = 1;
+-    I2cControlReg.bits.spedd = 0x1;
+-    I2cControlReg.bits.restart_en = 1;
+-    I2cControlReg.bits.slave_disable = 1;
+-    I2C_REG_WRITE(Base + I2C_CON_OFFSET,I2cControlReg.Val32);
+-
+-
+-    if(Normal == SpeedMode)
+-    {
+-        I2C_REG_READ(Base + I2C_SS_SCL_HCNT_OFFSET,I2cStandardSpeedSclHighCount.Val32);
+-        I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT;
+-        I2C_REG_WRITE(Base + I2C_SS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
+-        I2C_REG_READ(Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+-        I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT;
+-        I2C_REG_WRITE(Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+-    }
+-    else
+-    {
+-        I2C_REG_READ(Base + I2C_FS_SCL_HCNT_OFFSET,I2cStandardSpeedSclHighCount.Val32);
+-        I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT;
+-        I2C_REG_WRITE(Base + I2C_FS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
+-        I2C_REG_READ(Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+-        I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT;
+-        I2C_REG_WRITE(Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
+-    }
+-
+-
+-    I2C_REG_READ(Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32);
+-    I2cRxFifoReg.bits.rx_tl = I2C_TXRX_THRESHOLD;
+-    I2C_REG_WRITE(Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32);
+-    I2C_REG_READ(Base + I2C_TX_TL_OFFSET,I2cTxFifoReg.Val32);
+-    I2cTxFifoReg.bits.tx_tl = I2C_TXRX_THRESHOLD;
+-    I2C_REG_WRITE(Base + I2C_TX_TL_OFFSET, I2cTxFifoReg.Val32);
+-
+-
+-    I2C_REG_READ(Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32);
+-    I2cIntrMask.Val32 = 0x0;
+-    I2C_REG_WRITE(Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32);
+-
+-
+-    Status = I2C_Enable(Socket,Port);
+-    if(EFI_ERROR(Status))
+-    {
+-        return EFI_DEVICE_ERROR;
+-    }
+-
+-    return I2cLibRuntimeSetup (Socket, Port);
++  I2C0_CON_U              I2cControlReg;
++  I2C0_SS_SCL_HCNT_U      I2cStandardSpeedSclHighCount;
++  I2C0_SS_SCL_LCNT_U      I2cStandardSpeedSclLowCount;
++  I2C0_RX_TL_U            I2cRxFifoReg;
++  I2C0_TX_TL_U            I2cTxFifoReg;
++  I2C0_INTR_MASK_U        I2cIntrMask;
++  EFI_STATUS              Status;
++
++  UINTN Base = GetI2cBase (Socket, Port);
++
++  if ((Socket >= MAX_SOCKET) ||
++     (Port >= I2C_PORT_MAX) ||
++     (SpeedMode >= SPEED_MODE_MAX)) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Status = I2C_Disable (Socket,Port);
++  if (EFI_ERROR (Status)) {
++    return EFI_DEVICE_ERROR;
++  }
++
++  I2C_REG_READ (Base + I2C_CON_OFFSET, I2cControlReg.Val32);
++  I2cControlReg.bits.master = 1;
++  I2cControlReg.bits.spedd = 0x1;
++  I2cControlReg.bits.restart_en = 1;
++  I2cControlReg.bits.slave_disable = 1;
++  I2C_REG_WRITE (Base + I2C_CON_OFFSET, I2cControlReg.Val32);
++
++  if (SpeedMode == Normal) {
++    I2C_REG_READ (Base + I2C_SS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
++    I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT;
++    I2C_REG_WRITE (Base + I2C_SS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
++    I2C_REG_READ (Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
++    I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT;
++    I2C_REG_WRITE (Base + I2C_SS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
++  } else {
++    I2C_REG_READ (Base + I2C_FS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
++    I2cStandardSpeedSclHighCount.bits.ic_ss_scl_hcnt = I2C_SS_SCLHCNT;
++    I2C_REG_WRITE (Base + I2C_FS_SCL_HCNT_OFFSET, I2cStandardSpeedSclHighCount.Val32);
++    I2C_REG_READ (Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
++    I2cStandardSpeedSclLowCount.bits.ic_ss_scl_lcnt = I2C_SS_SCLLCNT;
++    I2C_REG_WRITE (Base + I2C_FS_SCL_LCNT_OFFSET, I2cStandardSpeedSclLowCount.Val32);
++  }
++
++  I2C_REG_READ (Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32);
++  I2cRxFifoReg.bits.rx_tl = I2C_TXRX_THRESHOLD;
++  I2C_REG_WRITE (Base + I2C_RX_TL_OFFSET, I2cRxFifoReg.Val32);
++  I2C_REG_READ (Base + I2C_TX_TL_OFFSET, I2cTxFifoReg.Val32);
++  I2cTxFifoReg.bits.tx_tl = I2C_TXRX_THRESHOLD;
++  I2C_REG_WRITE (Base + I2C_TX_TL_OFFSET, I2cTxFifoReg.Val32);
++
++  I2C_REG_READ (Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32);
++  I2cIntrMask.Val32 = 0x0;
++  I2C_REG_WRITE (Base + I2C_INTR_MASK_OFFSET, I2cIntrMask.Val32);
++
++  Status = I2C_Enable (Socket, Port);
++  if (EFI_ERROR (Status)) {
++    return EFI_DEVICE_ERROR;
++  }
++
++  return I2cLibRuntimeSetup (Socket, Port);
+ }
+ 
+ EFI_STATUS
+ EFIAPI
+-I2CSdaConfig(UINT32 Socket, UINT32 Port)
++I2CSdaConfig (
++  UINT32 Socket,
++  UINT32 Port
++  )
+ {
++  UINTN Base = GetI2cBase (Socket, Port);
+ 
+-    UINTN Base = GetI2cBase(Socket, Port);
++  if ((Socket >= MAX_SOCKET) || (Port >= I2C_PORT_MAX)) {
++    return EFI_INVALID_PARAMETER;
++  }
+ 
+-    if((Socket >= MAX_SOCKET) || (Port >= I2C_PORT_MAX)){
+-        return EFI_INVALID_PARAMETER;
+-    }
+-
+-    I2C_REG_WRITE(Base + I2C_SDA_HOLD, 0x14);
++  I2C_REG_WRITE (Base + I2C_SDA_HOLD, 0x14);
+ 
+-    return EFI_SUCCESS;
++  return EFI_SUCCESS;
+ }
+ 
+ 
+ 
+-UINT32 I2C_GetTxStatus(UINT32 Socket,UINT8 Port)
++UINT32
++I2C_GetTxStatus (
++  UINT32 Socket,
++  UINT8  Port
++  )
+ {
+-    I2C0_TXFLR_U ulFifo;
+-    UINTN Base = GetI2cBase(Socket, Port);
++  I2C0_TXFLR_U Fifo;
++  UINTN        Base = GetI2cBase (Socket, Port);
+ 
+-    I2C_REG_READ(Base + I2C_TXFLR_OFFSET, ulFifo.Val32);
+-    return ulFifo.bits.txflr;
++  I2C_REG_READ (Base + I2C_TXFLR_OFFSET, Fifo.Val32);
++  return Fifo.bits.txflr;
+ }
+ 
+ UINT32
+-I2C_GetRxStatus(UINT32 Socket,UINT8 Port)
++I2C_GetRxStatus (
++  UINT32 Socket,
++  UINT8 Port
++  )
+ {
+-    I2C0_RXFLR_U ulFifo;
+-    UINTN Base = GetI2cBase(Socket, Port);
++  I2C0_RXFLR_U Fifo;
++  UINTN Base = GetI2cBase (Socket, Port);
+ 
+-    I2C_REG_READ(Base + I2C_RXFLR_OFFSET, ulFifo.Val32);
+-    return ulFifo.bits.rxflr;
++  I2C_REG_READ (Base + I2C_RXFLR_OFFSET, Fifo.Val32);
++  return Fifo.bits.rxflr;
+ }
+ 
+ EFI_STATUS
+ EFIAPI
+-WriteBeforeRead(I2C_DEVICE *I2cInfo, UINT32 ulLength, UINT8 *pBuf)
++WriteBeforeRead (
++  I2C_DEVICE *I2cInfo,
++  UINT32     Length,
++  UINT8      *pBuf
++  )
+ {
+-    UINT32 ulFifo;
+-    UINT32 ulCnt;
+-    UINT32 ulTimes = 0;
++  UINT32 Fifo;
++  UINT32 Count;
++  UINT32 Times = 0;
+ 
+-    UINTN  Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
++  UINTN  Base = GetI2cBase (I2cInfo->Socket, I2cInfo->Port);
+ 
++  I2C_SetTarget (I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress);
+ 
+-    I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+-
+-    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    while(0 != ulFifo)
+-    {
+-        I2C_Delay(2);
+-        if(++ulTimes > I2C_READ_TIMEOUT)
+-        {
+-            return EFI_TIMEOUT;
+-        }
+-        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
++  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  while (Fifo != 0) {
++    I2C_Delay (2);
++    if (++Times > I2C_READ_TIMEOUT) {
++      return EFI_TIMEOUT;
+     }
++    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  }
+ 
+-    for(ulCnt = 0; ulCnt < ulLength; ulCnt++)
+-    {
+-        ulTimes = 0;
+-        while(ulFifo > I2C_TXRX_THRESHOLD)
+-        {
+-            I2C_Delay(2);
+-            if(++ulTimes > I2C_READ_TIMEOUT)
+-            {
+-                return EFI_TIMEOUT;
+-            }
+-            ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-        }
+-
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++);
+-        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
++  for (Count = 0; Count < Length; Count++) {
++    Times = 0;
++    while (Fifo > I2C_TXRX_THRESHOLD) {
++      I2C_Delay (2);
++      if (++Times > I2C_READ_TIMEOUT) {
++        return EFI_TIMEOUT;
++      }
++      Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+     }
+ 
+-    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    ulTimes = 0;
+-    while(0 != ulFifo)
+-    {
+-        I2C_Delay(2);
+-
+-        if(++ulTimes > I2C_READ_TIMEOUT)
+-        {
+-            return EFI_TIMEOUT;
+-        }
+-        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, *pBuf++);
++    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  }
++
++  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  Times = 0;
++  while (Fifo != 0) {
++    I2C_Delay (2);
++
++    if (++Times > I2C_READ_TIMEOUT) {
++      return EFI_TIMEOUT;
+     }
++    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  }
+ 
+-    return EFI_SUCCESS;
++  return EFI_SUCCESS;
+ }
+ 
+ 
+ EFI_STATUS
+ EFIAPI
+-I2CWrite(I2C_DEVICE *I2cInfo, UINT16 InfoOffset, UINT32 ulLength, UINT8 *pBuf)
++I2CWrite(
++  I2C_DEVICE *I2cInfo,
++  UINT16     InfoOffset,
++  UINT32     Length,
++  UINT8 *pBuf
++  )
+ {
+-    UINT32 ulFifo;
+-    UINT32 ulTimes = 0;
+-    UINT32  Idx;
+-    UINTN  Base;
+-
+-
+-    if(I2cInfo->Port >= I2C_PORT_MAX)
+-    {
+-        return EFI_INVALID_PARAMETER;
+-    }
+-
+-    Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+-
+-    (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+-
+-    I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+-
+-    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    while(0 != ulFifo)
+-    {
+-        I2C_Delay(2);
+-        if(++ulTimes > I2C_READ_TIMEOUT)
+-        {
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_TIMEOUT;
+-        }
+-        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    }
+-
+-
+-    if(I2cInfo->DeviceType)
+-    {
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+-    }
+-    else
+-    {
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+-    }
+-
+-    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    ulTimes = 0;
+-    while(0 != ulFifo)
+-    {
+-        I2C_Delay(2);
+-        if(++ulTimes > I2C_READ_TIMEOUT)
+-        {
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_TIMEOUT;
+-        }
+-        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    }
+-
+-    for(Idx = 0; Idx < ulLength; Idx++)
+-    {
+-        ulTimes = 0;
+-        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-        while(ulFifo > I2C_TXRX_THRESHOLD)
+-        {
+-            I2C_Delay(2);
+-            if(++ulTimes > I2C_READ_TIMEOUT)
+-            {
+-                (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-                return EFI_TIMEOUT;
+-            }
+-            ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-        }
+-
+-        if (Idx < ulLength - 1) {
+-            I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (*pBuf++));
+-        } else {
+-            //Send command stop bit for the last transfer
+-            I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (*pBuf++) | I2C_CMD_STOP_BIT);
+-        }
+-    }
+-
+-    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    ulTimes = 0;
+-    while(0 != ulFifo)
+-    {
+-        I2C_Delay(2);
+-
+-        if(++ulTimes > I2C_READ_TIMEOUT)
+-        {
+-            DEBUG ((EFI_D_ERROR, "I2C Write try to finished,time out!\n"));
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_TIMEOUT;
+-        }
+-        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    }
+-    (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-
+-    return EFI_SUCCESS;
++  UINT32 Fifo;
++  UINT32 Times = 0;
++  UINT32  Idx;
++  UINTN  Base;
++
++  if (I2cInfo->Port >= I2C_PORT_MAX) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Base = GetI2cBase (I2cInfo->Socket, I2cInfo->Port);
++
++  (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
++
++  I2C_SetTarget(I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress);
++
++  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  while (Fifo != 0) {
++    I2C_Delay (2);
++    if (++Times > I2C_READ_TIMEOUT) {
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_TIMEOUT;
++    }
++    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  }
++
++  if (I2cInfo->DeviceType) {
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
++  } else {
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
++  }
++
++  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  Times = 0;
++  while (Fifo != 0) {
++    I2C_Delay (2);
++    if (++Times > I2C_READ_TIMEOUT) {
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_TIMEOUT;
++    }
++    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  }
++
++  for (Idx = 0; Idx < Length; Idx++) {
++    Times = 0;
++    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++    while (Fifo > I2C_TXRX_THRESHOLD) {
++      I2C_Delay (2);
++      if (++Times > I2C_READ_TIMEOUT) {
++        (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++        return EFI_TIMEOUT;
++      }
++      Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++    }
++
++    if (Idx < Length - 1) {
++      I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (*pBuf++));
++    } else {
++      //Send command stop bit for the last transfer
++      I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (*pBuf++) | I2C_CMD_STOP_BIT);
++    }
++  }
++
++  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  Times = 0;
++  while (Fifo != 0) {
++    I2C_Delay (2);
++
++    if (++Times > I2C_READ_TIMEOUT) {
++      DEBUG ((DEBUG_ERROR, "I2C Write try to finished,time out!\n"));
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_TIMEOUT;
++    }
++    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  }
++  (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++
++  return EFI_SUCCESS;
+ }
+ 
+ EFI_STATUS
+ EFIAPI
+-I2CRead(I2C_DEVICE *I2cInfo, UINT16 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf)
++I2CRead(
++  I2C_DEVICE *I2cInfo,
++  UINT16     InfoOffset,
++  UINT32     RxLen,
++  UINT8 *pBuf
++  )
+ {
+-    UINT32 ulFifo;
+-    UINT32 ulTimes = 0;
+-    UINT8  I2CWAddr[2];
+-    EFI_STATUS  Status;
+-    UINT32  Idx = 0;
+-    UINTN Base;
+-
+-
+-    if(I2cInfo->Port >= I2C_PORT_MAX)
+-    {
+-        return EFI_INVALID_PARAMETER;
+-    }
+-
+-    (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+-    Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+-    if(I2cInfo->DeviceType)
+-    {
+-        I2CWAddr[0] = (InfoOffset >> 8) & 0xff;
+-        I2CWAddr[1] = (InfoOffset & 0xff);
+-        Status = WriteBeforeRead(I2cInfo, 2,I2CWAddr);
+-        if(EFI_ERROR(Status))
+-        {
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_ABORTED;
+-        }
+-    }
+-    else
+-    {
+-        I2CWAddr[0] = (InfoOffset & 0xff);
+-        Status = WriteBeforeRead(I2cInfo, 1,I2CWAddr);
+-        if(EFI_ERROR(Status))
+-        {
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_ABORTED;
+-        }
+-    }
+-
+-    I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+-
+-    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    while(0 != ulFifo)
+-    {
+-        I2C_Delay(2);
+-
+-        while(++ulTimes > I2C_READ_TIMEOUT)
+-        {
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_TIMEOUT;
+-        }
+-        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    }
+-
+-    while (ulRxLen > 0) {
+-        if (ulRxLen > 1) {
+-            I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
+-        } else {
+-            //Send command stop bit for the last transfer
+-            I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL | I2C_CMD_STOP_BIT);
+-        }
+-
+-        ulTimes = 0;
+-        do {
+-            I2C_Delay(2);
+-
+-            while(++ulTimes > I2C_READ_TIMEOUT) {
+-                (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-                return EFI_TIMEOUT;
+-            }
+-            ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port);
+-        }while(0 == ulFifo);
+-
+-        I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+-
+-        ulRxLen --;
+-    }
+-    (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-
+-    return EFI_SUCCESS;
++  UINT32      Fifo;
++  UINT32      Times = 0;
++  UINT8       I2CWAddr[2];
++  EFI_STATUS  Status;
++  UINT32      Idx = 0;
++  UINTN       Base;
++
++  if (I2cInfo->Port >= I2C_PORT_MAX) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
++  Base = GetI2cBase (I2cInfo->Socket, I2cInfo->Port);
++  if (I2cInfo->DeviceType) {
++    I2CWAddr[0] = (InfoOffset >> 8) & 0xff;
++    I2CWAddr[1] = (InfoOffset & 0xff);
++    Status = WriteBeforeRead (I2cInfo, 2,I2CWAddr);
++    if (EFI_ERROR (Status)) {
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_ABORTED;
++    }
++  } else {
++    I2CWAddr[0] = (InfoOffset & 0xff);
++    Status = WriteBeforeRead (I2cInfo, 1, I2CWAddr);
++    if (EFI_ERROR (Status)) {
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_ABORTED;
++    }
++  }
++
++  I2C_SetTarget (I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress);
++
++  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  while (Fifo != 0) {
++    I2C_Delay (2);
++
++    while (++Times > I2C_READ_TIMEOUT) {
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_TIMEOUT;
++    }
++    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  }
++
++  while (RxLen > 0) {
++    if (RxLen > 1) {
++      I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
++    } else {
++      //Send command stop bit for the last transfer
++      I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL | I2C_CMD_STOP_BIT);
++    }
++
++    Times = 0;
++    do {
++      I2C_Delay (2);
++
++      while (++Times > I2C_READ_TIMEOUT) {
++        (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++        return EFI_TIMEOUT;
++      }
++      Fifo = I2C_GetRxStatus (I2cInfo->Socket, I2cInfo->Port);
++    } while (Fifo == 0);
++
++    I2C_REG_READ (Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
++
++    RxLen --;
++  }
++  (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++
++  return EFI_SUCCESS;
+ }
+ 
+ EFI_STATUS
+ EFIAPI
+-I2CReadMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset,UINT32 ulRxLen,UINT8 *pBuf)
++I2CReadMultiByte (
++  I2C_DEVICE *I2cInfo,
++  UINT32     InfoOffset,
++  UINT32     RxLen,
++  UINT8      *pBuf
++  )
+ {
+-    UINT32 ulCnt;
+-    UINT16 usTotalLen = 0;
+-    UINT32 ulFifo;
+-    UINT32 ulTimes = 0;
+-    UINT8  I2CWAddr[4];
+-    EFI_STATUS  Status;
+-    UINT32  BytesLeft;
+-    UINT32  Idx = 0;
+-    UINTN Base;
+-
+-
+-    if(I2cInfo->Port >= I2C_PORT_MAX)
+-    {
+-        return EFI_INVALID_PARAMETER;
+-    }
+-
+-    (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+-    Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+-    if(I2cInfo->DeviceType == DEVICE_TYPE_E2PROM)
+-    {
+-        I2CWAddr[0] = (InfoOffset >> 8) & 0xff;
+-        I2CWAddr[1] = (InfoOffset & 0xff);
+-        Status = WriteBeforeRead(I2cInfo, 2,I2CWAddr);
+-        if(EFI_ERROR(Status))
+-        {
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_ABORTED;
+-        }
+-    }
+-
+-    else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS)
+-    {
+-        I2CWAddr[0] = (InfoOffset >> 16) & 0xff;
+-        I2CWAddr[1] = (InfoOffset >> 8) & 0xff;
+-        I2CWAddr[2] = (InfoOffset & 0xff);
+-        Status = WriteBeforeRead(I2cInfo, 3,I2CWAddr);
+-        if(EFI_ERROR(Status))
+-        {
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_ABORTED;
+-        }
+-    }
+-
+-    else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS)
+-    {
+-        I2CWAddr[0] = (InfoOffset >> 24) & 0xff;
+-        I2CWAddr[1] = (InfoOffset >> 16) & 0xff;
+-        I2CWAddr[2] = (InfoOffset >> 8) & 0xff;
+-        I2CWAddr[3] = (InfoOffset & 0xff);
+-        Status = WriteBeforeRead(I2cInfo, 4,I2CWAddr);
+-        if(EFI_ERROR(Status))
+-        {
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_ABORTED;
+-        }
+-    }
+-
+-    else
+-    {
+-        I2CWAddr[0] = (InfoOffset & 0xff);
+-        Status = WriteBeforeRead(I2cInfo, 1,I2CWAddr);
+-        if(EFI_ERROR(Status))
+-        {
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_ABORTED;
+-        }
+-    }
+-
+-
+-    I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+-    usTotalLen = ulRxLen;
+-    BytesLeft = usTotalLen;
+-
+-    for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) {
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
+-    }
+-
+-
+-    for(ulCnt = 0; ulCnt < BytesLeft; ulCnt++) {
+-        ulTimes = 0;
+-        do {
+-            I2C_Delay(2);
+-
+-            while(++ulTimes > I2C_READ_TIMEOUT) {
+-                (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-                return EFI_TIMEOUT;
+-            }
+-            ulFifo = I2C_GetRxStatus(I2cInfo->Socket,I2cInfo->Port);
+-        }while(0 == ulFifo);
+-
+-        I2C_REG_READ(Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+-    }
+-    (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-
+-    return EFI_SUCCESS;
++  UINT32      Count;
++  UINT16      TotalLen = 0;
++  UINT32      Fifo;
++  UINT32      Times = 0;
++  UINT8       I2CWAddr[4];
++  EFI_STATUS  Status;
++  UINT32      BytesLeft;
++  UINT32      Idx = 0;
++  UINTN       Base;
++
++  if (I2cInfo->Port >= I2C_PORT_MAX) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  (VOID)I2C_Enable (I2cInfo->Socket, I2cInfo->Port);
++  Base = GetI2cBase (I2cInfo->Socket, I2cInfo->Port);
++  if (I2cInfo->DeviceType == DEVICE_TYPE_E2PROM) {
++    I2CWAddr[0] = (InfoOffset >> 8) & 0xff;
++    I2CWAddr[1] = (InfoOffset & 0xff);
++    Status = WriteBeforeRead (I2cInfo, 2,I2CWAddr);
++    if (EFI_ERROR (Status)) {
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_ABORTED;
++    }
++  } else if (I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS) {
++    I2CWAddr[0] = (InfoOffset >> 16) & 0xff;
++    I2CWAddr[1] = (InfoOffset >> 8) & 0xff;
++    I2CWAddr[2] = (InfoOffset & 0xff);
++    Status = WriteBeforeRead (I2cInfo, 3, I2CWAddr);
++    if (EFI_ERROR (Status)) {
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_ABORTED;
++    }
++  } else if (I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS) {
++    I2CWAddr[0] = (InfoOffset >> 24) & 0xff;
++    I2CWAddr[1] = (InfoOffset >> 16) & 0xff;
++    I2CWAddr[2] = (InfoOffset >> 8) & 0xff;
++    I2CWAddr[3] = (InfoOffset & 0xff);
++    Status = WriteBeforeRead (I2cInfo, 4,I2CWAddr);
++    if (EFI_ERROR (Status)) {
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_ABORTED;
++    }
++  } else {
++    I2CWAddr[0] = (InfoOffset & 0xff);
++    Status = WriteBeforeRead (I2cInfo, 1,I2CWAddr);
++    if (EFI_ERROR (Status)) {
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_ABORTED;
++    }
++  }
++
++  I2C_SetTarget(I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress);
++  TotalLen = RxLen;
++  BytesLeft = TotalLen;
++
++  for (Count = 0; Count < BytesLeft; Count++) {
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL);
++  }
++
++  for (Count = 0; Count < BytesLeft; Count++) {
++    Times = 0;
++    do {
++      I2C_Delay (2);
++
++      while (++Times > I2C_READ_TIMEOUT) {
++        (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++        return EFI_TIMEOUT;
++      }
++      Fifo = I2C_GetRxStatus (I2cInfo->Socket, I2cInfo->Port);
++    } while (Fifo == 0);
++
++    I2C_REG_READ (Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
++  }
++  (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++
++  return EFI_SUCCESS;
+ }
+ 
+ EFI_STATUS
+ EFIAPI
+-I2CWriteMultiByte(I2C_DEVICE *I2cInfo, UINT32 InfoOffset, UINT32 ulLength, UINT8 *pBuf)
++I2CWriteMultiByte(
++  I2C_DEVICE *I2cInfo,
++  UINT32     InfoOffset,
++  UINT32     Length,
++  UINT8      *pBuf
++  )
+ {
+-    UINT32 ulFifo;
+-    UINT32 ulTimes = 0;
+-    UINT32  Idx;
+-    UINTN  Base;
+-
+-
+-    if(I2cInfo->Port >= I2C_PORT_MAX)
+-    {
+-        return EFI_INVALID_PARAMETER;
+-    }
+-
+-    Base = GetI2cBase(I2cInfo->Socket, I2cInfo->Port);
+-
+-    (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
+-
+-    I2C_SetTarget(I2cInfo->Socket,I2cInfo->Port,I2cInfo->SlaveDeviceAddress);
+-
+-    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    while(0 != ulFifo)
+-    {
+-        I2C_Delay(2);
+-        if(++ulTimes > I2C_READ_TIMEOUT)
+-        {
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_TIMEOUT;
+-        }
+-        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    }
+-
+-
+-    if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS)
+-    {
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff);
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+-    }
+-
+-    else if(I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS)
+-    {
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 24) & 0xff);
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff);
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
+-        I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+-    }
+-
+-    else
+-    {
+-
+-    }
+-
+-    ulTimes = 0;
+-    for(Idx = 0; Idx < ulLength; Idx++)
+-    {
+-
+-       I2C_REG_WRITE(Base + I2C_DATA_CMD_OFFSET, *pBuf++);
+-
+-    }
+-
+-    ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    ulTimes = 0;
+-    while(0 != ulFifo)
+-    {
+-        I2C_Delay(2);
+-
+-        if(++ulTimes > I2C_READ_TIMEOUT)
+-        {
+-            DEBUG ((EFI_D_ERROR, "I2C Write try to finished,time out!\n"));
+-            (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-            return EFI_TIMEOUT;
+-        }
+-        ulFifo = I2C_GetTxStatus(I2cInfo->Socket,I2cInfo->Port);
+-    }
+-    (VOID)I2C_Disable(I2cInfo->Socket, I2cInfo->Port);
+-
+-    return EFI_SUCCESS;
++  UINT32 Fifo;
++  UINT32 Times = 0;
++  UINT32  Idx;
++  UINTN  Base;
++
++  if (I2cInfo->Port >= I2C_PORT_MAX) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Base = GetI2cBase (I2cInfo->Socket, I2cInfo->Port);
++
++  (VOID)I2C_Enable(I2cInfo->Socket, I2cInfo->Port);
++
++  I2C_SetTarget(I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress);
++
++  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  while (0 != Fifo) {
++    I2C_Delay (2);
++    if (++Times > I2C_READ_TIMEOUT) {
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_TIMEOUT;
++    }
++    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  }
++
++  if (I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS) {
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff);
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
++  } else if (I2cInfo->DeviceType == DEVICE_TYPE_CPLD_4BYTE_OPERANDS) {
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 24) & 0xff);
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 16) & 0xff);
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, (InfoOffset >> 8) & 0xff);
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
++  } else {
++  }
++
++  Times = 0;
++  for (Idx = 0; Idx < Length; Idx++) {
++    I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, *pBuf++);
++  }
++
++  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  Times = 0;
++  while (Fifo != 0) {
++    I2C_Delay (2);
++
++    if (++Times > I2C_READ_TIMEOUT) {
++      DEBUG ((DEBUG_ERROR, "I2C Write try to finished,time out!\n"));
++      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++      return EFI_TIMEOUT;
++    }
++    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  }
++  (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
++
++  return EFI_SUCCESS;
+ }
+ 
+-- 
+2.17.0
+
diff --git a/v2/v2-0021-Silicon-Hisilicon-I2C-Refactor-I2C-library.patch b/v2/v2-0021-Silicon-Hisilicon-I2C-Refactor-I2C-library.patch
new file mode 100644
index 0000000000..906f58800d
--- /dev/null
+++ b/v2/v2-0021-Silicon-Hisilicon-I2C-Refactor-I2C-library.patch
@@ -0,0 +1,302 @@
+From 5ab57cd9e3f75cbb7562d3900633a0da5f857c26 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sun, 22 Jul 2018 21:56:40 +0800
+Subject: [PATCH edk2-platforms v2 21/43] Silicon/Hisilicon/I2C: Refactor I2C
+ library
+
+The hunk of waiting TX/TX finish is used by ten times,
+so move there hunks to a function CheckI2CTimeOut().
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Library/I2CLib/I2CHw.h  |   4 +
+ Silicon/Hisilicon/Library/I2CLib/I2CLib.c | 161 ++++++++------------
+ 2 files changed, 66 insertions(+), 99 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CHw.h b/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
+index aa561e929c..fa954c7937 100644
+--- a/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
++++ b/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
+@@ -265,5 +265,9 @@
+      UINT32      Val32;
+  } I2C0_ENABLE_STATUS_U;
+ 
++typedef enum {
++  I2CTx,
++  I2CRx
++} I2CTransfer;
+ 
+ #endif
+diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+index f03d55d6b2..9174e50dd4 100644
+--- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
++++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+@@ -238,6 +238,45 @@ I2C_GetRxStatus (
+   return Fifo.bits.rxflr;
+ }
+ 
++EFI_STATUS
++EFIAPI
++CheckI2CTimeOut (
++  UINT32      Socket,
++  UINT8       Port,
++  I2CTransfer Transfer
++  )
++{
++  UINT32 Times = 0;
++  UINT32 Fifo;
++
++  if (Transfer == I2CTx) {
++    Fifo = I2C_GetTxStatus (Socket, Port);
++    while (Fifo != 0) {
++      // This is a empirical value for I2C delay. MemoryFance is no need here.
++      I2C_Delay (2);
++      if (++Times > I2C_READ_TIMEOUT) {
++        (VOID)I2C_Disable (Socket, Port);
++        return EFI_TIMEOUT;
++      }
++      Fifo = I2C_GetTxStatus (Socket, Port);
++    }
++  } else {
++    Fifo = I2C_GetRxStatus (Socket, Port);
++    while (Fifo == 0) {
++      // This is a empirical value for I2C delay. MemoryFance is no need here.
++      I2C_Delay (2);
++      if (++Times > I2C_READ_TIMEOUT) {
++        (VOID)I2C_Disable (Socket, Port);
++        return EFI_TIMEOUT;
++      }
++      Fifo = I2C_GetRxStatus (Socket, Port);
++    }
++  }
++
++  return EFI_SUCCESS;
++}
++
++
+ EFI_STATUS
+ EFIAPI
+ WriteBeforeRead (
+@@ -254,15 +293,11 @@ WriteBeforeRead (
+ 
+   I2C_SetTarget (I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress);
+ 
+-  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+-  while (Fifo != 0) {
+-    I2C_Delay (2);
+-    if (++Times > I2C_READ_TIMEOUT) {
+-      return EFI_TIMEOUT;
+-    }
+-    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) {
++    return EFI_TIMEOUT;
+   }
+ 
++  Fifo = 0;
+   for (Count = 0; Count < Length; Count++) {
+     Times = 0;
+     while (Fifo > I2C_TXRX_THRESHOLD) {
+@@ -277,15 +312,8 @@ WriteBeforeRead (
+     Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+   }
+ 
+-  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+-  Times = 0;
+-  while (Fifo != 0) {
+-    I2C_Delay (2);
+-
+-    if (++Times > I2C_READ_TIMEOUT) {
+-      return EFI_TIMEOUT;
+-    }
+-    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) {
++    return EFI_TIMEOUT;
+   }
+ 
+   return EFI_SUCCESS;
+@@ -316,14 +344,8 @@ I2CWrite(
+ 
+   I2C_SetTarget(I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress);
+ 
+-  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+-  while (Fifo != 0) {
+-    I2C_Delay (2);
+-    if (++Times > I2C_READ_TIMEOUT) {
+-      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+-      return EFI_TIMEOUT;
+-    }
+-    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) {
++    return EFI_TIMEOUT;
+   }
+ 
+   if (I2cInfo->DeviceType) {
+@@ -333,15 +355,8 @@ I2CWrite(
+     I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, InfoOffset & 0xff);
+   }
+ 
+-  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+-  Times = 0;
+-  while (Fifo != 0) {
+-    I2C_Delay (2);
+-    if (++Times > I2C_READ_TIMEOUT) {
+-      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+-      return EFI_TIMEOUT;
+-    }
+-    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) {
++    return EFI_TIMEOUT;
+   }
+ 
+   for (Idx = 0; Idx < Length; Idx++) {
+@@ -364,17 +379,8 @@ I2CWrite(
+     }
+   }
+ 
+-  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+-  Times = 0;
+-  while (Fifo != 0) {
+-    I2C_Delay (2);
+-
+-    if (++Times > I2C_READ_TIMEOUT) {
+-      DEBUG ((DEBUG_ERROR, "I2C Write try to finished,time out!\n"));
+-      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+-      return EFI_TIMEOUT;
+-    }
+-    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) {
++    return EFI_TIMEOUT;
+   }
+   (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+ 
+@@ -390,8 +396,6 @@ I2CRead(
+   UINT8 *pBuf
+   )
+ {
+-  UINT32      Fifo;
+-  UINT32      Times = 0;
+   UINT8       I2CWAddr[2];
+   EFI_STATUS  Status;
+   UINT32      Idx = 0;
+@@ -422,15 +426,8 @@ I2CRead(
+ 
+   I2C_SetTarget (I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress);
+ 
+-  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+-  while (Fifo != 0) {
+-    I2C_Delay (2);
+-
+-    while (++Times > I2C_READ_TIMEOUT) {
+-      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+-      return EFI_TIMEOUT;
+-    }
+-    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) {
++    return EFI_TIMEOUT;
+   }
+ 
+   while (RxLen > 0) {
+@@ -441,16 +438,9 @@ I2CRead(
+       I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, I2C_READ_SIGNAL | I2C_CMD_STOP_BIT);
+     }
+ 
+-    Times = 0;
+-    do {
+-      I2C_Delay (2);
+-
+-      while (++Times > I2C_READ_TIMEOUT) {
+-        (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+-        return EFI_TIMEOUT;
+-      }
+-      Fifo = I2C_GetRxStatus (I2cInfo->Socket, I2cInfo->Port);
+-    } while (Fifo == 0);
++    if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CRx) == EFI_TIMEOUT) {
++      return EFI_TIMEOUT;
++    }
+ 
+     I2C_REG_READ (Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+ 
+@@ -472,8 +462,6 @@ I2CReadMultiByte (
+ {
+   UINT32      Count;
+   UINT16      TotalLen = 0;
+-  UINT32      Fifo;
+-  UINT32      Times = 0;
+   UINT8       I2CWAddr[4];
+   EFI_STATUS  Status;
+   UINT32      BytesLeft;
+@@ -531,16 +519,9 @@ I2CReadMultiByte (
+   }
+ 
+   for (Count = 0; Count < BytesLeft; Count++) {
+-    Times = 0;
+-    do {
+-      I2C_Delay (2);
+-
+-      while (++Times > I2C_READ_TIMEOUT) {
+-        (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+-        return EFI_TIMEOUT;
+-      }
+-      Fifo = I2C_GetRxStatus (I2cInfo->Socket, I2cInfo->Port);
+-    } while (Fifo == 0);
++    if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CRx) == EFI_TIMEOUT) {
++      return EFI_TIMEOUT;
++    }
+ 
+     I2C_REG_READ (Base + I2C_DATA_CMD_OFFSET, pBuf[Idx++]);
+   }
+@@ -558,8 +539,6 @@ I2CWriteMultiByte(
+   UINT8      *pBuf
+   )
+ {
+-  UINT32 Fifo;
+-  UINT32 Times = 0;
+   UINT32  Idx;
+   UINTN  Base;
+ 
+@@ -573,14 +552,8 @@ I2CWriteMultiByte(
+ 
+   I2C_SetTarget(I2cInfo->Socket, I2cInfo->Port, I2cInfo->SlaveDeviceAddress);
+ 
+-  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+-  while (0 != Fifo) {
+-    I2C_Delay (2);
+-    if (++Times > I2C_READ_TIMEOUT) {
+-      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+-      return EFI_TIMEOUT;
+-    }
+-    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) {
++    return EFI_TIMEOUT;
+   }
+ 
+   if (I2cInfo->DeviceType == DEVICE_TYPE_CPLD_3BYTE_OPERANDS) {
+@@ -595,22 +568,12 @@ I2CWriteMultiByte(
+   } else {
+   }
+ 
+-  Times = 0;
+   for (Idx = 0; Idx < Length; Idx++) {
+     I2C_REG_WRITE (Base + I2C_DATA_CMD_OFFSET, *pBuf++);
+   }
+ 
+-  Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+-  Times = 0;
+-  while (Fifo != 0) {
+-    I2C_Delay (2);
+-
+-    if (++Times > I2C_READ_TIMEOUT) {
+-      DEBUG ((DEBUG_ERROR, "I2C Write try to finished,time out!\n"));
+-      (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+-      return EFI_TIMEOUT;
+-    }
+-    Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
++  if (CheckI2CTimeOut (I2cInfo->Socket, I2cInfo->Port, I2CTx) == EFI_TIMEOUT) {
++    return EFI_TIMEOUT;
+   }
+   (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+ 
+-- 
+2.17.0
+
diff --git a/v2/v2-0022-Silicon-Hisilicon-D06-Fix-I2C-enable-fail-issue-f.patch b/v2/v2-0022-Silicon-Hisilicon-D06-Fix-I2C-enable-fail-issue-f.patch
new file mode 100644
index 0000000000..a7598a816a
--- /dev/null
+++ b/v2/v2-0022-Silicon-Hisilicon-D06-Fix-I2C-enable-fail-issue-f.patch
@@ -0,0 +1,55 @@
+From 1199d612614134c4e11cfde66bf2e5626607109d Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Thu, 25 Jan 2018 13:43:30 +0800
+Subject: [PATCH edk2-platforms v2 22/43] Silicon/Hisilicon/D06: Fix I2C enable
+ fail issue for D06
+
+I2C may enable failed in D06, so retry I2C enable while
+enable failed.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Library/I2CLib/I2CLib.c | 18 ++++++++++++------
+ 1 file changed, 12 insertions(+), 6 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+index 9174e50dd4..d67ddc7f9b 100644
+--- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
++++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+@@ -86,6 +86,7 @@ I2C_Enable (
+ {
+   I2C0_ENABLE_U           I2cEnableReg;
+   I2C0_ENABLE_STATUS_U    I2cEnableStatusReg;
++  UINT32                  TimeCnt = I2C_READ_TIMEOUT;
+ 
+   UINTN Base = GetI2cBase (Socket, Port);
+ 
+@@ -93,13 +94,18 @@ I2C_Enable (
+   I2cEnableReg.bits.enable = 1;
+   I2C_REG_WRITE (Base + I2C_ENABLE_OFFSET, I2cEnableReg.Val32);
+ 
++  do {
++    // This is a empirical value for I2C delay. MemoryFance is no need here.
++    I2C_Delay (10000);
+ 
+-  I2C_REG_READ (Base + I2C_ENABLE_STATUS_OFFSET, I2cEnableStatusReg.Val32);
+-  if (I2cEnableStatusReg.bits.ic_en == 1) {
+-    return EFI_SUCCESS;
+-  } else {
+-    return EFI_DEVICE_ERROR;
+-  }
++    TimeCnt--;
++    I2C_REG_READ (Base + I2C_ENABLE_STATUS_OFFSET, I2cEnableStatusReg.Val32);
++    if (TimeCnt == 0) {
++      return EFI_DEVICE_ERROR;
++    }
++  } while (I2cEnableStatusReg.bits.ic_en == 0);
++
++  return EFI_SUCCESS;
+ }
+ 
+ VOID
+-- 
+2.17.0
+
diff --git a/v2/v2-0023-Silicon-Hisilicon-D06-Add-I2C-delay-for-HNS-auto-.patch b/v2/v2-0023-Silicon-Hisilicon-D06-Add-I2C-delay-for-HNS-auto-.patch
new file mode 100644
index 0000000000..10be9b3042
--- /dev/null
+++ b/v2/v2-0023-Silicon-Hisilicon-D06-Add-I2C-delay-for-HNS-auto-.patch
@@ -0,0 +1,80 @@
+From 4ed38a68168e94f2fd04d774102b5286b968d921 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Wed, 2 May 2018 17:04:30 +0800
+Subject: [PATCH edk2-platforms v2 23/43] Silicon/Hisilicon/D06: Add I2C delay
+ for HNS auto config
+
+Because I2C Port5 salve device connect under I2C extender
+(9545 device), it will cost more time to access I2C slave
+device, so add delay time for HNS auto config.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Library/I2CLib/I2CHw.h  |  3 +++
+ Silicon/Hisilicon/Library/I2CLib/I2CLib.c | 21 +++++++++++++++-----
+ 2 files changed, 19 insertions(+), 5 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CHw.h b/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
+index fa954c7937..d77aea509e 100644
+--- a/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
++++ b/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
+@@ -19,6 +19,9 @@
+ #include <Uefi.h>
+ #include <Library/IoLib.h>
+ 
++// The HNS I2C port 5 is under I2C extender
++#define I2C_EXTENDER_PORT_HNS        5
++
+ #define I2C_READ_TIMEOUT             500
+ #define I2C_DRV_ONCE_WRITE_BYTES_NUM 8
+ #define I2C_DRV_ONCE_READ_BYTES_NUM  8
+diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+index d67ddc7f9b..59633106ce 100644
+--- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
++++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+@@ -258,8 +258,13 @@ CheckI2CTimeOut (
+   if (Transfer == I2CTx) {
+     Fifo = I2C_GetTxStatus (Socket, Port);
+     while (Fifo != 0) {
+-      // This is a empirical value for I2C delay. MemoryFance is no need here.
+-      I2C_Delay (2);
++      if (Port == I2C_EXTENDER_PORT_HNS) {
++        // This is a empirical value for I2C delay. MemoryFance is no need here.
++        I2C_Delay (1000);
++      } else {
++        // This is a empirical value for I2C delay. MemoryFance is no need here.
++        I2C_Delay (2);
++      }
+       if (++Times > I2C_READ_TIMEOUT) {
+         (VOID)I2C_Disable (Socket, Port);
+         return EFI_TIMEOUT;
+@@ -269,8 +274,13 @@ CheckI2CTimeOut (
+   } else {
+     Fifo = I2C_GetRxStatus (Socket, Port);
+     while (Fifo == 0) {
+-      // This is a empirical value for I2C delay. MemoryFance is no need here.
+-      I2C_Delay (2);
++      if (Port == I2C_EXTENDER_PORT_HNS) {
++        // This is a empirical value for I2C delay. MemoryFance is no need here.
++        I2C_Delay (1000);
++      } else {
++        // This is a empirical value for I2C delay. MemoryFance is no need here.
++        I2C_Delay (2);
++      }
+       if (++Times > I2C_READ_TIMEOUT) {
+         (VOID)I2C_Disable (Socket, Port);
+         return EFI_TIMEOUT;
+@@ -369,7 +379,8 @@ I2CWrite(
+     Times = 0;
+     Fifo = I2C_GetTxStatus (I2cInfo->Socket, I2cInfo->Port);
+     while (Fifo > I2C_TXRX_THRESHOLD) {
+-      I2C_Delay (2);
++      // This is a empirical value for I2C delay. MemoryFance is no need here.
++      I2C_Delay (1000);
+       if (++Times > I2C_READ_TIMEOUT) {
+         (VOID)I2C_Disable (I2cInfo->Socket, I2cInfo->Port);
+         return EFI_TIMEOUT;
+-- 
+2.17.0
+
diff --git a/v2/v2-0024-Hisilicon-I2C-Fix-a-typo-issue.patch b/v2/v2-0024-Hisilicon-I2C-Fix-a-typo-issue.patch
new file mode 100644
index 0000000000..b00dd679b4
--- /dev/null
+++ b/v2/v2-0024-Hisilicon-I2C-Fix-a-typo-issue.patch
@@ -0,0 +1,43 @@
+From 13acafeb2fb0002885d6bc9bd6dd873c7c20f3ee Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Sat, 11 Aug 2018 22:18:03 +0800
+Subject: [PATCH edk2-platforms v2 24/43] Hisilicon/I2C: Fix a typo issue
+
+Modify spedd to Speed.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Library/I2CLib/I2CHw.h  | 2 +-
+ Silicon/Hisilicon/Library/I2CLib/I2CLib.c | 2 +-
+ 2 files changed, 2 insertions(+), 2 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CHw.h b/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
+index d77aea509e..6fd7b8183e 100644
+--- a/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
++++ b/Silicon/Hisilicon/Library/I2CLib/I2CHw.h
+@@ -81,7 +81,7 @@
+      struct
+      {
+         UINT32      master                : 1   ;
+-        UINT32      spedd                 : 2   ;
++        UINT32      Speed                 : 2   ;
+         UINT32      slave_10bit           : 1   ;
+         UINT32      master_10bit          : 1   ;
+         UINT32      restart_en            : 1   ;
+diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+index 59633106ce..ed44ac204f 100644
+--- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
++++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+@@ -158,7 +158,7 @@ I2CInit (
+ 
+   I2C_REG_READ (Base + I2C_CON_OFFSET, I2cControlReg.Val32);
+   I2cControlReg.bits.master = 1;
+-  I2cControlReg.bits.spedd = 0x1;
++  I2cControlReg.bits.Speed = 0x1;
+   I2cControlReg.bits.restart_en = 1;
+   I2cControlReg.bits.slave_disable = 1;
+   I2C_REG_WRITE (Base + I2C_CON_OFFSET, I2cControlReg.Val32);
+-- 
+2.17.0
+
diff --git a/v2/v2-0025-Silicon-Hisilicon-D06-Optimize-HNS-config-CDR-pos.patch b/v2/v2-0025-Silicon-Hisilicon-D06-Optimize-HNS-config-CDR-pos.patch
new file mode 100644
index 0000000000..7d180c2537
--- /dev/null
+++ b/v2/v2-0025-Silicon-Hisilicon-D06-Optimize-HNS-config-CDR-pos.patch
@@ -0,0 +1,44 @@
+From dfb52fc65450d03f858f1e2f0ac86ec6d266e2d8 Mon Sep 17 00:00:00 2001
+From: shaochangliang <shaochangliang@huawei.com>
+Date: Mon, 21 May 2018 18:09:07 +0800
+Subject: [PATCH edk2-platforms v2 25/43] Silicon/Hisilicon/D06: Optimize HNS
+ config CDR post time
+
+Use I2C 400KB speed for config CDR.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Library/I2CLib/I2CLib.c | 9 ++++++++-
+ 1 file changed, 8 insertions(+), 1 deletion(-)
+
+diff --git a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+index ed44ac204f..55c030a3af 100644
+--- a/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
++++ b/Silicon/Hisilicon/Library/I2CLib/I2CLib.c
+@@ -28,6 +28,9 @@
+ #include "I2CLibInternal.h"
+ #include "I2CHw.h"
+ 
++#define I2C_100KB_SPEED 0x1
++#define I2C_400KB_SPEED 0x2
++
+ VOID
+ I2C_Delay (
+   UINT32 Count
+@@ -158,7 +161,11 @@ I2CInit (
+ 
+   I2C_REG_READ (Base + I2C_CON_OFFSET, I2cControlReg.Val32);
+   I2cControlReg.bits.master = 1;
+-  I2cControlReg.bits.Speed = 0x1;
++  if(SpeedMode == Normal) {
++    I2cControlReg.bits.Speed = I2C_100KB_SPEED;
++  } else {
++    I2cControlReg.bits.Speed = I2C_400KB_SPEED;
++  }
+   I2cControlReg.bits.restart_en = 1;
+   I2cControlReg.bits.slave_disable = 1;
+   I2C_REG_WRITE (Base + I2C_CON_OFFSET, I2cControlReg.Val32);
+-- 
+2.17.0
+
diff --git a/v2/v2-0026-Silicon-Hisilicon-Setup-Add-Setup-Item-EnableGOP.patch b/v2/v2-0026-Silicon-Hisilicon-Setup-Add-Setup-Item-EnableGOP.patch
new file mode 100644
index 0000000000..160e860729
--- /dev/null
+++ b/v2/v2-0026-Silicon-Hisilicon-Setup-Add-Setup-Item-EnableGOP.patch
@@ -0,0 +1,73 @@
+From 0f5bb8b897a91c05af02491a7e9a9569676c45c9 Mon Sep 17 00:00:00 2001
+From: Yang XinYi <yangxingyi@huawei.com>
+Date: Thu, 28 Jun 2018 10:49:44 +0800
+Subject: [PATCH edk2-platforms v2 26/43] Silicon/Hisilicon/Setup: Add Setup
+ Item "EnableGOP"
+
+Add Setup Item "EnableGOP" for D06, This Item only takes
+effect on VGA device SM750.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Yang XinYi <yangxingyi@huawei.com>
+---
+ Silicon/Hisilicon/Include/Library/OemConfigData.h            | 1 +
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c    | 1 +
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr | 7 +++++++
+ Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni | 4 ++--
+ 4 files changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Include/Library/OemConfigData.h b/Silicon/Hisilicon/Include/Library/OemConfigData.h
+index 478821ae2c..e4d5917046 100644
+--- a/Silicon/Hisilicon/Include/Library/OemConfigData.h
++++ b/Silicon/Hisilicon/Include/Library/OemConfigData.h
+@@ -61,6 +61,7 @@ typedef struct {
+   UINT8         EnableSmmu;
+   UINT8         EnableFdtTable;
+   UINT8         EnableSpcr;
++  UINT8         EnableGOP;
+   /*RAS Config*/
+   UINT8         EnRasSupport;
+   UINT8         EnPoison;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c
+index 1e3635307c..3ecae3759a 100644
+--- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/OemConfig.c
+@@ -295,6 +295,7 @@ OemConfigUiLibConstructor (
+       Configuration.EnableSmmu = 1;
+       Configuration.EnableFdtTable = 0;
+       Configuration.EnableSpcr = 0;
++      Configuration.EnableGOP = 0;
+       //
+       //Set the default value of the Ras option
+       //
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr
+index 9e3ac73116..c0b6e294a6 100644
+--- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.hfr
+@@ -38,4 +38,11 @@ form formid = MISC_CONFIG_FORM_ID,
+       option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = 0;
+     endoneof;
+ 
++    oneof varid   = OEM_CONFIG_DATA.EnableGOP,
++      prompt      = STRING_TOKEN(STR_ENABLE_GOP_FRAME_BUFFER),
++      help        = STRING_TOKEN(STR_ENABLE_GOP_FRAME_BUFFER_HELP),
++      option text = STRING_TOKEN(STR_DISABLED), value = 0, flags = DEFAULT;
++      option text = STRING_TOKEN(STR_ENABLED), value = 1, flags = 0;
++    endoneof;
++
+ endform;
+diff --git a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni
+index 53eb1622c4..2fd92fedff 100644
+--- a/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni
++++ b/Silicon/Hisilicon/Hi1620/Hi1620OemConfigUiLib/MiscConfig.uni
+@@ -23,5 +23,5 @@
+ #string STR_FDT_CONFIG_HELP            #language en-US  "Enable or Disable Fdt Table."
+ #string STR_ENABLE_SPCR_TABLE          #language en-US  "Support SPCR"
+ #string STR_ENABLE_SPCR_HELP           #language en-US  "Enable or Disable SPCR Table."
+-#string STR_ENABLE_GOP_FRAME_BUFFER    #language en-US  "Support GOP FB"
+-#string STR_ENABLE_GOP_FRAME_BUFFER_HELP     #language en-US  "Enable or Disable GOP frame buffer."
++#string STR_ENABLE_GOP_FRAME_BUFFER    #language en-US  "Support GOP FB for SM750"
++#string STR_ENABLE_GOP_FRAME_BUFFER_HELP     #language en-US  "Enable or Disable GOP frame buffer for SM750."
+-- 
+2.17.0
+
diff --git a/v2/v2-0027-Hisilicon-Hi1620-Add-ACPI-PPTT-table.patch b/v2/v2-0027-Hisilicon-Hi1620-Add-ACPI-PPTT-table.patch
new file mode 100644
index 0000000000..403709d66b
--- /dev/null
+++ b/v2/v2-0027-Hisilicon-Hi1620-Add-ACPI-PPTT-table.patch
@@ -0,0 +1,701 @@
+From 2685ba26f1fff25f0f30ad0d59a286759d9af6bf Mon Sep 17 00:00:00 2001
+From: Heyi Guo <heyi.guo@linaro.org>
+Date: Mon, 23 Apr 2018 15:46:04 +0800
+Subject: [PATCH edk2-platforms v2 27/43] Hisilicon/Hi1620: Add ACPI PPTT table
+
+This driver fetches information from MADT,  so it is adaptable for
+partial good and 1P/2P, since MADT is updated for different
+configurations by certain mechanism.
+
+Since L2 cache is also private resource of core, so we need to set the
+next level of cache for L1I and L1D, which is important for OS to
+parse cache hierarchy.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
+---
+ Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf |  48 ++
+ Silicon/Hisilicon/Hi1620/Pptt/Pptt.h   |  68 +++
+ Silicon/Hisilicon/Hi1620/Pptt/Pptt.c   | 543 ++++++++++++++++++++
+ 3 files changed, 659 insertions(+)
+
+diff --git a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf
+new file mode 100644
+index 0000000000..f8a5ed33a4
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf
+@@ -0,0 +1,48 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under Platform/ARM/JunoPkg/AcpiTables/
++*
++**/
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = AcpiPptt
++  FILE_GUID                      = 65766562-49e7-11e8-817f-286ed489ee9b
++  MODULE_TYPE                    = DXE_DRIVER
++  VERSION_STRING                 = 1.0
++  ENTRY_POINT                    = PpttEntryPoint
++
++[Sources.common]
++  Pptt.c
++
++[Packages]
++  ArmPkg/ArmPkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  ArmLib
++  BaseMemoryLib
++  DebugLib
++  HobLib
++  UefiDriverEntryPoint
++  UefiRuntimeServicesTableLib
++
++[Protocols]
++  gEfiAcpiSdtProtocolGuid                       ## PROTOCOL ALWAYS_CONSUMED
++  gEfiAcpiTableProtocolGuid                     ## PROTOCOL ALWAYS_CONSUMED
++
++[Depex]
++  gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid
++
+diff --git a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h
+new file mode 100644
+index 0000000000..5f2ec67cb9
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.h
+@@ -0,0 +1,68 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under Platform/ARM/JunoPkg/AcpiTables/
++*
++**/
++
++#ifndef _PPTT_H_
++#define _PPTT_H_
++
++#include <PlatformArch.h>
++#include <IndustryStandard/Acpi.h>
++#include <Library/ArmLib/ArmLibPrivate.h>
++#include <Library/BaseMemoryLib.h>
++#include <Library/DebugLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include <Library/PcdLib.h>
++#include <Library/UefiBootServicesTableLib.h>
++#include <Library/UefiLib.h>
++#include <Protocol/AcpiSystemDescriptionTable.h>
++#include <Protocol/AcpiTable.h>
++
++#define PPTT_VENDOR_ID             SIGNATURE_32('H', 'I', 'S', 'I')
++
++#define EFI_ACPI_MAX_NUM_TABLES    20
++
++#define MAX_SCL_PER_SOCKET         MAX_DIE
++#define MAX_SCL                    (MAX_SOCKET * MAX_SCL_PER_SOCKET)
++#define MAX_CLUSTER_PER_SCL        8
++
++#define PPTT_TABLE_MAX_LEN         0x6000
++#define PPTT_SOCKET_COMPONENT_NO   0x1
++#define PPTT_CACHE_NO              0x4
++
++typedef union {
++  struct {
++    UINT32    InD           :1;
++    UINT32    Level         :3;
++    UINT32    Reserved      :28;
++  } Bits;
++  UINT32 Data;
++} CSSELR_DATA;
++
++typedef union {
++  struct {
++    UINT32    LineSize           :3;
++    UINT32    Associativity      :10;
++    UINT32    NumSets            :15;
++    UINT32    Wa                 :1;
++    UINT32    Ra                 :1;
++    UINT32    Wb                 :1;
++    UINT32    Wt                 :1;
++  } Bits;
++  UINT32 Data;
++} CCSIDR_DATA;
++
++#endif    // _PPTT_H_
++
+diff --git a/Silicon/Hisilicon/Hi1620/Pptt/Pptt.c b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.c
+new file mode 100644
+index 0000000000..944b4b9507
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Pptt/Pptt.c
+@@ -0,0 +1,543 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++*  Based on the files under Platform/ARM/JunoPkg/AcpiTables/
++*
++**/
++
++#include "Pptt.h"
++
++typedef EFI_ACPI_5_1_GIC_STRUCTURE                          ACPI_GIC_STRUCTURE;
++typedef EFI_ACPI_5_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER ACPI_MADT_TABLE_HEADER;
++
++EFI_ACPI_TABLE_PROTOCOL       *mAcpiTableProtocol = NULL;
++EFI_ACPI_SDT_PROTOCOL         *mAcpiSdtProtocol   = NULL;
++
++EFI_ACPI_DESCRIPTION_HEADER mPpttHeader =
++  ARM_ACPI_HEADER (
++    EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_STRUCTURE_SIGNATURE,
++    EFI_ACPI_DESCRIPTION_HEADER,
++    EFI_ACPI_6_2_PROCESSOR_PROPERTIES_TOPOLOGY_TABLE_REVISION
++  );
++
++EFI_ACPI_6_2_PPTT_STRUCTURE_ID mPpttSocketType2[PPTT_SOCKET_COMPONENT_NO] =
++{
++  {2, sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID), {0, 0}, PPTT_VENDOR_ID, 0, 0, 0, 0, 0}
++};
++
++EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE mPpttCacheType1[PPTT_CACHE_NO];
++
++STATIC UINT32 mSocketOffset[MAX_SOCKET];
++STATIC UINT32 mScclOffset[MAX_SCL];
++STATIC UINT32 mClusterOffset[MAX_SCL][MAX_CLUSTER_PER_SCL];
++
++STATIC
++VOID
++InitCacheInfo (
++  VOID
++  )
++{
++  UINT8                                        Index;
++  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES Type1Attributes;
++  CSSELR_DATA                                  CsselrData;
++  CCSIDR_DATA                                  CcsidrData;
++
++  for (Index = 0; Index < PPTT_CACHE_NO; Index++) {
++    CsselrData.Data = 0;
++    CcsidrData.Data = 0;
++    SetMem (
++      &Type1Attributes,
++      sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
++      0
++      );
++
++    if (Index == 0) { //L1I
++      CsselrData.Bits.InD = 1;
++      CsselrData.Bits.Level = 0;
++      Type1Attributes.CacheType  = 1;
++    } else if (Index == 1) {
++      Type1Attributes.CacheType  = 0;
++      CsselrData.Bits.Level = Index - 1;
++    } else {
++      Type1Attributes.CacheType  = 2;
++      CsselrData.Bits.Level = Index - 1;
++    }
++
++    CcsidrData.Data = ReadCCSIDR (CsselrData.Data);
++
++    if (CcsidrData.Bits.Wa == 1) {
++      Type1Attributes.AllocationType = EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_WRITE;
++      if (CcsidrData.Bits.Ra == 1) {
++        Type1Attributes.AllocationType = EFI_ACPI_6_2_CACHE_ATTRIBUTES_ALLOCATION_READ_WRITE;
++      }
++    }
++
++    if (CcsidrData.Bits.Wt == 1) {
++      Type1Attributes.WritePolicy = 1;
++    }
++    DEBUG ((DEBUG_INFO,
++            "[Acpi PPTT] Level = %x!CcsidrData = %x!\n",
++            CsselrData.Bits.Level,
++            CcsidrData.Data));
++
++    mPpttCacheType1[Index].Type = EFI_ACPI_6_2_PPTT_TYPE_CACHE;
++    mPpttCacheType1[Index].Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE);
++    mPpttCacheType1[Index].Reserved[0] = 0;
++    mPpttCacheType1[Index].Reserved[1] = 0;
++    mPpttCacheType1[Index].Flags.SizePropertyValid = 1;
++    mPpttCacheType1[Index].Flags.NumberOfSetsValid = 1;
++    mPpttCacheType1[Index].Flags.AssociativityValid = 1;
++    mPpttCacheType1[Index].Flags.AllocationTypeValid = 1;
++    mPpttCacheType1[Index].Flags.CacheTypeValid = 1;
++    mPpttCacheType1[Index].Flags.WritePolicyValid = 1;
++    mPpttCacheType1[Index].Flags.LineSizeValid = 1;
++    mPpttCacheType1[Index].Flags.Reserved = 0;
++    mPpttCacheType1[Index].NextLevelOfCache = 0;
++
++    if (Index != PPTT_CACHE_NO - 1) {
++      mPpttCacheType1[Index].NumberOfSets = (UINT16)CcsidrData.Bits.NumSets + 1;
++      mPpttCacheType1[Index].Associativity = (UINT16)CcsidrData.Bits.Associativity + 1;
++      mPpttCacheType1[Index].LineSize = (UINT16)( 1 << (CcsidrData.Bits.LineSize + 4));
++      mPpttCacheType1[Index].Size = mPpttCacheType1[Index].LineSize *      \
++                                    mPpttCacheType1[Index].Associativity * \
++                                    mPpttCacheType1[Index].NumberOfSets;
++      CopyMem (
++        &mPpttCacheType1[Index].Attributes,
++        &Type1Attributes,
++        sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES)
++        );
++    } else {
++      // L3 cache
++      mPpttCacheType1[Index].Size = 0x2000000;       // 32MB
++      mPpttCacheType1[Index].NumberOfSets = 0x800;
++      mPpttCacheType1[Index].Associativity = 0x0F;   // CacheAssociativity16Way
++      SetMem (
++        &mPpttCacheType1[Index].Attributes,
++        sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE_ATTRIBUTES),
++        0x0A
++        );
++      mPpttCacheType1[Index].LineSize = 0x80;        // 128byte
++    }
++  }
++}
++
++STATIC
++EFI_STATUS
++AddCoreTable (
++  IN     EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
++  IN OUT UINT32                      *PpttTableLengthRemain,
++  IN     UINT32                      Parent,
++  IN     UINT32                      ResourceNo,
++  IN     UINT32                      ProcessorId
++  )
++{
++  EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0;
++  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE     *PpttType1;
++  UINT32                                *PrivateResource;
++  UINT8                                 Index;
++  UINT32                                NextLevelCacheOffset;
++
++  if (*PpttTableLengthRemain <
++      (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) {
++    return EFI_OUT_OF_RESOURCES;
++  }
++  PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable +
++                                                        PpttTable->Length);
++  PpttType0->Type = 0;
++  SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0);
++  PpttType0->Flags.AcpiProcessorIdValid = EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID;
++  PpttType0->Parent= Parent;
++  PpttType0->AcpiProcessorId = ProcessorId;
++  PpttType0->NumberOfPrivateResources = ResourceNo;
++  PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) +
++                      ResourceNo * 4;
++
++  *PpttTableLengthRemain  -= (UINTN)PpttType0->Length;
++  PpttTable->Length += PpttType0->Length;
++  PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
++                               sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR));
++
++  // Add cache type structure
++  for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
++    if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
++      return EFI_OUT_OF_RESOURCES;
++    }
++    *PrivateResource = PpttTable->Length;
++    PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
++                                                      PpttTable->Length);
++    gBS->CopyMem (
++           PpttType1,
++           &mPpttCacheType1[Index],
++           sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
++           );
++    *PpttTableLengthRemain -= PpttType1->Length;
++    PpttTable->Length += PpttType1->Length;
++  }
++
++  NextLevelCacheOffset = *(PrivateResource - 1);
++  PrivateResource = (UINT32 *)(PpttType0 + 1);
++  // Set the next level to L2 for L1I and L1D
++  PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *) PpttTable + *PrivateResource++);
++  PpttType1->NextLevelOfCache = NextLevelCacheOffset;
++  PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *) PpttTable + *PrivateResource++);
++  PpttType1->NextLevelOfCache = NextLevelCacheOffset;
++
++  return EFI_SUCCESS;
++}
++
++STATIC
++EFI_STATUS
++AddClusterTable (
++  IN     EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
++  IN OUT UINT32                      *PpttTableLengthRemain,
++  IN     UINT32                      Parent,
++  IN     UINT32                      ResourceNo
++  )
++{
++  EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0;
++
++  if ((*PpttTableLengthRemain) <
++      (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) {
++    return EFI_OUT_OF_RESOURCES;
++  }
++  PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable +
++                                                        PpttTable->Length);
++  PpttType0->Type = 0;
++  SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0);
++  PpttType0->Parent= Parent;
++  PpttType0->NumberOfPrivateResources = ResourceNo;
++  PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) +
++                      ResourceNo * 4;
++
++  *PpttTableLengthRemain -= PpttType0->Length;
++  PpttTable->Length += PpttType0->Length;
++
++  return EFI_SUCCESS;
++}
++
++STATIC
++EFI_STATUS
++AddScclTable (
++  IN     EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
++  IN OUT UINT32                      *PpttTableLengthRemain,
++  IN     UINT32                      Parent,
++  IN     UINT32                      ResourceNo
++  )
++{
++  EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0;
++  EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE     *PpttType1;
++  UINT32                                *PrivateResource;
++
++  if (*PpttTableLengthRemain <
++      (sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) + ResourceNo * 4)) {
++    return EFI_OUT_OF_RESOURCES;
++  }
++  PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable +
++                                                        PpttTable->Length);
++  PpttType0->Type = 0;
++  SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0);
++  PpttType0->Parent= Parent;
++  PpttType0->NumberOfPrivateResources = ResourceNo;
++  PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) +
++                      ResourceNo * 4;
++
++  *PpttTableLengthRemain -= PpttType0->Length;
++  PpttTable->Length += PpttType0->Length;
++  PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
++                               sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR));
++
++  // Add cache type structure
++  if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)) {
++    return EFI_OUT_OF_RESOURCES;
++  }
++  *PrivateResource = PpttTable->Length;
++  PpttType1 = (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE *)((UINT8 *)PpttTable +
++                                                    PpttTable->Length);
++  gBS->CopyMem (
++         PpttType1,
++         &mPpttCacheType1[3],
++         sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_CACHE)
++         );
++  *PpttTableLengthRemain -= PpttType1->Length;
++  PpttTable->Length += PpttType1->Length;
++
++  return EFI_SUCCESS;
++}
++
++STATIC
++EFI_STATUS
++AddSocketTable (
++  IN     EFI_ACPI_DESCRIPTION_HEADER *PpttTable,
++  IN OUT UINT32                      *PpttTableLengthRemain,
++  IN     UINT32                      Parent,
++  IN     UINT32                      ResourceNo
++  )
++{
++  EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *PpttType0;
++  EFI_ACPI_6_2_PPTT_STRUCTURE_ID        *PpttType2;
++  UINT32                                *PrivateResource;
++  UINT8                                 Index;
++
++  if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR)) {
++    return EFI_OUT_OF_RESOURCES;
++  }
++  PpttType0 = (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR *)((UINT8 *)PpttTable +
++                                                        PpttTable->Length);
++  PpttType0->Type = 0;
++  SetMem (&PpttType0->Flags, sizeof (PpttType0->Flags), 0);
++  PpttType0->Flags.PhysicalPackage = EFI_ACPI_6_2_PPTT_PROCESSOR_ID_VALID;
++  PpttType0->Parent= Parent;
++  PpttType0->NumberOfPrivateResources = ResourceNo;
++  PpttType0->Length = sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR) +
++                      ResourceNo * 4;
++  PpttTable->Length += PpttType0->Length;
++
++  *PpttTableLengthRemain -= PpttType0->Length;
++  if (*PpttTableLengthRemain < ResourceNo * 4) {
++    return EFI_OUT_OF_RESOURCES;
++  }
++  PrivateResource = (UINT32 *)((UINT8 *)PpttType0 +
++                               sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_PROCESSOR));
++  DEBUG ((DEBUG_INFO,
++          "[Acpi PPTT]  sizeof(EFI_ACPI_6_2_PPTT_STRUCTURE_ID) = %x!\n",
++          sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)));
++
++  for (Index = 0; Index < ResourceNo; Index++, PrivateResource++) {
++    if (*PpttTableLengthRemain < sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)) {
++      return EFI_OUT_OF_RESOURCES;
++    }
++    *PrivateResource = PpttTable->Length;
++    PpttType2 = (EFI_ACPI_6_2_PPTT_STRUCTURE_ID *)((UINT8 *)PpttTable +
++                                                   PpttTable->Length);
++    gBS->CopyMem (
++           PpttType2,
++           &mPpttSocketType2[Index],
++           sizeof (EFI_ACPI_6_2_PPTT_STRUCTURE_ID)
++           );
++    *PpttTableLengthRemain -= PpttType2->Length;
++    PpttTable->Length += PpttType2->Length;
++  }
++
++  return EFI_SUCCESS;
++}
++
++STATIC
++VOID
++GetAffLvl (
++  IN     UINT64     Mpidr,
++  IN OUT UINT8      *Level3,
++  IN OUT UINT8      *Level2,
++  IN OUT UINT8      *Level1,
++  IN OUT UINT8      *Level0
++  )
++{
++  *Level3 = BitFieldRead64 (Mpidr, 32, 39);
++  *Level2 = BitFieldRead64 (Mpidr, 16, 23);
++  *Level1 = BitFieldRead64 (Mpidr, 8, 15);
++  *Level0 = BitFieldRead64 (Mpidr, 0, 7);
++}
++
++
++STATIC
++VOID
++GetApic (
++  IN     ACPI_MADT_TABLE_HEADER                 *ApicTable,
++  IN OUT EFI_ACPI_DESCRIPTION_HEADER            *PpttTable,
++  IN     UINT32                                 PpttTableLengthRemain
++)
++{
++  UINT32                Parent = 0;
++  UINT32                ResourceNo = 0;
++  ACPI_GIC_STRUCTURE    *Ptr;
++  UINT8                 AffLvl3 = 0;
++  UINT8                 AffLvl2 = 0;
++  UINT8                 AffLvl1 = 0;
++  UINT8                 AffLvl0 = 0;
++  UINTN                 SocketIndex;
++
++  for (Ptr = (ACPI_GIC_STRUCTURE *) (ApicTable + 1);
++      (UINTN) Ptr < (UINTN) ApicTable + ApicTable->Header.Length;
++      Ptr = (ACPI_GIC_STRUCTURE *) ((UINTN) Ptr + Ptr->Length)) {
++
++    // Avoid dead loop due to corrupted MADT
++    if (Ptr->Length == 0) {
++      DEBUG ((DEBUG_ERROR, "[%a:%d] - Invalid MADT sub structure at 0x%x\n",
++            __FUNCTION__, __LINE__, (UINTN) Ptr - (UINTN) ApicTable));
++      break;
++    }
++
++    if (Ptr->Type != EFI_ACPI_5_1_GIC ||
++        (Ptr->Flags & EFI_ACPI_5_1_GIC_ENABLED) == 0) {
++      continue;
++    }
++    GetAffLvl (Ptr->MPIDR, &AffLvl3, &AffLvl2, &AffLvl1, &AffLvl0);
++    // AffLvl3 is not used for Hi1620
++    // And socket index is calculated by AffLvl2
++
++    SocketIndex = AffLvl2 / MAX_SCL_PER_SOCKET;
++    if (mSocketOffset[SocketIndex] == 0) {
++      //Add socket for type0 table
++      ResourceNo = PPTT_SOCKET_COMPONENT_NO;
++      mSocketOffset[SocketIndex] = PpttTable->Length;
++      Parent = 0;
++      AddSocketTable (
++        PpttTable,
++        &PpttTableLengthRemain,
++        Parent,
++        ResourceNo
++        );
++    }
++
++    if (mScclOffset[AffLvl2] == 0) {
++      //Add SCCL for type0 table
++      ResourceNo = 1;
++      mScclOffset[AffLvl2] = PpttTable->Length ;
++      Parent = mSocketOffset[SocketIndex];
++      AddScclTable (
++        PpttTable,
++        &PpttTableLengthRemain,
++        Parent,
++        ResourceNo
++        );
++    }
++
++    if (mClusterOffset[AffLvl2][AffLvl1] == 0) {
++      // Add cluster for type0 table
++      // No private resource for cluster on Hi1620
++      ResourceNo = 0;
++      mClusterOffset[AffLvl2][AffLvl1] = PpttTable->Length ;
++      Parent = mScclOffset[AffLvl2];
++      AddClusterTable (
++        PpttTable,
++        &PpttTableLengthRemain,
++        Parent,
++        ResourceNo
++        );
++    }
++
++    //Add core for type0 table
++    ResourceNo = 3;
++    Parent = mClusterOffset[AffLvl2][AffLvl1];
++    AddCoreTable (
++      PpttTable,
++      &PpttTableLengthRemain,
++      Parent,
++      ResourceNo,
++      Ptr->AcpiProcessorUid
++      );
++  }
++}
++
++
++STATIC
++VOID
++PpttSetAcpiTable(
++  IN EFI_EVENT    Event,
++  IN VOID         *Context
++  )
++{
++  UINTN                                         AcpiTableHandle;
++  EFI_STATUS                                    Status;
++  UINT8                                         Checksum;
++  EFI_ACPI_SDT_HEADER                           *Table;
++  ACPI_MADT_TABLE_HEADER                        *ApicTable;
++  EFI_ACPI_TABLE_VERSION                        TableVersion;
++  EFI_ACPI_DESCRIPTION_HEADER                   *PpttTable;
++  UINTN                                         TableKey;
++  UINT32                                        Index0;
++  UINT32                                        PpttTableLengthRemain = 0;
++
++  gBS->CloseEvent (Event);
++
++  InitCacheInfo ();
++
++  PpttTable = (EFI_ACPI_DESCRIPTION_HEADER *)AllocateZeroPool (PPTT_TABLE_MAX_LEN);
++  gBS->CopyMem (
++         (VOID *)PpttTable,
++         &mPpttHeader,
++         sizeof (EFI_ACPI_DESCRIPTION_HEADER)
++         );
++  PpttTableLengthRemain = PPTT_TABLE_MAX_LEN - sizeof (EFI_ACPI_DESCRIPTION_HEADER);
++
++  for (Index0 = 0; Index0 < EFI_ACPI_MAX_NUM_TABLES; Index0++) {
++    Status = mAcpiSdtProtocol->GetAcpiTable (
++                                 Index0,
++                                 &Table,
++                                 &TableVersion,
++                                 &TableKey
++                                 );
++    if (EFI_ERROR (Status)) {
++      break;
++    }
++
++    // Find APIC table
++    if (Table->Signature == EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE) {
++      break;
++    }
++
++  }
++
++  if (!EFI_ERROR (Status) && (Index0 != EFI_ACPI_MAX_NUM_TABLES)) {
++    ApicTable = (ACPI_MADT_TABLE_HEADER *)Table;
++
++    GetApic (ApicTable, PpttTable, PpttTableLengthRemain);
++
++    Checksum = CalculateCheckSum8 ((UINT8 *)(PpttTable), PpttTable->Length);
++    PpttTable->Checksum = Checksum;
++
++    AcpiTableHandle = 0;
++    Status = mAcpiTableProtocol->InstallAcpiTable (
++                                   mAcpiTableProtocol,
++                                   PpttTable,
++                                   PpttTable->Length,
++                                   &AcpiTableHandle);
++  }
++
++  FreePool (PpttTable);
++  return ;
++}
++
++EFI_STATUS
++EFIAPI
++PpttEntryPoint(
++  IN EFI_HANDLE         ImageHandle,
++  IN EFI_SYSTEM_TABLE   *SystemTable
++  )
++{
++  EFI_STATUS              Status;
++  EFI_EVENT               ReadyToBootEvent;
++
++  Status = gBS->LocateProtocol (
++                  &gEfiAcpiTableProtocolGuid,
++                  NULL,
++                  (VOID **)&mAcpiTableProtocol);
++  ASSERT_EFI_ERROR (Status);
++
++  Status = gBS->LocateProtocol (
++                  &gEfiAcpiSdtProtocolGuid,
++                  NULL,
++                  (VOID **)&mAcpiSdtProtocol);
++  ASSERT_EFI_ERROR (Status);
++
++  Status = EfiCreateEventReadyToBootEx (
++             TPL_NOTIFY,
++             PpttSetAcpiTable,
++             NULL,
++             &ReadyToBootEvent
++             );
++  ASSERT_EFI_ERROR (Status);
++
++  DEBUG ((DEBUG_INFO, "Acpi Pptt init done.\n"));
++
++  return Status;
++}
+-- 
+2.17.0
+
diff --git a/v2/v2-0028-Platform-Hisilicon-D06-Enable-ACPI-PPTT.patch b/v2/v2-0028-Platform-Hisilicon-D06-Enable-ACPI-PPTT.patch
new file mode 100644
index 0000000000..a42fcaf061
--- /dev/null
+++ b/v2/v2-0028-Platform-Hisilicon-D06-Enable-ACPI-PPTT.patch
@@ -0,0 +1,41 @@
+From 1228acfd4f09f8a9c82e5648262f2cfbabd76571 Mon Sep 17 00:00:00 2001
+From: Heyi Guo <heyi.guo@linaro.org>
+Date: Sat, 30 Jun 2018 09:29:53 +0800
+Subject: [PATCH edk2-platforms v2 28/43] Platform/Hisilicon/D06: Enable ACPI
+ PPTT
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc | 1 +
+ Platform/Hisilicon/D06/D06.fdf | 2 ++
+ 2 files changed, 3 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index bec422670d..06249d8a5b 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -338,6 +338,7 @@
+   Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+   Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
++  Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf
+   #
+   # Usb Support
+   #
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index 06203dc079..5bb779d2e4 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -252,6 +252,8 @@ READ_LOCK_STATUS   = TRUE
+   INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+   INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
++  INF Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf
++
+   #
+   #Network
+   #
+-- 
+2.17.0
+
diff --git a/v2/v2-0029-Platform-Hisilicon-D06-Add-OemNicLib.patch b/v2/v2-0029-Platform-Hisilicon-D06-Add-OemNicLib.patch
new file mode 100644
index 0000000000..3a032e7b22
--- /dev/null
+++ b/v2/v2-0029-Platform-Hisilicon-D06-Add-OemNicLib.patch
@@ -0,0 +1,647 @@
+From 1fafb5508111aab60784d509985300893ace7f34 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Thu, 28 Jun 2018 11:28:35 +0800
+Subject: [PATCH edk2-platforms v2 29/43] Platform/Hisilicon/D06: Add OemNicLib
+
+OemNicLib provide nic related api like GetMac,SetMac.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                         |   1 +
+ Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf |  35 ++
+ Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c   | 570 ++++++++++++++++++++
+ 3 files changed, 606 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 06249d8a5b..e18badf3b3 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -90,6 +90,7 @@
+ 
+   LpcLib|Silicon/Hisilicon/Hi1620/Library/LpcLibHi1620/LpcLib.inf
+   SerialPortLib|ArmPlatformPkg/Library/PL011SerialPortLib/PL011SerialPortLib.inf
++  OemNicLib|Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf
+ !if $(SECURE_BOOT_ENABLE) == TRUE
+   FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ !endif
+diff --git a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf
+new file mode 100644
+index 0000000000..3b0bd2d60c
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.inf
+@@ -0,0 +1,35 @@
++#/** @file
++#
++#    Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#    Copyright (c) 2017, Linaro Limited. All rights reserved.
++#
++#    This program and the accompanying materials
++#    are licensed and made available under the terms and conditions of the BSD License
++#    which accompanies this distribution. The full text of the license may be found at
++#    http://opensource.org/licenses/bsd-license.php
++#
++#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = OemNicLib
++  FILE_GUID                      = 520F872C-FFCF-4EF3-AC01-85BDB0816DCE
++  MODULE_TYPE                    = BASE
++  VERSION_STRING                 = 1.0
++  LIBRARY_CLASS                  = OemNicLib
++
++[Sources.common]
++  OemNicLib.c
++
++[Packages]
++  ArmPkg/ArmPkg.dec
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  CpldIoLib
++  I2CLib
+diff --git a/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c
+new file mode 100644
+index 0000000000..caf931cdbb
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/OemNicLib/OemNicLib.c
+@@ -0,0 +1,570 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2017, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include <Uefi.h>
++#include <Library/CpldIoLib.h>
++#include <Library/DebugLib.h>
++#include <Library/I2CLib.h>
++#include <Library/IoLib.h>
++#include <Library/OemNicLib.h>
++
++#define CPU2_SFP2_100G_CARD_OFFSET   0x25
++#define CPU1_SFP1_LOCATE_OFFSET      0x16
++#define CPU1_SFP0_LOCATE_OFFSET      0x12
++#define CPU2_SFP1_LOCATE_OFFSET      0x21
++#define CPU2_SFP0_LOCATE_OFFSET      0x19
++#define CPU2_SFP2_10G_GE_CARD_OFFSET 0x25
++
++#define SFP_10G_SPEED   10
++#define SFP_25G_SPEED   25
++#define SFP_100G_SPEED  100
++#define SFP_GE_SPEED    1
++
++#define SFP_GE_SPEED_VAL_VENDOR_FINISAR 0x0C
++#define SFP_GE_SPEED_VAL                0x0D
++#define SFP_10G_SPEED_VAL               0x67
++#define SFP_25G_SPEED_VAL               0xFF
++
++#define CARD_PRESENT_100G               (BIT7)
++#define CARD_PRESENT_10G                (BIT0)
++#define SELECT_SFP_BY_INDEX(index)      (1 << (index - 1))
++#define SPF_SPEED_OFFSET                12
++
++#define SFP_DEVICE_ADDRESS 0x50
++#define CPU1_9545_I2C_ADDR 0x70
++#define CPU2_9545_I2C_ADDR 0x71
++
++#define FIBER_PRESENT     0
++#define CARD_PRESENT      1
++#define I2C_PORT_SFP      4
++#define CPU2_I2C_PORT_SFP 5
++
++#define SOCKET_0                 0
++#define SOCKET_1                 1
++#define EEPROM_I2C_PORT          4
++#define EEPROM_PAGE_SIZE         0x40
++#define MAC_ADDR_LEN             6
++#define I2C_OFFSET_EEPROM_ETH0   (0xc00)
++#define I2C_SLAVEADDR_EEPROM     (0x52)
++
++#pragma pack(1)
++typedef struct {
++  UINT16 Crc16;
++  UINT16 MacLen;
++  UINT8  Mac[MAC_ADDR_LEN];
++} NIC_MAC_ADDRESS;
++#pragma pack()
++
++ETH_PRODUCT_DESC gEthPdtDesc[ETH_MAX_PORT] =
++{
++    {TRUE,   ETH_SPEED_10KM,  ETH_FULL_DUPLEX, ETH_INVALID, ETH_INVALID},
++    {TRUE,   ETH_SPEED_10KM,  ETH_FULL_DUPLEX, ETH_INVALID, ETH_INVALID},
++    {FALSE,  ETH_INVALID,     ETH_INVALID,     ETH_INVALID, ETH_INVALID},
++    {FALSE,  ETH_INVALID,     ETH_INVALID,     ETH_INVALID, ETH_INVALID},
++    {TRUE,   ETH_SPEED_1000M, ETH_FULL_DUPLEX, ETH_PHY_MVL88E1512_ID, 0},
++    {TRUE,   ETH_SPEED_1000M, ETH_FULL_DUPLEX, ETH_PHY_MVL88E1512_ID, 1},
++    {FALSE,  ETH_INVALID,     ETH_INVALID,     ETH_INVALID, ETH_INVALID},
++    {FALSE,  ETH_INVALID,     ETH_INVALID,     ETH_INVALID, ETH_INVALID}
++};
++
++UINT16 CrcTable16[256] = {
++  0x0000, 0x1021, 0x2042, 0x3063, 0x4084, 0x50A5, 0x60C6, 0x70E7,
++  0x8108, 0x9129, 0xA14A, 0xB16B, 0xC18C, 0xD1AD, 0xE1CE, 0xF1EF,
++  0x1231, 0x0210, 0x3273, 0x2252, 0x52B5, 0x4294, 0x72F7, 0x62D6,
++  0x9339, 0x8318, 0xB37B, 0xA35A, 0xD3BD, 0xC39C, 0xF3FF, 0xE3DE,
++  0x2462, 0x3443, 0x0420, 0x1401, 0x64E6, 0x74C7, 0x44A4, 0x5485,
++  0xA56A, 0xB54B, 0x8528, 0x9509, 0xE5EE, 0xF5CF, 0xC5AC, 0xD58D,
++  0x3653, 0x2672, 0x1611, 0x0630, 0x76D7, 0x66F6, 0x5695, 0x46B4,
++  0xB75B, 0xA77A, 0x9719, 0x8738, 0xF7DF, 0xE7FE, 0xD79D, 0xC7BC,
++  0x48C4, 0x58E5, 0x6886, 0x78A7, 0x0840, 0x1861, 0x2802, 0x3823,
++  0xC9CC, 0xD9ED, 0xE98E, 0xF9AF, 0x8948, 0x9969, 0xA90A, 0xB92B,
++  0x5AF5, 0x4AD4, 0x7AB7, 0x6A96, 0x1A71, 0x0A50, 0x3A33, 0x2A12,
++  0xDBFD, 0xCBDC, 0xFBBF, 0xEB9E, 0x9B79, 0x8B58, 0xBB3B, 0xAB1A,
++  0x6CA6, 0x7C87, 0x4CE4, 0x5CC5, 0x2C22, 0x3C03, 0x0C60, 0x1C41,
++  0xEDAE, 0xFD8F, 0xCDEC, 0xDDCD, 0xAD2A, 0xBD0B, 0x8D68, 0x9D49,
++  0x7E97, 0x6EB6, 0x5ED5, 0x4EF4, 0x3E13, 0x2E32, 0x1E51, 0x0E70,
++  0xFF9F, 0xEFBE, 0xDFDD, 0xCFFC, 0xBF1B, 0xAF3A, 0x9F59, 0x8F78,
++  0x9188, 0x81A9, 0xB1CA, 0xA1EB, 0xD10C, 0xC12D, 0xF14E, 0xE16F,
++  0x1080, 0x00A1, 0x30C2, 0x20E3, 0x5004, 0x4025, 0x7046, 0x6067,
++  0x83B9, 0x9398, 0xA3FB, 0xB3DA, 0xC33D, 0xD31C, 0xE37F, 0xF35E,
++  0x02B1, 0x1290, 0x22F3, 0x32D2, 0x4235, 0x5214, 0x6277, 0x7256,
++  0xB5EA, 0xA5CB, 0x95A8, 0x8589, 0xF56E, 0xE54F, 0xD52C, 0xC50D,
++  0x34E2, 0x24C3, 0x14A0, 0x0481, 0x7466, 0x6447, 0x5424, 0x4405,
++  0xA7DB, 0xB7FA, 0x8799, 0x97B8, 0xE75F, 0xF77E, 0xC71D, 0xD73C,
++  0x26D3, 0x36F2, 0x0691, 0x16B0, 0x6657, 0x7676, 0x4615, 0x5634,
++  0xD94C, 0xC96D, 0xF90E, 0xE92F, 0x99C8, 0x89E9, 0xB98A, 0xA9AB,
++  0x5844, 0x4865, 0x7806, 0x6827, 0x18C0, 0x08E1, 0x3882, 0x28A3,
++  0xCB7D, 0xDB5C, 0xEB3F, 0xFB1E, 0x8BF9, 0x9BD8, 0xABBB, 0xBB9A,
++  0x4A75, 0x5A54, 0x6A37, 0x7A16, 0x0AF1, 0x1AD0, 0x2AB3, 0x3A92,
++  0xFD2E, 0xED0F, 0xDD6C, 0xCD4D, 0xBDAA, 0xAD8B, 0x9DE8, 0x8DC9,
++  0x7C26, 0x6C07, 0x5C64, 0x4C45, 0x3CA2, 0x2C83, 0x1CE0, 0x0CC1,
++  0xEF1F, 0xFF3E, 0xCF5D, 0xDF7C, 0xAF9B, 0xBFBA, 0x8FD9, 0x9FF8,
++  0x6E17, 0x7E36, 0x4E55, 0x5E74, 0x2E93, 0x3EB2, 0x0ED1, 0x1EF0,
++};
++
++EFI_STATUS
++GetSfpSpeed (
++  UINT16 Socket,
++  UINT16 SfpNum,
++  UINT8* FiberSpeed
++  )
++{
++  EFI_STATUS  Status;
++  I2C_DEVICE  SpdDev;
++  UINT8       SpdReg;
++  UINT8       SfpSpeed;
++  UINT32      RegAddr;
++  UINT16      I2cAddr;
++  UINT32      SfpPort;
++
++  SfpSpeed = 0x0;
++  if (Socket == SOCKET_1) {
++    I2cAddr =  CPU2_9545_I2C_ADDR;
++    SfpPort = CPU2_I2C_PORT_SFP;
++  } else {
++    I2cAddr =  CPU1_9545_I2C_ADDR;
++    SfpPort = I2C_PORT_SFP;
++  }
++
++  Status = I2CInit (Socket, SfpPort, Normal);
++  if (EFI_ERROR (Status))
++  {
++      DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Socket%d Call I2CInit failed! p1=0x%x.\n",
++             __FUNCTION__, __LINE__, Socket, Status));
++      return Status;
++  }
++
++  SpdDev.Socket = Socket;
++  SpdDev.DeviceType         =  DEVICE_TYPE_SPD;
++  SpdDev.Port               =  SfpPort;
++  SpdDev.SlaveDeviceAddress =  I2cAddr;
++  RegAddr                   =  0x0;
++  SpdReg                    =  1 << (SfpNum - 1);
++
++  Status = I2CWrite (&SpdDev, RegAddr, 1, &SpdReg);
++  if (EFI_ERROR (Status)) {
++      DEBUG ((DEBUG_ERROR, "I2CWrite Error =%r.\n", Status));
++      return Status;
++  }
++
++  SpdDev.Socket = Socket;
++  SpdDev.DeviceType         =  DEVICE_TYPE_SPD;
++  SpdDev.Port               =  SfpPort;
++  SpdDev.SlaveDeviceAddress =  SFP_DEVICE_ADDRESS;
++
++  RegAddr                   =  SPF_SPEED_OFFSET;
++  Status = I2CRead (&SpdDev, RegAddr, 1, &SfpSpeed);
++  if (EFI_ERROR (Status)) {
++      DEBUG ((DEBUG_ERROR, "I2CRead Error =%r.\n", Status));
++      return Status;
++  }
++
++  DEBUG ((DEBUG_INFO, "BR, Nominal, Nominal signalling rate, SfpSpeed:    0x%x\n",
++         SfpSpeed));
++
++  if (SfpSpeed == SFP_10G_SPEED_VAL) {
++    *FiberSpeed = SFP_10G_SPEED;
++  } else if (SfpSpeed == SFP_25G_SPEED_VAL) {
++    *FiberSpeed = SFP_25G_SPEED;
++  } else if ((SfpSpeed == SFP_GE_SPEED_VAL) ||
++             (SfpSpeed == SFP_GE_SPEED_VAL_VENDOR_FINISAR)) {
++    *FiberSpeed = SFP_GE_SPEED;
++  }
++
++  return EFI_SUCCESS;
++}
++
++//Fiber1Type/Fiber2Type/Fiber3Type return: SFP_10G_SPEED, SFP_100G_SPEED, SFP_GE_SPEED
++UINT32
++GetCpu2FiberType (
++  UINT8* Fiber1Type,
++  UINT8* Fiber2Type,
++  UINT8* Fiber100Ge
++  )
++{
++  EFI_STATUS  Status;
++  UINT16      SfpNum1;
++  UINT8       SfpSpeed1;
++  UINT16      SfpNum2;
++  UINT8       SfpSpeed2;
++
++  SfpNum1 = 0x1;
++  SfpSpeed1 = SFP_10G_SPEED;
++  SfpNum2 = 0x2;
++  SfpSpeed2 = SFP_10G_SPEED;
++  *Fiber100Ge = 0x0;
++  *Fiber1Type = SFP_10G_SPEED;
++  *Fiber2Type = SFP_10G_SPEED;
++
++  if ((ReadCpldReg (CPU2_SFP2_100G_CARD_OFFSET) & CARD_PRESENT_100G) != 0) {
++    // 100 Ge card
++    *Fiber1Type = SFP_10G_SPEED;
++    *Fiber2Type = SFP_10G_SPEED;
++    *Fiber100Ge = SFP_100G_SPEED;
++    DEBUG ((DEBUG_ERROR,"Detect Fiber SFP_100G is Present, Set 100Ge\n"));
++  } else if ((ReadCpldReg (CPU2_SFP2_10G_GE_CARD_OFFSET) & CARD_PRESENT_10G) != 0) {
++    *Fiber100Ge = 0x0;
++    *Fiber1Type = SFP_10G_SPEED;
++    *Fiber2Type = SFP_10G_SPEED;
++    if (ReadCpldReg (CPU2_SFP0_LOCATE_OFFSET) == FIBER_PRESENT) {
++      // Fiber detected in CPU2 slot0, read speed via i2c
++      Status = GetSfpSpeed (SOCKET_1, SfpNum1, &SfpSpeed1);
++      if (EFI_ERROR (Status)) {
++        DEBUG((DEBUG_ERROR,
++               "Get Socket1 Sfp%d Speed Error: %r.\n",
++               SfpNum1,
++               Status));
++        return Status;
++      }
++      if (SfpSpeed1 == SFP_25G_SPEED) {
++        // P1 don't support 25G, so set speed to 10G
++        *Fiber1Type = SFP_10G_SPEED;
++      } else {
++        *Fiber1Type = SfpSpeed1;
++      }
++    } else {
++      // No fiber, set speed to 10G
++      *Fiber1Type = SFP_10G_SPEED;
++    }
++
++    if (ReadCpldReg (CPU2_SFP1_LOCATE_OFFSET) == FIBER_PRESENT) {
++      // Fiber detected in CPU2 slot1, read speed via i2c
++      Status = GetSfpSpeed (SOCKET_1, SfpNum2, &SfpSpeed2);
++      if (EFI_ERROR (Status)) {
++        DEBUG ((DEBUG_ERROR, "Get Sfp%d Speed Error: %r.\n", SfpNum2, Status));
++        return Status;
++      }
++      if (SfpSpeed2 == SFP_25G_SPEED) {
++        *Fiber2Type = SFP_10G_SPEED;
++      } else {
++        *Fiber2Type = SfpSpeed2;
++      }
++    } else {
++      // No fiber, set speed to 10G
++      *Fiber2Type = SFP_10G_SPEED;
++    }
++  } else {
++    // 100Ge/10Ge/Ge Fiber is not found.
++    *Fiber1Type = SFP_10G_SPEED;
++    *Fiber2Type = SFP_10G_SPEED;
++    *Fiber100Ge = 0x0;
++  }
++
++  return EFI_SUCCESS;
++}
++
++//Fiber1Type/Fiber2Type return: SFP_10G_SPEED, SFP_25G_SPEED, SFP_GE_SPEED
++UINT32
++GetCpu1FiberType (
++  UINT8* Fiber1Type,
++  UINT8* Fiber2Type
++  )
++{
++  EFI_STATUS  Status;
++  UINT16      SfpNum1;
++  UINT8       SfpSpeed1;
++  UINT16      SfpNum2;
++  UINT8       SfpSpeed2;
++
++  SfpNum1 = 0x1;
++  SfpSpeed1 = SFP_10G_SPEED;
++  SfpNum2 = 0x2;
++  SfpSpeed2 = SFP_10G_SPEED;
++  *Fiber1Type = SFP_10G_SPEED;
++  *Fiber2Type = SFP_10G_SPEED;
++  // Fiber detected in CPU1 slot0, read speed via i2c
++  if (ReadCpldReg (CPU1_SFP0_LOCATE_OFFSET) == FIBER_PRESENT) {
++    Status = GetSfpSpeed (SOCKET_0, SfpNum1, &SfpSpeed1);
++    if (EFI_ERROR (Status)) {
++      DEBUG ((DEBUG_ERROR, "Get Socket0 Sfp%d Speed Error: %r.\n",
++              SfpNum1, Status));
++      return Status;
++    }
++    *Fiber1Type = SfpSpeed1;
++  } else {
++    *Fiber1Type = SFP_10G_SPEED;
++  }
++
++  // Fiber detected in CPU1 slot1, read speed via i2c
++  if (ReadCpldReg (CPU1_SFP1_LOCATE_OFFSET) == FIBER_PRESENT) {
++    Status = GetSfpSpeed (SOCKET_0, SfpNum2, &SfpSpeed2);
++    if (EFI_ERROR (Status)) {
++      *Fiber2Type = SFP_10G_SPEED;
++      DEBUG ((DEBUG_ERROR, "Get Sfp%d Speed Error: %r.\n", SfpNum2, Status));
++      return Status;
++    }
++    *Fiber2Type = SfpSpeed2;
++  } else {
++    *Fiber2Type = SFP_10G_SPEED;
++  }
++
++  return EFI_SUCCESS;
++}
++
++UINT16 MakeCrcCheckSum (
++  UINT8 *Buffer,
++  UINT32 Length
++  )
++{
++  UINT16 StartCRC = 0;
++
++  if (Length > SIZE_512KB) {
++    return 0;
++  }
++
++  if (Buffer == NULL) {
++    return 0;
++  }
++
++  while (Length) {
++    StartCRC = CrcTable16 [((UINT8) ((StartCRC >> 8) & 0xff)) ^ *(Buffer++)] ^
++               ((UINT16) (StartCRC << 8));
++    Length--;
++  }
++
++  return StartCRC;
++}
++
++
++EFI_STATUS
++OemGetMacE2prom(
++  IN  UINT32 Port,
++  OUT UINT8  *Addr
++  )
++{
++  I2C_DEVICE       I2cDev = {0};
++  EFI_STATUS       Status;
++  UINT16           I2cOffset;
++  UINT16           Crc16;
++  NIC_MAC_ADDRESS  MacDesc = {0};
++  UINT16           RemainderMacOffset;
++  UINT16           LessSizeOfPage;
++  UINT32           I = 0;
++
++  Status = I2CInit (0, EEPROM_I2C_PORT, Normal);
++  if (EFI_ERROR (Status))
++  {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n",
++            __FUNCTION__, __LINE__, Status));
++    return Status;
++  }
++
++  I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof (NIC_MAC_ADDRESS));
++
++  I2cDev.DeviceType = DEVICE_TYPE_E2PROM;
++  I2cDev.Port = EEPROM_I2C_PORT;
++  I2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
++  I2cDev.Socket = 0;
++  RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE;
++  LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset;
++  //The length of NIC_MAC_ADDRESS is 10 bytes long,
++  //It surly less than EEPROM page size, so we could
++  //code as below, check the address whether across the page boundary,
++  //and split the data when across page boundary.
++  if (sizeof (NIC_MAC_ADDRESS) <= LessSizeOfPage) {
++    Status = I2CRead (&I2cDev, I2cOffset, sizeof (NIC_MAC_ADDRESS), (UINT8 *) &MacDesc);
++  } else {
++    Status = I2CRead (&I2cDev, I2cOffset, LessSizeOfPage, (UINT8 *) &MacDesc);
++    if (!EFI_ERROR (Status)) {
++      Status |= I2CRead (
++                  &I2cDev,
++                  I2cOffset + LessSizeOfPage,
++                  sizeof (NIC_MAC_ADDRESS) - LessSizeOfPage,
++                  (UINT8 *) &MacDesc + LessSizeOfPage
++                );
++    }
++  }
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Call I2cRead failed! p1=0x%x.\n",
++            __FUNCTION__, __LINE__, Status));
++    return Status;
++  }
++
++  Crc16 = MakeCrcCheckSum (
++            (UINT8 *) & (MacDesc.MacLen),
++            sizeof (MacDesc.MacLen) + sizeof (MacDesc.Mac)
++          );
++  if ((Crc16 != MacDesc.Crc16) || (Crc16 == 0)) {
++    return EFI_NOT_FOUND;
++  }
++
++  for (I = 0; I < MAC_ADDR_LEN; I++) {
++    Addr[I] = MacDesc.Mac[I];
++  }
++
++  return EFI_SUCCESS;
++}
++
++
++EFI_STATUS
++OemSetMacE2prom (
++  IN UINT32 Port,
++  IN UINT8 *Addr
++  )
++{
++  I2C_DEVICE       I2cDev = {0};
++  EFI_STATUS       Status;
++  UINT16           I2cOffset;
++  NIC_MAC_ADDRESS  MacDesc = {0};
++  UINT32           I;
++  UINT16           RemainderMacOffset;
++  UINT16           LessSizeOfPage;
++
++  I = 0;
++  MacDesc.MacLen = MAC_ADDR_LEN;
++
++  for (I = 0; I < MAC_ADDR_LEN; I++) {
++    MacDesc.Mac[I] = Addr[I];
++  }
++
++  MacDesc.Crc16 = MakeCrcCheckSum (
++                      (UINT8 *) & (MacDesc.MacLen),
++                      sizeof (MacDesc.MacLen) + MAC_ADDR_LEN
++                    );
++
++  Status = I2CInit (0, EEPROM_I2C_PORT, Normal);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Call I2CInit failed! p1=0x%x.\n",
++           __FUNCTION__, __LINE__, Status));
++    return Status;
++  }
++
++  I2cOffset = I2C_OFFSET_EEPROM_ETH0 + (Port * sizeof (NIC_MAC_ADDRESS));
++
++  I2cDev.DeviceType = DEVICE_TYPE_E2PROM;
++  I2cDev.Port = EEPROM_I2C_PORT;
++  I2cDev.SlaveDeviceAddress = I2C_SLAVEADDR_EEPROM;
++  I2cDev.Socket = 0;
++  RemainderMacOffset = I2cOffset % EEPROM_PAGE_SIZE;
++  LessSizeOfPage = EEPROM_PAGE_SIZE - RemainderMacOffset;
++  //The length of NIC_MAC_ADDRESS is 10 bytes long,
++  //It surly less than EEPROM page size, so we could
++  //code as below, check the address whether across the page boundary,
++  //and split the data when across page boundary.
++  if (sizeof (NIC_MAC_ADDRESS) <= LessSizeOfPage) {
++    Status = I2CWrite (
++               &I2cDev,
++               I2cOffset,
++               sizeof (NIC_MAC_ADDRESS),
++               (UINT8 *) &MacDesc
++             );
++  } else {
++    Status = I2CWrite (&I2cDev, I2cOffset, LessSizeOfPage, (UINT8 *) &MacDesc);
++    if (!EFI_ERROR (Status)) {
++      Status |= I2CWrite (
++                  &I2cDev,
++                  I2cOffset + LessSizeOfPage,
++                  sizeof (NIC_MAC_ADDRESS) - LessSizeOfPage,
++                  (UINT8 *) &MacDesc + LessSizeOfPage
++                );
++    }
++  }
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Call I2cWrite failed! p1=0x%x.\n",
++            __FUNCTION__, __LINE__, Status));
++    return Status;
++  }
++  return EFI_SUCCESS;
++}
++
++EFI_STATUS
++EFIAPI
++OemGetMac (
++  IN OUT EFI_MAC_ADDRESS *Mac,
++  IN     UINTN           Port
++  )
++{
++  EFI_STATUS Status;
++
++  if (Mac == NULL) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Mac buffer is null!\n",
++            __FUNCTION__, __LINE__));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Status = OemGetMacE2prom (Port, Mac->Addr);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR,
++      "[%a]:[%dL] Cannot get MAC from EEPROM, Status: %r; using default MAC.\n",
++      __FUNCTION__, __LINE__, Status));
++
++    Mac->Addr[0] = 0x00;
++    Mac->Addr[1] = 0x18;
++    Mac->Addr[2] = 0x82;
++    Mac->Addr[3] = 0x2F;
++    Mac->Addr[4] = 0x02;
++    Mac->Addr[5] = Port;
++    return EFI_SUCCESS;
++  }
++
++  return EFI_SUCCESS;
++}
++
++EFI_STATUS
++EFIAPI
++OemSetMac (
++  IN EFI_MAC_ADDRESS *Mac,
++  IN UINTN           Port
++  )
++{
++  EFI_STATUS Status;
++
++  if (Mac == NULL) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Mac buffer is null!\n",
++            __FUNCTION__, __LINE__));
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Status = OemSetMacE2prom (Port, Mac->Addr);
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Set mac failed!\n", __FUNCTION__, __LINE__));
++    return Status;
++  }
++
++  return EFI_SUCCESS;
++}
++
++UINT32
++OemEthFindFirstSP (
++  VOID
++  )
++{
++  UINT32 I;
++
++  for (I = 0; I < ETH_MAX_PORT; I++) {
++    if (gEthPdtDesc[I].Valid == TRUE) {
++      return I;
++    }
++  }
++
++  return ETH_INVALID;
++}
++
++ETH_PRODUCT_DESC *
++OemEthInit (
++  UINT32 port
++  )
++{
++  return (ETH_PRODUCT_DESC *)(&(gEthPdtDesc[port]));
++}
++
++
++BOOLEAN
++OemIsInitEth (
++  UINT32 Port
++  )
++{
++  return TRUE;
++}
+-- 
+2.17.0
+
diff --git a/v2/v2-0030-Platform-Hisilicon-D06-Add-OemNicConfig2P-Driver.patch b/v2/v2-0030-Platform-Hisilicon-D06-Add-OemNicConfig2P-Driver.patch
new file mode 100644
index 0000000000..4cca5f67cc
--- /dev/null
+++ b/v2/v2-0030-Platform-Hisilicon-D06-Add-OemNicConfig2P-Driver.patch
@@ -0,0 +1,204 @@
+From 0c98fb7c786568f6188414aec8caca11d93956f1 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Thu, 28 Jun 2018 15:44:35 +0800
+Subject: [PATCH edk2-platforms v2 30/43] Platform/Hisilicon/D06: Add
+ OemNicConfig2P Driver
+
+This Driver provide Get/Set Mac function.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                         |  2 +-
+ Platform/Hisilicon/D06/D06.fdf                                         |  2 +-
+ Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf | 43 ++++++++++++
+ Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h     | 25 +++++++
+ Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c   | 71 ++++++++++++++++++++
+ 5 files changed, 141 insertions(+), 2 deletions(-)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index e18badf3b3..5571028f42 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -285,7 +285,7 @@
+   #
+   ArmPkg/Drivers/CpuDxe/CpuDxe.inf
+   MdeModulePkg/Core/RuntimeDxe/RuntimeDxe.inf
+-
++  Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf
+ 
+ !if $(SECURE_BOOT_ENABLE) == TRUE
+   MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf {
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index 5bb779d2e4..184d5d4dcf 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -174,7 +174,7 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Universal/SecurityStubDxe/SecurityStubDxe.inf
+   INF Platform/Hisilicon/D06/Drivers/SFC/SfcDxeDriver.inf
+ 
+-
++  INF Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf
+   INF Silicon/Hisilicon/Drivers/FlashFvbDxe/FlashFvbDxe.inf
+   INF MdeModulePkg/Universal/FaultTolerantWriteDxe/FaultTolerantWriteDxe.inf
+   INF MdeModulePkg/Universal/Variable/RuntimeDxe/VariableRuntimeDxe.inf
+diff --git a/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf b/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf
+new file mode 100644
+index 0000000000..a91f2b6005
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.inf
+@@ -0,0 +1,43 @@
++#/** @file
++#
++#    Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved.
++#    Copyright (c) 2016-2018, Linaro Limited. All rights reserved.
++#
++#    This program and the accompanying materials
++#    are licensed and made available under the terms and conditions of the BSD License
++#    which accompanies this distribution. The full text of the license may be found at
++#    http://opensource.org/licenses/bsd-license.php
++#
++#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = OemNicConfigPangea
++  FILE_GUID                      = edc95319-ebe9-4c38-96af-1d203fb85231
++  MODULE_TYPE                    = DXE_DRIVER
++  VERSION_STRING                 = 1.0
++  ENTRY_POINT                    = OemNicConfigEntry
++
++[Sources.common]
++  OemNicConfig2P.c
++
++[Packages]
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[Protocols]
++  gHisiBoardNicProtocolGuid       ##Produce
++
++[LibraryClasses]
++  DebugLib
++  IoLib
++  OemNicLib
++  UefiBootServicesTableLib
++  UefiDriverEntryPoint
++
++[Depex]
++  TRUE
+diff --git a/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h b/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h
+new file mode 100644
+index 0000000000..35228fdf1d
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig.h
+@@ -0,0 +1,25 @@
++/** @file
++*
++*  Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2016-2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#ifndef __OEM_NIC_CONFIG_H__
++#define __OEM_NIC_CONFIG_H__
++
++#include <Uefi.h>
++#include <Library/DebugLib.h>
++#include <Library/IoLib.h>
++#include <Library/OemNicLib.h>
++#include <Library/UefiBootServicesTableLib.h>
++#include <Protocol/HisiBoardNicProtocol.h>
++#endif
+diff --git a/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c b/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c
+new file mode 100644
+index 0000000000..c01c49150a
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Drivers/OemNicConfig2PHi1620/OemNicConfig2P.c
+@@ -0,0 +1,71 @@
++/** @file
++*
++*  Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2016-2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include <OemNicConfig.h>
++
++
++EFI_STATUS
++EFIAPI OemGetMac2P (
++  IN OUT EFI_MAC_ADDRESS *Mac,
++  IN     UINTN           Port
++  )
++{
++  OemGetMac (Mac, Port);
++
++  return EFI_SUCCESS;
++}
++
++EFI_STATUS
++EFIAPI OemSetMac2P (
++  IN EFI_MAC_ADDRESS *Mac,
++  IN UINTN           Port
++  )
++{
++  OemSetMac (Mac, Port);
++
++  return EFI_SUCCESS;
++}
++
++HISI_BOARD_NIC_PROTOCOL mHisiBoardNicProtocol2P = {
++  .GetMac = OemGetMac2P,
++  .SetMac = OemSetMac2P,
++};
++
++
++EFI_STATUS
++EFIAPI
++OemNicConfigEntry (
++  IN EFI_HANDLE           ImageHandle,
++  IN EFI_SYSTEM_TABLE     *SystemTable
++  )
++{
++  EFI_STATUS Status;
++
++  Status = gBS->InstallProtocolInterface (
++                  &ImageHandle,
++                  &gHisiBoardNicProtocolGuid,
++                  EFI_NATIVE_INTERFACE,
++                  &mHisiBoardNicProtocol2P
++                  );
++
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL] Install Protocol failed %r\n",
++        __FUNCTION__, __LINE__, Status));
++    return Status;
++  }
++
++  return EFI_SUCCESS;
++}
++
+-- 
+2.17.0
+
diff --git a/v2/v2-0031-Hisilicon-D0x-Update-SMBIOS-type9-info.patch b/v2/v2-0031-Hisilicon-D0x-Update-SMBIOS-type9-info.patch
new file mode 100644
index 0000000000..1d2e66d9e1
--- /dev/null
+++ b/v2/v2-0031-Hisilicon-D0x-Update-SMBIOS-type9-info.patch
@@ -0,0 +1,325 @@
+From 1f6fc1e19fc8168dd3b161d308474e0a833df265 Mon Sep 17 00:00:00 2001
+From: Sun Yuanchen <sunyuanchen@huawei.com>
+Date: Mon, 2 Jul 2018 19:53:39 +0800
+Subject: [PATCH edk2-platforms v2 31/43] Hisilicon/D0x: Update SMBIOS type9
+ info
+
+Move board level code to OemMiscLibD0x for unifying D0x.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Sun Yuanchen <sunyuanchen@huawei.com>
+---
+ Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf |  1 +
+ Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf     |  1 +
+ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf     |  4 +
+ Platform/Hisilicon/D06/Include/Library/CpldD06.h                   |  2 +
+ Silicon/Hisilicon/Include/Library/OemMiscLib.h                     |  1 +
+ Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c   | 24 ++++++
+ Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c       | 27 +++++-
+ Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c       | 90 ++++++++++++++++++++
+ Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c   | 14 +--
+ 9 files changed, 151 insertions(+), 13 deletions(-)
+
+diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
+index 310bbaea84..0fa7fdf80f 100644
+--- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
++++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.inf
+@@ -34,6 +34,7 @@
+   Silicon/Hisilicon/HisiPkg.dec
+ 
+ [LibraryClasses]
++  BaseMemoryLib
+   PcdLib
+   TimerLib
+ 
+diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
+index bf44ff7440..022c3e940a 100644
+--- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
++++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.inf
+@@ -33,6 +33,7 @@
+   Silicon/Hisilicon/HisiPkg.dec
+ 
+ [LibraryClasses]
++  BaseMemoryLib
+   PcdLib
+   TimerLib
+ 
+diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+index 8f68f7cec5..bd984a6fe3 100644
+--- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
++++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.inf
+@@ -30,9 +30,13 @@
+   ArmPkg/ArmPkg.dec
+   MdeModulePkg/MdeModulePkg.dec
+   MdePkg/MdePkg.dec
++  Platform/Hisilicon/D06/D06.dec
+   Silicon/Hisilicon/HisiPkg.dec
+ 
+ [LibraryClasses]
++  BaseMemoryLib
++  CpldIoLib
++  IoLib
+   PcdLib
+   SerdesLib
+   TimerLib
+diff --git a/Platform/Hisilicon/D06/Include/Library/CpldD06.h b/Platform/Hisilicon/D06/Include/Library/CpldD06.h
+index be3548c8d1..ec9b49f4e7 100644
+--- a/Platform/Hisilicon/D06/Include/Library/CpldD06.h
++++ b/Platform/Hisilicon/D06/Include/Library/CpldD06.h
+@@ -29,6 +29,8 @@
+ #define CPLD_LOGIC_COMPILE_DAY           (0x3)
+ 
+ #define CPLD_RISER_PRSNT_FLAG             0x40
++#define CPU1_RISER_PRESENT                BIT6
++#define CPU0_RISER_PRESENT                BIT7
+ #define CPLD_RISER2_BOARD_ID              0x44
+ 
+ #define CPLD_X8_X8_X8_BOARD_ID            0x92
+diff --git a/Silicon/Hisilicon/Include/Library/OemMiscLib.h b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+index efecb9aa77..86ea6a1b3d 100644
+--- a/Silicon/Hisilicon/Include/Library/OemMiscLib.h
++++ b/Silicon/Hisilicon/Include/Library/OemMiscLib.h
+@@ -34,6 +34,7 @@ typedef struct _REPORT_PCIEDIDVID2BMC{
+     UINTN   Slot;
+ }REPORT_PCIEDIDVID2BMC;
+ extern REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX];
++extern VOID GetPciDidVid (REPORT_PCIEDIDVID2BMC *Report);
+ 
+ BOOLEAN OemIsSocketPresent (UINTN Socket);
+ VOID CoreSelectBoot(VOID);
+diff --git a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
+index fa1039bda1..c80500276f 100644
+--- a/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
++++ b/Platform/Hisilicon/D03/Library/OemMiscLib2P/OemMiscLib2PHi1610.c
+@@ -15,6 +15,7 @@
+ 
+ #include <Uefi.h>
+ 
++#include <Library/BaseMemoryLib.h>
+ #include <Library/DebugLib.h>
+ #include <Library/IoLib.h>
+ #include <Library/TimerLib.h>
+@@ -31,6 +32,29 @@ REPORT_PCIEDIDVID2BMC  PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
+       {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+ };
+ 
++REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = {
++  {0x79,0,0,0},
++  {0xFF,0xFF,0xFF,1},
++  {0xC1,0,0,2},
++  {0xF9,0,0,3},
++  {0xFF,0xFF,0xFF,4},
++  {0x11,0,0,5},
++  {0x31,0,0,6},
++  {0x21,0,0,7}
++};
++
++VOID
++GetPciDidVid (
++  REPORT_PCIEDIDVID2BMC *Report
++  )
++{
++  if (OemIsMpBoot ()) {
++    (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P, sizeof (PcieDeviceToReport_2P));
++  } else {
++    (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport, sizeof (PcieDeviceToReport));
++  }
++}
++
+ // Right now we only support 1P
+ BOOLEAN OemIsSocketPresent (UINTN Socket)
+ {
+diff --git a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
+index b17eeada16..4c4c944dbe 100644
+--- a/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
++++ b/Platform/Hisilicon/D05/Library/OemMiscLibD05/OemMiscLibD05.c
+@@ -1,7 +1,7 @@
+ /** @file
+ *
+-*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+-*  Copyright (c) 2016, Linaro Limited. All rights reserved.
++*  Copyright (c) 2016 - 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2016 - 2018, Linaro Limited. All rights reserved.
+ *
+ *  This program and the accompanying materials
+ *  are licensed and made available under the terms and conditions of the BSD License
+@@ -16,6 +16,7 @@
+ #include <PlatformArch.h>
+ #include <Uefi.h>
+ 
++#include <Library/BaseMemoryLib.h>
+ #include <Library/DebugLib.h>
+ #include <Library/IoLib.h>
+ #include <Library/LpcLib.h>
+@@ -37,6 +38,28 @@ REPORT_PCIEDIDVID2BMC  PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
+   {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+ };
+ 
++REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = {
++  {0x79,0,0,0},
++  {0xFF,0xFF,0xFF,1},
++  {0xC1,0,0,2},
++  {0xF9,0,0,3},
++  {0xFF,0xFF,0xFF,4},
++  {0x11,0,0,5},
++  {0x31,0,0,6},
++  {0x21,0,0,7}
++};
++
++VOID
++GetPciDidVid (
++  REPORT_PCIEDIDVID2BMC *Report
++  )
++{
++  if (OemIsMpBoot ()) {
++    (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P, sizeof (PcieDeviceToReport_2P));
++  } else {
++    (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport, sizeof (PcieDeviceToReport));
++  }
++}
+ 
+ BOOLEAN OemIsSocketPresent (UINTN Socket)
+ {
+diff --git a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+index 2cd360d49f..be11c88992 100644
+--- a/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
++++ b/Platform/Hisilicon/D06/Library/OemMiscLibD06/OemMiscLibD06.c
+@@ -15,6 +15,8 @@
+ 
+ #include <Uefi.h>
+ #include <PlatformArch.h>
++#include <Library/BaseMemoryLib.h>
++#include <Library/CpldD06.h>
+ #include <Library/DebugLib.h>
+ #include <Library/IoLib.h>
+ #include <Library/LpcLib.h>
+@@ -33,6 +35,94 @@ REPORT_PCIEDIDVID2BMC PcieDeviceToReport[PCIEDEVICE_REPORT_MAX] = {
+   {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+ };
+ 
++//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (X16 + X8)
++REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type1 [PCIEDEVICE_REPORT_MAX] = {
++  {0x01,0,0,0},
++  {0x03,0,0,1},
++  {0xFF,0xFF,0xFF,2},
++  {0x81,0,0,3},
++  {0x84,0,0,4},
++  {0xFF,0xFF,0xFF,5}
++};
++
++//Cpu0 Riser type is (X16 + X8) & Cpu1 Riser type is (3 * X8)
++REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type2 [PCIEDEVICE_REPORT_MAX] = {
++  {0x01,0,0,0},
++  {0x03,0,0,1},
++  {0xFF,0xFF,0xFF,2},
++  {0xFF,0xFF,0xFF,3},
++  {0x81,0,0,4},
++  {0x85,0,0,5}
++};
++
++//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (X16 + X8)
++REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type3 [PCIEDEVICE_REPORT_MAX] = {
++  {0xFF,0xFF,0xFF,0},
++  {0x01,0,0,1},
++  {0x04,0,0,2},
++  {0x81,0,0,3},
++  {0x84,0,0,4},
++  {0xFF,0xFF,0xFF,5}
++};
++
++//Cpu0 Riser type is (3 * X8) & Cpu1 Riser type is (3 * X8)
++REPORT_PCIEDIDVID2BMC PcieDeviceToReport_2P_Type4 [PCIEDEVICE_REPORT_MAX] = {
++  {0xFF,0xFF,0xFF,0},
++  {0x01,0,0,1},
++  {0x04,0,0,2},
++  {0xFF,0xFF,0xFF,3},
++  {0x81,0,0,4},
++  {0x85,0,0,5}
++};
++
++VOID
++GetPciDidVid (
++  REPORT_PCIEDIDVID2BMC *Report
++  )
++{
++  UINT32                             PresentStatus;
++  UINT32                             CardType;
++  UINT8                              Cpu0CardType = 0;
++  UINT8                              Cpu1CardType = 0;
++
++  PresentStatus = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER_PRSNT_FLAG);
++  CardType = MmioRead32 (CPLD_BASE_ADDRESS + CPLD_RISER2_BOARD_ID);
++
++  // Offset 0x40: Bit7 = 1 CPU0 Riser present
++  if ((PresentStatus & CPU0_RISER_PRESENT) != 0) {
++    Cpu0CardType = (UINT8) (PresentStatus >> 8);
++  }
++
++  // Offset 0x40: Bit6 = 1 CPU1 Riser present
++  if ((PresentStatus & CPU1_RISER_PRESENT) != 0) {
++    Cpu1CardType = (UINT8)CardType;
++  }
++
++  if (OemIsMpBoot ()) {
++    if (Cpu0CardType == CPLD_X16_X8_BOARD_ID) {
++      if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) {
++        (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type1,
++                        sizeof (PcieDeviceToReport_2P_Type1));
++      } else {
++        (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type2,
++                        sizeof (PcieDeviceToReport_2P_Type2));
++      }
++    } else {
++      if (Cpu1CardType == CPLD_X16_X8_BOARD_ID) {
++        (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type3,
++                        sizeof (PcieDeviceToReport_2P_Type3));
++      } else {
++        (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport_2P_Type4,
++                        sizeof (PcieDeviceToReport_2P_Type4));
++      }
++    }
++  } else {
++    (VOID)CopyMem ((VOID *)Report, (VOID *)PcieDeviceToReport,
++                    sizeof (PcieDeviceToReport));
++  }
++}
++
++
+ // Right now we only support 1P
+ BOOLEAN
+ OemIsSocketPresent (
+diff --git a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
+index 8d8dacd3e0..cc1131577d 100644
+--- a/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
++++ b/Silicon/Hisilicon/Drivers/Smbios/AddSmbiosType9/AddSmbiosType9.c
+@@ -18,12 +18,6 @@
+ extern SMBIOS_TABLE_TYPE9 gPcieSlotInfo[];
+ extern UINT8 OemGetPcieSlotNumber ();
+ 
+-REPORT_PCIEDIDVID2BMC  PcieDeviceToReport_2P[PCIEDEVICE_REPORT_MAX] = {
+-      {67,0,0,0},
+-      {225,0,0,3},
+-      {0xFFFF,0xFFFF,0xFFFF,0xFFFF},
+-      {0xFFFF,0xFFFF,0xFFFF,0xFFFF}
+-};
+ VOID
+ EFIAPI
+ UpdateSmbiosType9Info(
+@@ -41,11 +35,9 @@ UpdateSmbiosType9Info(
+     UINTN                              FunctionNumber;
+     UINTN                              Index;
+     REPORT_PCIEDIDVID2BMC              ReportPcieDidVid[PCIEDEVICE_REPORT_MAX];
+-    if(OemIsMpBoot()){
+-        (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport_2P,sizeof(PcieDeviceToReport_2P));
+-    } else {
+-        (VOID)CopyMem((VOID *)ReportPcieDidVid,(VOID *)PcieDeviceToReport,sizeof(PcieDeviceToReport));
+-    }
++
++    GetPciDidVid ((VOID *) ReportPcieDidVid);
++
+     Status = gBS->LocateHandleBuffer (
+                                       ByProtocol,
+                                       &gEfiPciIoProtocolGuid,
+-- 
+2.17.0
+
diff --git a/v2/v2-0032-Platform-Hisilicon-D06-Add-EarlyConfigPeim-peim.patch b/v2/v2-0032-Platform-Hisilicon-D06-Add-EarlyConfigPeim-peim.patch
new file mode 100644
index 0000000000..a8cebaed4c
--- /dev/null
+++ b/v2/v2-0032-Platform-Hisilicon-D06-Add-EarlyConfigPeim-peim.patch
@@ -0,0 +1,227 @@
+From 4fdd5ee39f9486e5cb599c6a5227cfdcf3e9cbbe Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Mon, 2 Jul 2018 16:54:26 +0800
+Subject: [PATCH edk2-platforms v2 32/43] Platform/Hisilicon/D06: Add
+ EarlyConfigPeim peim
+
+This peim configuare SMMU,BSP,MN(Miscellaneous Node).
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                |   1 +
+ Platform/Hisilicon/D06/D06.fdf                                |   1 +
+ Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf |  50 +++++++++
+ Silicon/Hisilicon/Include/Library/OemAddressMapLib.h          |   2 +
+ Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c   | 107 ++++++++++++++++++++
+ 5 files changed, 161 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 5571028f42..3de09ea870 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -263,6 +263,7 @@
+   MdeModulePkg/Universal/FaultTolerantWritePei/FaultTolerantWritePei.inf
+   MdeModulePkg/Universal/Variable/Pei/VariablePei.inf
+ 
++  Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf
+   Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+ 
+   MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index 184d5d4dcf..bd3ea47226 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -359,6 +359,7 @@ READ_LOCK_STATUS   = TRUE
+   INF ArmPkg/Drivers/CpuPei/CpuPei.inf
+   INF MdeModulePkg/Universal/PCD/Pei/Pcd.inf
+   INF IntelFrameworkModulePkg/Universal/StatusCode/Pei/StatusCodePei.inf
++  INF Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf
+ 
+   INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+ 
+diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf
+new file mode 100644
+index 0000000000..8296ee02de
+--- /dev/null
++++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf
+@@ -0,0 +1,50 @@
++#/** @file
++#
++#    Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#    Copyright (c) 2017, Linaro Limited. All rights reserved.
++#
++#    This program and the accompanying materials
++#    are licensed and made available under the terms and conditions of the BSD License
++#    which accompanies this distribution. The full text of the license may be found at
++#    http://opensource.org/licenses/bsd-license.php
++#
++#    THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#    WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#**/
++
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = EarlyConfigPeimD06
++  FILE_GUID                      = FB8C65EB-0199-40C3-A82B-029921A9E9B3
++  MODULE_TYPE                    = PEIM
++  VERSION_STRING                 = 1.0
++  ENTRY_POINT                    = EarlyConfigEntry
++
++[Sources.common]
++  EarlyConfigPeimD06.c
++
++[Packages]
++  ArmPkg/ArmPkg.dec
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  ArmLib
++  CacheMaintenanceLib
++  DebugLib
++  IoLib
++  PcdLib
++  PeimEntryPoint
++  PlatformSysCtrlLib
++
++[Pcd]
++  gHisiTokenSpaceGuid.PcdMailBoxAddress
++  gHisiTokenSpaceGuid.PcdPeriSubctrlAddress
++  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
++
++[Depex]
++## As we will clean mailbox in this module, need to wait memory init complete
++  gEfiPeiMemoryDiscoveredPpiGuid
+diff --git a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
+index 332a79343f..b330be09ba 100644
+--- a/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
++++ b/Silicon/Hisilicon/Include/Library/OemAddressMapLib.h
+@@ -16,6 +16,8 @@
+ #ifndef _OEM_ADDRESS_MAP_LIB_H_
+ #define _OEM_ADDRESS_MAP_LIB_H_
+ 
++#include "PlatformArch.h"
++
+ typedef struct _DDRC_BASE_ID{
+     UINTN  Base;
+     UINTN  Id;
+diff --git a/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c
+new file mode 100644
+index 0000000000..0790f7941a
+--- /dev/null
++++ b/Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.c
+@@ -0,0 +1,107 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++
++#include <Uefi.h>
++#include <Library/ArmLib.h>
++#include <Library/CacheMaintenanceLib.h>
++#include <Library/DebugLib.h>
++#include <Library/IoLib.h>
++#include <Library/OemAddressMapLib.h>
++#include <Library/OemMiscLib.h>
++#include <Library/PcdLib.h>
++#include <Library/PlatformSysCtrlLib.h>
++#include <PiPei.h>
++
++#define PERI_SUBCTRL_BASE                               (0x40000000)
++#define MDIO_SUBCTRL_BASE                               (0x60000000)
++#define PCIE2_SUBCTRL_BASE                              (0xA0000000)
++#define PCIE0_SUBCTRL_BASE                              (0xB0000000)
++#define ALG_BASE                                        (0xD0000000)
++
++#define SC_BROADCAST_EN_REG                             (0x16220)
++#define SC_BROADCAST_SCL1_ADDR0_REG                     (0x16230)
++#define SC_BROADCAST_SCL1_ADDR1_REG                     (0x16234)
++#define SC_BROADCAST_SCL2_ADDR0_REG                     (0x16238)
++#define SC_BROADCAST_SCL2_ADDR1_REG                     (0x1623C)
++#define SC_BROADCAST_SCL3_ADDR0_REG                     (0x16240)
++#define SC_BROADCAST_SCL3_ADDR1_REG                     (0x16244)
++#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG                 (0x1000)
++#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG         (0x1010)
++#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG         (0x1014)
++#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG         (0x1018)
++#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG         (0x101C)
++#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG                  (0x1200)
++#define SC_ITS_M3_INT_MUX_SEL_REG                       (0x21F0)
++#define SC_TM_CLKEN0_REG                                (0x2050)
++
++#define SC_TM_CLKEN0_REG_VALUE                          (0x3)
++#define SC_BROADCAST_EN_REG_VALUE                       (0x7)
++#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE0              (0x0)
++#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE1              (0x40016260)
++#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE2              (0x60016260)
++#define SC_BROADCAST_SCLx_ADDRx_REG_VALUE3              (0x400)
++#define SC_ITS_M3_INT_MUX_SEL_REG_VALUE                 (0x7)
++#define PCIE_SUBCTRL_SC_REMAP_CTRL_REG_VALUE0           (0x0)
++#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE0          (0x27)
++#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE1          (0x2F)
++#define PCIE_SUBCTRL_SC_DISP_DAW_EN_REG_VALUE2          (0x77)
++#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY3_REG_VALUE0  (0x178033)
++#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY4_REG_VALUE0  (0x17003c)
++#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE0  (0x15003d)
++#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY5_REG_VALUE1  (0x170035)
++#define PCIE_SUBCTRL_SC_DISPATCH_DAW_ARRAY6_REG_VALUE0  (0x16003e)
++
++STATIC
++VOID
++QResetAp (
++  VOID
++  )
++{
++  MmioWrite64 (FixedPcdGet64 (PcdMailBoxAddress), 0x0);
++  (VOID)WriteBackInvalidateDataCacheRange (
++          (VOID *)FixedPcdGet64 (PcdMailBoxAddress),
++          sizeof (UINT64)
++          );
++
++  //SCCL A
++  if (!PcdGet64 (PcdTrustedFirmwareEnable)) {
++    StartupAp ();
++  }
++}
++
++
++EFI_STATUS
++EFIAPI
++EarlyConfigEntry (
++  IN       EFI_PEI_FILE_HANDLE  FileHandle,
++  IN CONST EFI_PEI_SERVICES     **PeiServices
++  )
++{
++  DEBUG ((DEBUG_INFO,"SMMU CONFIG........."));
++  (VOID)SmmuConfigForBios ();
++  DEBUG ((DEBUG_INFO,"Done\n"));
++
++  DEBUG ((DEBUG_INFO,"AP CONFIG........."));
++  (VOID)QResetAp ();
++  DEBUG ((DEBUG_INFO,"Done\n"));
++
++  DEBUG ((DEBUG_INFO,"MN CONFIG........."));
++  (VOID)MN_CONFIG ();
++  DEBUG ((DEBUG_INFO,"Done\n"));
++
++  return EFI_SUCCESS;
++}
++
+-- 
+2.17.0
+
diff --git a/v2/v2-0033-Platform-Hisilicon-D06-Add-PciHostBridgeLib.patch b/v2/v2-0033-Platform-Hisilicon-D06-Add-PciHostBridgeLib.patch
new file mode 100644
index 0000000000..cb4e6a1a07
--- /dev/null
+++ b/v2/v2-0033-Platform-Hisilicon-D06-Add-PciHostBridgeLib.patch
@@ -0,0 +1,716 @@
+From c2bd4bf799df6f029c4e9be6d571763380ccf967 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Thu, 5 Jul 2018 09:50:49 +0800
+Subject: [PATCH edk2-platforms v2 33/43] Platform/Hisilicon/D06: Add
+ PciHostBridgeLib
+
+PciHostBridgeLib which is need by PciHostBridgeDxe, provide
+root bridges and deal with resource conflict.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                       |   2 +-
+ Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf |  36 ++
+ Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c   | 635 ++++++++++++++++++++
+ 3 files changed, 672 insertions(+), 1 deletion(-)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 3de09ea870..c6de9f04ad 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -418,7 +418,7 @@
+     <LibraryClasses>
+       PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+       PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+-      PciHostBridgeLib|MdeModulePkg/Library/PciHostBridgeLibNull/PciHostBridgeLibNull.inf
++      PciHostBridgeLib|Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+   }
+ 
+   MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+diff --git a/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+new file mode 100644
+index 0000000000..8a998681a3
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.inf
+@@ -0,0 +1,36 @@
++## @file
++#
++#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++#  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution. The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#
++##
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = PciHostBridgeLib
++  FILE_GUID                      = 61b7276a-fc67-11e5-82fd-47ea9896dd5d
++  MODULE_TYPE                    = DXE_DRIVER
++  VERSION_STRING                 = 1.0
++  LIBRARY_CLASS                  = PciHostBridgeLib|DXE_DRIVER
++
++[Sources]
++  PciHostBridgeLib.c
++
++[Packages]
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++
++[LibraryClasses]
++  BaseLib
++  DebugLib
++  DevicePathLib
++  MemoryAllocationLib
++  UefiBootServicesTableLib
+diff --git a/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c
+new file mode 100644
+index 0000000000..d1a436d9bc
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Library/PciHostBridgeLib/PciHostBridgeLib.c
+@@ -0,0 +1,635 @@
++/** @file
++
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.<BR>
++  Copyright (c) 2018, Linaro Limited. All rights reserved.<BR>
++
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++#include <PiDxe.h>
++#include <Library/DebugLib.h>
++#include <Library/DevicePathLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include <Library/PciHostBridgeLib.h>
++#include <Protocol/PciHostBridgeResourceAllocation.h>
++#include <Protocol/PciRootBridgeIo.h>
++
++#define ENUM_HB_NUM 8
++
++#define EFI_PCI_SUPPORT   (EFI_PCI_ATTRIBUTE_ISA_MOTHERBOARD_IO | \
++                           EFI_PCI_ATTRIBUTE_IDE_SECONDARY_IO | \
++                           EFI_PCI_ATTRIBUTE_IDE_PRIMARY_IO | \
++                           EFI_PCI_ATTRIBUTE_ISA_IO_16  | \
++                           EFI_PCI_ATTRIBUTE_VGA_MEMORY | \
++                           EFI_PCI_ATTRIBUTE_VGA_IO_16  | \
++                           EFI_PCI_ATTRIBUTE_VGA_PALETTE_IO_16)
++
++#define EFI_PCI_ATTRIBUTE  EFI_PCI_SUPPORT
++
++#pragma pack(1)
++typedef struct {
++  ACPI_HID_DEVICE_PATH     AcpiDevicePath;
++  EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
++} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
++#pragma pack ()
++
++STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath [ENUM_HB_NUM] = {
++//Host Bridge 0
++  {
++    {
++      {
++        ACPI_DEVICE_PATH,
++        ACPI_DP,
++        {
++          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
++          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
++        }
++      },
++      EISA_PNP_ID(0x0A03), // PCI
++      0
++    },
++    {
++      END_DEVICE_PATH_TYPE,
++      END_ENTIRE_DEVICE_PATH_SUBTYPE,
++      {
++        END_DEVICE_PATH_LENGTH,
++        0
++      }
++    }
++  },
++
++//Host Bridge 2
++  {
++    {
++      {
++        ACPI_DEVICE_PATH,
++        ACPI_DP,
++        {
++          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
++          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
++        }
++      },
++      EISA_PNP_ID(0x0A04), // PCI
++      0
++    },
++    {
++      END_DEVICE_PATH_TYPE,
++      END_ENTIRE_DEVICE_PATH_SUBTYPE,
++      {
++        END_DEVICE_PATH_LENGTH,
++        0
++      }
++    }
++  },
++
++//Host Bridge 4
++  {
++    {
++      {
++        ACPI_DEVICE_PATH,
++        ACPI_DP,
++        {
++          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
++          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
++        }
++      },
++      EISA_PNP_ID(0x0A05), // PCI
++      0
++    },
++    {
++      END_DEVICE_PATH_TYPE,
++      END_ENTIRE_DEVICE_PATH_SUBTYPE,
++      {
++        END_DEVICE_PATH_LENGTH,
++        0
++      }
++    }
++  },
++
++//Host Bridge 5
++  {
++    {
++      {
++        ACPI_DEVICE_PATH,
++        ACPI_DP,
++        {
++          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
++          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
++        }
++      },
++      EISA_PNP_ID(0x0A06), // PCI
++      0
++    },
++    {
++      END_DEVICE_PATH_TYPE,
++      END_ENTIRE_DEVICE_PATH_SUBTYPE,
++      {
++        END_DEVICE_PATH_LENGTH,
++        0
++      }
++    }
++  },
++
++//Host Bridge 6
++  {
++    {
++      {
++        ACPI_DEVICE_PATH,
++        ACPI_DP,
++        {
++          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
++          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
++        }
++      },
++      EISA_PNP_ID(0x0A07), // PCI
++      0
++    },
++    {
++      END_DEVICE_PATH_TYPE,
++      END_ENTIRE_DEVICE_PATH_SUBTYPE,
++      {
++        END_DEVICE_PATH_LENGTH,
++        0
++      }
++    }
++  },
++
++//Host Bridge 8
++  {
++    {
++      {
++        ACPI_DEVICE_PATH,
++        ACPI_DP,
++        {
++          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
++          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
++        }
++      },
++      EISA_PNP_ID(0x0A08), // PCI
++      0
++    },
++    {
++      END_DEVICE_PATH_TYPE,
++      END_ENTIRE_DEVICE_PATH_SUBTYPE,
++      {
++        END_DEVICE_PATH_LENGTH,
++        0
++      }
++    }
++  },
++
++//Host Bridge 10
++  {
++    {
++      {
++        ACPI_DEVICE_PATH,
++        ACPI_DP,
++        {
++          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
++          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
++        }
++      },
++      EISA_PNP_ID(0x0A09), // PCI
++      0
++    },
++    {
++      END_DEVICE_PATH_TYPE,
++      END_ENTIRE_DEVICE_PATH_SUBTYPE,
++      {
++        END_DEVICE_PATH_LENGTH,
++        0
++      }
++    }
++  },
++
++//Host Bridge 11
++  {
++    {
++      {
++        ACPI_DEVICE_PATH,
++        ACPI_DP,
++        {
++          (UINT8)sizeof (ACPI_HID_DEVICE_PATH),
++          (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)
++        }
++      },
++      EISA_PNP_ID(0x0A0A), // PCI
++      0
++    },
++    {
++      END_DEVICE_PATH_TYPE,
++      END_ENTIRE_DEVICE_PATH_SUBTYPE,
++      {
++        END_DEVICE_PATH_LENGTH,
++        0
++      }
++    }
++  }
++};
++
++STATIC PCI_ROOT_BRIDGE gRootBridge [ENUM_HB_NUM] = {
++//Host Bridge 0
++  {
++    0,                                              // Segment
++    EFI_PCI_SUPPORT,                                // Supports
++    EFI_PCI_ATTRIBUTE,                              // Attributes
++    TRUE,                                           // DmaAbove4G
++    FALSE,                                          // NoExtendedConfigSpace
++    FALSE,                                          // ResourceAssigned
++    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
++    { // Bus
++      00,
++      0x3F
++    },
++    { // Io (32K)
++      0,
++      0x7FFF
++    },
++    { // Mem (256M - 64K - 1)
++      0xE0000000,
++      0xEFFEFFFF
++    },
++    { // MemAbove4G (8T + 256G)
++      0x80000000000,
++      0x83FFFFFFFFF
++    },
++    { // PMem
++      0xE0000000,
++      0xEFFEFFFF
++    },
++    { // PMemAbove4G
++      0x80000000000,
++      0x83FFFFFFFFF
++    },
++    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[0]
++  },
++
++  //Host Bridge 2
++  {
++    0,                                              // Segment
++    EFI_PCI_SUPPORT,                                // Supports
++    EFI_PCI_ATTRIBUTE,                              // Attributes
++    TRUE,                                           // DmaAbove4G
++    FALSE,                                          // NoExtendedConfigSpace
++    FALSE,                                          // ResourceAssigned
++    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes
++    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
++    { // Bus
++      0x7A,
++      0x7A
++    },
++    { // Io
++      MAX_UINT32,
++      0
++    },
++    { // Mem
++      MAX_UINT32,
++      0
++    },
++    { // MemAbove4G
++      0x20c000000,
++      0x20c1fffff
++    },
++    { // PMem
++      MAX_UINT32,
++      0
++    },
++    { // PMemAbove4G
++      MAX_UINT64,
++      0
++    },
++    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[1]
++  },
++
++  //Host Bridge 4
++  {
++    0,                                              // Segment
++    EFI_PCI_SUPPORT,                                // Supports
++    EFI_PCI_ATTRIBUTE,                              // Attributes
++    TRUE,                                           // DmaAbove4G
++    FALSE,                                          // NoExtendedConfigSpace
++    FALSE,                                          // ResourceAssigned
++    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes
++    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
++    { // Bus
++      0x7C,
++      0x7D
++    },
++    { // Io
++      MAX_UINT32,
++      0
++    },
++    { // Mem
++      MAX_UINT32,
++      0
++    },
++    { // MemAbove4G
++      0x120000000,
++      0x13fffffff
++    },
++    { // PMem
++      MAX_UINT32,
++      0
++    },
++    { // PMemAbove4G
++      MAX_UINT64,
++      0
++    },
++    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[2]
++  },
++
++  //Host Bridge 5
++  {
++    0,                                              // Segment
++    EFI_PCI_SUPPORT,                                // Supports
++    EFI_PCI_ATTRIBUTE,                              // Attributes
++    TRUE,                                           // DmaAbove4G
++    FALSE,                                          // NoExtendedConfigSpace
++    FALSE,                                          // ResourceAssigned
++    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes
++    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
++    { // Bus
++      0x74,
++      0x76
++    },
++    { // Io
++      MAX_UINT32,
++      0
++    },
++    { // Mem
++      0xA2000000,
++      0xA2ffffff
++    },
++    { // MemAbove4G
++      0x144000000,
++      0x147ffffff
++    },
++    { // PMem
++      MAX_UINT32,
++      0
++    },
++    { // PMemAbove4G
++      MAX_UINT64,
++      0
++    },
++    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[3]
++  },
++  //Host Bridge 6
++  {
++    0,                                              // Segment
++    EFI_PCI_SUPPORT,                                // Supports
++    EFI_PCI_ATTRIBUTE,                              // Attributes
++    TRUE,                                           // DmaAbove4G
++    FALSE,                                          // NoExtendedConfigSpace
++    FALSE,                                          // ResourceAssigned
++    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
++    { // Bus
++      0x80,
++      0x9F
++    },
++    { // Io (32K)
++      0x0,
++      0x7FFF
++    },
++    { // Mem (256M - 64K -1)
++      0xF0000000,
++      0xFFFEFFFF
++    },
++    { // MemAbove4G (8T + 256G)
++      0x480000000000,
++      0x483FFFFFFFFF
++    },
++    { // PMem
++      0xF0000000,
++      0xFFFEFFFF
++    },
++    { // PMemAbove4G
++      0x480000000000,
++      0x483FFFFFFFFF
++    },
++    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[4]
++  },
++
++  //Host Bridge 8
++  {
++    0,                                              // Segment
++    EFI_PCI_SUPPORT,                                // Supports
++    EFI_PCI_ATTRIBUTE,                              // Attributes
++    TRUE,                                           // DmaAbove4G
++    FALSE,                                          // NoExtendedConfigSpace
++    FALSE,                                          // ResourceAssigned
++    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes
++    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
++    { // Bus
++      0xBA,
++      0xBA
++    },
++    { // Io
++      MAX_UINT32,
++      0
++    },
++    { // Mem
++      MAX_UINT32,
++      0
++    },
++    { // MemAbove4G
++      0x40020c000000,
++      0x40020c1fffff
++    },
++    { // PMem
++      MAX_UINT32,
++      0
++    },
++    { // PMemAbove4G
++      MAX_UINT64,
++      0
++    },
++    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[5]
++  },
++
++  //Host Bridge 10
++  {
++    0,                                              // Segment
++    EFI_PCI_SUPPORT,                                // Supports
++    EFI_PCI_ATTRIBUTE,                              // Attributes
++    TRUE,                                           // DmaAbove4G
++    FALSE,                                          // NoExtendedConfigSpace
++    FALSE,                                          // ResourceAssigned
++    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes
++    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
++    { // Bus
++      0xBC,
++      0xBD
++    },
++    { // Io
++      MAX_UINT32,
++      0
++    },
++    { // Mem
++      MAX_UINT32,
++      0
++    },
++    { // MemAbove4G
++      0x400120000000,
++      0x40013fffffff
++    },
++    { // PMem
++      MAX_UINT32,
++      0
++    },
++    { // PMemAbove4G
++      MAX_UINT64,
++      0
++    },
++    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[6]
++  },
++
++  //Host Bridge 11
++  {
++    0,                                              // Segment
++    EFI_PCI_SUPPORT,                                // Supports
++    EFI_PCI_ATTRIBUTE,                              // Attributes
++    TRUE,                                           // DmaAbove4G
++    FALSE,                                          // NoExtendedConfigSpace
++    FALSE,                                          // ResourceAssigned
++    EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM |          // AllocationAttributes
++    EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
++    { // Bus
++      0xB4,
++      0xB6
++    },
++    { // Io
++      MAX_UINT32,
++      0
++    },
++    { // Mem
++      0xA3000000,
++      0xA3ffffff
++    },
++    { // MemAbove4G
++      0x400144000000,
++      0x400147ffffff
++    },
++    { // PMem
++      MAX_UINT32,
++      0
++    },
++    { // PMemAbove4G
++      MAX_UINT64,
++      0
++    },
++    (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath[7]
++  }
++
++};
++
++/**
++  Return all the root bridge instances in an array.
++
++  @param Count  Return the count of root bridge instances.
++
++  @return All the root bridge instances in an array.
++          The array should be passed into PciHostBridgeFreeRootBridges()
++          when it's not used.
++**/
++PCI_ROOT_BRIDGE *
++EFIAPI
++PciHostBridgeGetRootBridges (
++  UINTN *Count
++  )
++{
++  *Count = ENUM_HB_NUM;
++
++  return gRootBridge;
++}
++
++/**
++  Free the root bridge instances array returned from PciHostBridgeGetRootBridges().
++
++  @param Bridges The root bridge instances array.
++  @param Count   The count of the array.
++**/
++VOID
++EFIAPI
++PciHostBridgeFreeRootBridges (
++  PCI_ROOT_BRIDGE *Bridges,
++  UINTN           Count
++  )
++{
++  if (Bridges == NULL && Count == 0) {
++    return;
++  }
++
++  do {
++    --Count;
++    FreePool (Bridges[Count].DevicePath);
++  } while (Count > 0);
++
++  FreePool (Bridges);
++}
++
++STATIC CONST CHAR16 mPciHostBridgeLibAcpiAddressSpaceTypeStr[][4] = {
++  L"Mem", L"I/O", L"Bus"
++};
++
++/**
++  Inform the platform that the resource conflict happens.
++
++  @param HostBridgeHandle Handle of the Host Bridge.
++  @param Configuration    Pointer to PCI I/O and PCI memory resource
++                          descriptors. The Configuration contains the resources
++                          for all the root bridges. The resource for each root
++                          bridge is terminated with END descriptor and an
++                          additional END is appended indicating the end of the
++                          entire resources. The resource descriptor field
++                          values follow the description in
++                          EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
++                          .SubmitResources().
++**/
++VOID
++EFIAPI
++PciHostBridgeResourceConflict (
++  EFI_HANDLE                        HostBridgeHandle,
++  VOID                              *Configuration
++  )
++{
++  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
++  UINTN                             RootBridgeIndex;
++
++  DEBUG ((DEBUG_ERROR, "\n PciHostBridge: Resource conflict happens!\n"));
++  RootBridgeIndex = 0;
++  Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)Configuration;
++  while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
++    DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
++    for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
++      ASSERT (Descriptor->ResType <
++              ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)
++              );
++      DEBUG ((DEBUG_ERROR, " %s: Length/Alignment = 0x%lx / 0x%lx\n",
++              mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType],
++              Descriptor->AddrLen, Descriptor->AddrRangeMax
++              ));
++      if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
++        DEBUG ((DEBUG_ERROR, "     Granularity/SpecificFlag = %ld / %02x%s\n",
++                Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag,
++                ((Descriptor->SpecificFlag &
++                  EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
++                  ) != 0) ? L" (Prefetchable)" : L""
++                ));
++      }
++    }
++    //
++    // Skip the END descriptor for root bridge
++    //
++    ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
++    Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
++                   (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
++                   );
++  }
++}
+-- 
+2.17.0
+
diff --git a/v2/v2-0034-Hisilicon-D06-add-apei-driver.patch b/v2/v2-0034-Hisilicon-D06-add-apei-driver.patch
new file mode 100644
index 0000000000..6b704417a9
--- /dev/null
+++ b/v2/v2-0034-Hisilicon-D06-add-apei-driver.patch
@@ -0,0 +1,2508 @@
+From dc942bcd12eb5573beda66cef0d848471327d655 Mon Sep 17 00:00:00 2001
+From: Luqi Jiang <jiangluqi@huawei.com>
+Date: Fri, 6 Jul 2018 11:22:30 +0800
+Subject: [PATCH edk2-platforms v2 34/43] Hisilicon/D06: add apei driver
+
+This driver provide a means for the platform to
+convey error information to OSPM.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Luqi Jiang <jiangluqi@huawei.com>
+---
+ Platform/Hisilicon/D06/D06.dsc                           |   1 +
+ Platform/Hisilicon/D06/D06.fdf                           |   1 +
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf           |  64 ++++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h             |  41 +++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.h        |  43 +++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.h        | 146 ++++++++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h | 110 ++++++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.h        | 146 ++++++++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.h        |  59 +++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h    |  43 +++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c             | 108 ++++++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.c        |  92 +++++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.c        | 349 ++++++++++++++++++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c | 330 +++++++++++++++++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.c        | 374 ++++++++++++++++++++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.c        | 119 +++++++
+ Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c    | 337 ++++++++++++++++++
+ 17 files changed, 2363 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index c6de9f04ad..9550e0d497 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -340,6 +340,7 @@
+   Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+   Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
+ 
++  Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf
+   Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf
+   #
+   # Usb Support
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index bd3ea47226..90379b8558 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -251,6 +251,7 @@ READ_LOCK_STATUS   = TRUE
+ 
+   INF RuleOverride=ACPITABLE Silicon/Hisilicon/Hi1620/Hi1620AcpiTables/AcpiTablesHi1620.inf
+   INF Silicon/Hisilicon/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf
++  INF Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf
+ 
+   INF Silicon/Hisilicon/Hi1620/Pptt/Pptt.inf
+ 
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf
+new file mode 100644
+index 0000000000..7a75968da1
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.inf
+@@ -0,0 +1,64 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++[defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = AcpiApei
++  FILE_GUID                      = E9570C39-EF68-4fc6-B921-C1954A87CCD2
++  MODULE_TYPE                    = DXE_DRIVER
++  VERSION_STRING                 = 1.0
++  ENTRY_POINT                    = ApeiEntryPoint
++
++[sources.common]
++  Apei.c
++  Bert/bert.c
++  Bert/bert.h
++  Einj/einj.c
++  Einj/einj.h
++  Erst/erst.c
++  Erst/erst.h
++  Hest/hest.c
++  Hest/hest.h
++  ErrorSource/Ghes.c
++  ErrorSource/Ghes.h
++  OemApeiHi1620.c
++
++[Packages]
++  ArmPkg/ArmPkg.dec
++  MdePkg/MdePkg.dec
++  Silicon/Hisilicon/HisiPkg.dec
++
++[LibraryClasses]
++  ArmSmcLib
++  BaseMemoryLib
++  DebugLib
++  HobLib
++  TimerLib
++  UefiDriverEntryPoint
++  UefiRuntimeServicesTableLib
++
++[Guids]
++  gOemConfigGuid
++
++[Protocols]
++  gEfiAcpiSdtProtocolGuid
++  gEfiAcpiTableProtocolGuid                     # PROTOCOL ALWAYS_CONSUMED
++
++[Pcd]
++  gHisiTokenSpaceGuid.PcdCpldBaseAddress
++  gHisiTokenSpaceGuid.PcdTrustedFirmwareEnable
++
++[Depex]
++  gEfiAcpiTableProtocolGuid AND gEfiAcpiSdtProtocolGuid
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h
+new file mode 100644
+index 0000000000..ed8ec417cb
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.h
+@@ -0,0 +1,41 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++#ifndef _APEI_H_
++#define _APEI_H_
++
++#include <IndustryStandard/Acpi.h>
++#include <Protocol/AcpiSystemDescriptionTable.h>
++#include <Protocol/AcpiTable.h>
++
++#define EFI_ACPI_MAX_NUM_TABLES         20
++#define PRIVATE_ARM_SMC_ID_APEI         0x83000100
++#define PRIVATE_ARM_SMC_ID_APEI_S       0x83000101
++
++typedef struct {
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE  *HestCorrectedErrorGhesV2;
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE  *HestFatalErrorGhesV2;
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE  *HestRecoverableErrorGhesV2;
++  EFI_PHYSICAL_ADDRESS                                            HestTableAddress;
++  EFI_PHYSICAL_ADDRESS                                            EinjTableAddress;
++  EFI_PHYSICAL_ADDRESS                                            EinjDataStruct;
++  VOID                                                            *ErstContext;
++} APEI_TRUSTED_FIRMWARE_STRUCTURE;
++
++extern EFI_ACPI_TABLE_PROTOCOL       *mAcpiTableProtocol;
++extern EFI_ACPI_SDT_PROTOCOL         *mAcpiSdtProtocol;
++extern APEI_TRUSTED_FIRMWARE_STRUCTURE     *mApeiTrustedfirmwareData;
++
++
++#endif    // _APEI_H_
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.h
+new file mode 100644
+index 0000000000..36a0c58966
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.h
+@@ -0,0 +1,43 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#ifndef _BERT_H_
++#define _BERT_H_
++
++#include "Apei.h"
++#include <Guid/Cper.h>
++
++typedef struct _BERT_CONTEXT {
++  EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER   *BertHeader;
++  VOID                                          *Block;
++  UINT32                                        BlockSize;
++} BERT_CONTEXT;
++
++EFI_STATUS
++OemInitBertTable (
++  IN EFI_HANDLE    ImageHandle
++);
++VOID
++BertSetAcpiTable (
++  IN BERT_CONTEXT *Context
++);
++EFI_STATUS
++BertHeaderCreator (
++  BERT_CONTEXT  *Context,
++  UINT32        ErrorBlockSize
++);
++
++
++#endif    // _BERT_H_
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.h
+new file mode 100644
+index 0000000000..85aa52f450
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.h
+@@ -0,0 +1,146 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#ifndef _EINJ_H_
++#define _EINJ_H_
++
++#include "Apei.h"
++
++#define EINJ_ACTION_NO             10
++#define EINJ_BEGIN_OPERATION_VALUE 0xFFFF
++#define EINJ_END_OPERATION_VALUE   0
++#define EINJ_WRITE_MASK            0xFFFFFFFF
++#define EINJ_READ_VALUE            0xFFFF
++#define EINJ_READ_MASK             0xFFFFFFFF
++
++#define EINJ_TRIGGER_ERROR_ACTION_NO                                    1
++
++#define EFI_ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS                       0x08
++#define EFI_ACPI_EINJ_GET_EXCUTE_OPERATION_TIMINGS                      0x09
++
++
++extern EFI_ACPI_TABLE_PROTOCOL            *mAcpiTableProtocol;
++extern EFI_ACPI_SDT_PROTOCOL              *mAcpiSdtProtocol;
++extern APEI_TRUSTED_FIRMWARE_STRUCTURE    *mApeiTrustedfirmwareData;
++
++//
++// Error Type Definition
++//
++#define EINJ_PROCESSOR_CORRECTABLE                                      BIT0
++#define EINJ_PROCESSOR_UNCORRECTABLE_NONFATAL                           BIT1
++#define EINJ_PROCESSOR_UNCORRECTABLE_FATAL                              BIT2
++#define EINJ_MEMORY_CORRECTABLE                                         BIT3
++#define EINJ_MEMORY_UNCORRECTABLE_NONFATAL                              BIT4
++#define EINJ_MEMORY_UNCORRECTABLE_FATAL                                 BIT5
++#define EINJ_PCIE_CORRECTABLE                                           BIT6
++#define EINJ_PCIE_UNCORRECTABLE_NONFATAL                                BIT7
++#define EINJ_PCIE_UNCORRECTABLE_FATAL                                   BIT8
++#define EINJ_PLATFORM_CORRECTABLE                                       BIT9
++#define EINJ_PLATFORM_UNCORRECTABLE_NONFATAL                            BIT10
++#define EINJ_PLATFORM_UNCORRECTABLE_FATAL                               BIT11
++#define EINJ_VENDOR_DEFINED_ERROR_TYPE                                  BIT31
++
++#define EINJ_PROCESSOR_APIC_VALID                                       BIT0
++#define EINJ_MEMORY_ADDRESS_VALID                                       BIT1
++#define EINJ_PCIE_SBDF_VALID                                            BIT2
++
++///
++/// EINJ Table
++///
++typedef struct {
++  EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER        EinjTableHeader;
++  EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY    EinjInstructionEntry[EINJ_ACTION_NO];
++} EINJ_TABLE;
++
++typedef struct {
++  EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE           TriggerErrorHeader;
++  EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY    ErrorInstructionEntry[EINJ_TRIGGER_ERROR_ACTION_NO];
++} EINJ_TRIGGER_ERROR_ACTION;
++
++typedef struct {
++  UINT32 Reserved: 8;
++  UINT32 Function: 3;
++  UINT32 Device: 5;
++  UINT32 PrimaryOrDeviceBus: 8;
++  UINT32 Segment: 8;
++} EINJ_PCIE_SBDF;
++
++typedef struct {
++  UINT32         ErrorType;
++  UINT32         VendorErrorTypeOffset;
++  UINT32         Flags;
++  UINT32         ApicId;
++  UINT64         MemAddress;
++  UINT64         MemAddressRange;
++  EINJ_PCIE_SBDF PcieSBDF;
++} EINJ_SET_ERROR_TYPE_WITH_ADDRESS;
++
++typedef struct {
++  UINT32 Length;
++  UINT32 SBDF;
++  UINT16 VendorId;
++  UINT16 DeviceId;
++  UINT8  RevId;
++  UINT8  Reserved[3];
++} EINJ_VENDOR_ERROR_TYPE;
++
++typedef struct {
++  UINT64                           OperationBegin;
++  UINT64                           ErrorType;
++  UINT64                           ErrorCapabilities;
++  UINT64                           BusyStatus;
++  UINT64                           CommandStatus;
++  UINT64                           Timming;
++  EINJ_TRIGGER_ERROR_ACTION        *TriggerErrorActionTablePtr;
++  EINJ_SET_ERROR_TYPE_WITH_ADDRESS ErrorTypeWithAddress;
++  EINJ_VENDOR_ERROR_TYPE           VendorErrorTypeExtension;
++  EINJ_TRIGGER_ERROR_ACTION        TriggerErrorActionTable;
++} EINJ_DATA_STRUCTURE;
++
++// V2
++typedef struct _EINJ_CONTEXT {
++  EINJ_TABLE                                    *EINJ;
++  EINJ_DATA_STRUCTURE                           *EinjData;
++  EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY *GetErrorTypeEntry;
++  EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY *ExecuteOperationEntry;
++} EINJ_CONTEXT;
++
++
++EFI_STATUS
++InitEinjTable(VOID);
++// Version2
++EFI_STATUS
++EinjConfigErrorInjectCapability(
++  EINJ_CONTEXT  *Context,
++  UINT32        BitsSupportedErrorType
++);
++EFI_STATUS
++EinjHeaderCreator(
++  EINJ_CONTEXT  *Context
++);
++/***OEM***/
++EFI_STATUS
++OemInitEinjTable(VOID);
++EFI_STATUS
++OemEinjConfigExecuteOperationEntry(
++  EINJ_CONTEXT *Context
++);
++VOID
++EinjSetAcpiTable(
++  EINJ_CONTEXT *Context
++);
++
++
++#endif    // _EINJ_H_
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h
+new file mode 100644
+index 0000000000..44cd1f9577
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.h
+@@ -0,0 +1,110 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#ifndef GENERIC_HARDWARE_ERROR_SOURCE
++#define GENERIC_HARDWARE_ERROR_SOURCE
++#include "Apei.h"
++
++
++typedef struct {
++  UINT64 AckRegister;
++  UINT64 ErrorStatusBlockAddress;
++} GHES_REGISTER;
++
++typedef enum {
++  PROCESSOR_GENERIC   = 0,
++  PROCESSOR_IA32_X64  = 1,
++  PROCESSOR_IPF       = 2,
++  PROCESSOR_ARM       = 3,
++  PLATFORM_MEMORY     = 4,
++  PLATFORM_MEMORY2    = 5,
++  PCIE_EXPRESS        = 6,
++  FIRMWARE_ERROR      = 7,
++  PCI_BUS             = 8,
++  PCI_COMPONENT       = 9
++} EFI_CPER_SECTION_TYPE;
++typedef enum {
++  RECOVERABLE = 0,
++  FATAL = 1,
++  CORRECTED = 2,
++  NONE = 3
++} ERROR_SEVERITY;
++
++EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE*
++ErrorBlockInitial(
++  VOID   *Block,
++  UINT32 Severity
++);
++BOOLEAN ErrorBlockAddErrorData (
++  IN VOID                  *ErrorBlock,
++  IN UINT32                MaxBlockLength,
++  IN EFI_CPER_SECTION_TYPE TypeOfErrorData,
++  IN VOID                  *GenericErrorData,
++  IN UINT32                SizeOfGenericErrorData,
++  IN ERROR_SEVERITY        ErrorSeverity,
++  IN BOOLEAN               Correctable
++);
++BOOLEAN ErrorBlockAddErrorData (
++  IN VOID                  *ErrorBlock,
++  IN UINT32                MaxBlockLength,
++  IN EFI_CPER_SECTION_TYPE TypeOfErrorData,
++  IN VOID                  *GenericErrorData,
++  IN UINT32                SizeOfGenericErrorData,
++  IN ERROR_SEVERITY        ErrorSeverity,
++  IN BOOLEAN               Correctable
++);
++
++VOID
++GhesV2Initial (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE  *GhesV2,
++  UINT32                                                          BlockLength
++);
++
++/**
++@param type - one of HARDWARE_ERROR_NOTIFICATION Type, GSIV For ARM,and SCI for X86,
++              Notice: Windows OS hadn't support to GSIV, 20171026
++*/
++VOID
++GhesV2AddNotification (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE  *This,
++  UINT8                                                           Type
++);
++
++
++EFI_STATUS
++GhesV2LinkErrorBlock (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *GhesV2,
++  GHES_REGISTER                                                  *Register,
++  VOID                                                           *ErrorBlock
++);
++VOID
++GhesV1Initial (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *GhesV1,
++  UINT32                                               BlockLength
++);
++VOID
++GhesV1AddNotification (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *This,
++  UINT8                                                Type
++);
++EFI_STATUS
++GhesV1LinkErrorBlock (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *This,
++  UINT64                                               *ptrBlockAddress,
++  VOID                                                 *ErrorBlock
++);
++
++
++#endif
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.h
+new file mode 100644
+index 0000000000..ca43c83fa0
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.h
+@@ -0,0 +1,146 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#ifndef _ERST_H_
++#define _ERST_H_
++
++#include "Apei.h"
++
++#define ERST_STATUS_SUCCESS                 EFI_ACPI_6_1_ERST_STATUS_SUCCESS
++#define ERST_STATUS_NOT_ENOUGH_SPACE        EFI_ACPI_6_1_ERST_STATUS_NOT_ENOUGH_SPACE
++#define ERST_STATUS_HARDWARE_NOT_AVAILABLE  EFI_ACPI_6_1_ERST_STATUS_HARDWARE_NOT_AVAILABLE
++#define ERST_STATUS_FAILED                  EFI_ACPI_6_1_ERST_STATUS_FAILED
++#define ERST_STATUS_RECORD_STORE_EMPTY      EFI_ACPI_6_1_ERST_STATUS_RECORD_STORE_EMPTY
++#define ERST_STATUS_RECORD_NOT_FOUND        EFI_ACPI_6_1_ERST_STATUS_RECORD_NOT_FOUND
++
++#define ERST_BEGIN_WRITE_VALUE              0x01
++#define ERST_BEGIN_WRITE_MASK               0xFFFFFFFFFFFFFFFF
++#define ERST_BEGIN_READ_VALUE               0x02
++#define ERST_BEGIN_READ_MASK                0xFFFFFFFFFFFFFFFF
++#define ERST_BEGIN_CLEAR_VALUE              0x03
++#define ERST_BEGIN_CLEAR_MASK               0xFFFFFFFFFFFFFFFF
++#define ERST_END_OPERATION_VALUE            0x04
++#define ERST_END_OPERATION_MASK             0xFFFFFFFFFFFFFFFF
++#define ERST_MASK                           0xFFFFFFFFFFFFFFFF
++
++#define ERST_BEGIN_WRITE_OPERATION          EFI_ACPI_6_1_ERST_BEGIN_WRITE_OPERATION
++#define ERST_BEGIN_READ_OPERATION           EFI_ACPI_6_1_ERST_BEGIN_READ_OPERATION
++#define ERST_BEGIN_CLEAR_OPERATION          EFI_ACPI_6_1_ERST_BEGIN_CLEAR_OPERATION
++#define ERST_END_OPERATION                  EFI_ACPI_6_1_ERST_END_OPERATION
++#define ERST_BEGIN_DUMMY_WRITE_OPERATION    EFI_ACPI_6_1_ERST_BEGIN_DUMMY_WRITE_OPERATION
++
++#define ERST_ACTION_NO                      16
++
++#define ERST_RECORD_FREE                    0x00
++#define ERST_RECORD_INUSE                   0x01
++
++#define ERST_RECORD_STORE_IN_NVRAM          0
++#define ERST_RECORD_STORE_IN_MEM            1
++#define ERST_RECORD_STORE_IN_SPI_FLASH      2
++
++#define ERST_LOG_ATTR_NVRAM                 0x02
++
++typedef struct {
++  UINT64 OperationId;
++  UINT64 RecordOffset;
++  UINT64 BusyStatus;
++  UINT64 CommandStatus;
++  UINT64 GetRecordId;
++  UINT64 SetRecordId;
++  UINT64 RecordCount;
++  UINT64 DummyWrite;
++  UINT64 Reserved;
++  UINT64 ErrorLogAddrRange;
++  UINT64 ErrorLogAddrRangeLength;
++  UINT64 ErrorLogAttributes;
++  UINT64 NvRamLogAddrNext;
++  UINT64 NvRamLogSizeRemain;
++} ERST_DATA_STRUCTURE;
++
++typedef struct {
++  UINT16 Signature;
++  UINT16 Data0;
++  UINT16 Data1;
++  UINT8  Data2;
++  UINT8  Attributes; //0: free
++} ERST_ERROR_RECORD_INFO;
++
++///
++/// ERST Table
++///
++
++
++
++typedef struct _ERST_CONTEXT {
++  UINT64 Operation;                  // WRITE,READ,CLEAR,END,
++  UINT64 DummyWrite;                 //DUMMY_WRITE_OPEATION
++  UINT64 RecordOffset;               // Offset form the buffer(error log  adress range)
++  UINT32 BusyStatus;
++  UINT32 CommandStatus;
++  UINT64 KeyRecordId;                //OS Set the Record ID To Read/Write/Search
++  UINT64 MaxTimeOfExecuteOperation;
++  UINT64 RecordCount;                // Num of Record In NVRAM
++  UINT64 ErrorLogAddressRange;       // Address Of Range Top
++  UINT64 ErrorLogAddressRangeLength; // Address Of Range Top
++  UINT64 ErrorLogAttributes;
++  VOID   *NvRamLogAddrRange;
++  UINT64 NvRamLogAddrRangeLength;
++  UINT64 NvRamRecordOffset;
++  UINT64 NvRamNextVallidRecordId;    //Get RecordId entry
++  UINT64 NvRamNextValidRecordOffset;
++  UINT64 NvRamAllRecordLength;
++} ERST_RT_CONTEXT;
++
++typedef struct _ERST_BOOT_CONTEXT {
++  EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER *ErstHeader;
++  EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY    *ExecuteOperationEntry;
++  EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY    *GetErrorLogAddrRangeAttributes;
++  ERST_RT_CONTEXT                                      *Rt;
++} ERST_BOOT_CONTEXT;
++
++extern EFI_ACPI_TABLE_PROTOCOL              *mAcpiTableProtocol;
++extern APEI_TRUSTED_FIRMWARE_STRUCTURE      *mApeiTrustedfirmwareData;
++
++EFI_STATUS
++ErstHeaderCreator(
++  ERST_BOOT_CONTEXT  *Context,
++  UINT64             BufferSize,//ERST_DATASTORE_SIZE
++  VOID               *NvRamAddrRange,
++  UINT64             NvRamAllRecordLength,
++  UINT64             NvRamAddrRangeLength
++);
++
++VOID
++SetAttributeOfErrorLogAddressRange (
++  ERST_BOOT_CONTEXT  *Context,
++  UINT64             Attribute
++);
++
++/***OEM***/
++EFI_STATUS
++OemInitErstTable (VOID);
++
++EFI_STATUS
++OemErstConfigExecuteOperationEntry (
++  ERST_BOOT_CONTEXT *Context
++);
++
++VOID
++ErstSetAcpiTable (
++  ERST_BOOT_CONTEXT *Context
++);
++
++
++#endif    // _ERST_H_
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.h
+new file mode 100644
+index 0000000000..94f66496e6
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.h
+@@ -0,0 +1,59 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#ifndef _HEST_H_
++#define _HEST_H_
++
++#include "Apei.h"
++
++
++typedef struct _HEST_CONTEXT {
++  EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER  *HestHeader;         // pointer to hest header
++  UINT32                                           OccupiedMemorySize; // allocated memory size for hest
++  VOID                                             *KeyErrorSource;     // key error source, valtile
++} HEST_CONTEXT;
++
++EFI_STATUS
++HestAddErrorSourceDescriptor (
++  IN OUT HEST_CONTEXT  *Context,
++  IN VOID              *ErrorSourceDescriptor,
++  IN UINT32            SizeOfDescriptor
++);
++VOID
++HestSetAcpiTable (
++  IN HEST_CONTEXT *Context
++);
++EFI_STATUS
++HestHeaderCreator (
++  HEST_CONTEXT  *Context,
++  UINT32        PreAllocatedHestSize
++);
++
++/**
++* OEM Interface declaration
++* 1.Interface is not realized default
++* 2.OEM should implement this interface
++*/
++extern
++VOID
++OemHestInitialNotification (VOID);
++
++extern
++EFI_STATUS
++OemInitHestTable(
++  IN EFI_HANDLE ImageHandle
++);
++
++#endif    // _HEST_H_
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h b/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h
+new file mode 100644
+index 0000000000..e6fb386a62
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.h
+@@ -0,0 +1,43 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#ifndef OEM_APEI_HI1620_H_H
++#define OEM_APEI_HI1620_H_H
++#define GPIO0_BASE             0x94100000
++#define GPIO1_BASE             0x94110000
++#define GPIO_INT_MASK          0x34
++#define GPIO_INT_EN            0x30
++#define GPIO_SWPORT_DDR        0x04
++#define GPIO_INT_TYPE          0x38
++#define GPIO_INT_POLARITY      0x3c
++#define GPIO_LS_SYNC           0x60
++#define GPIO_INT_COMB          0xffc
++#define IOMUX_REG_BASE         0x94190000
++#define IOMG051                0xCC
++#define IOMG052                0xD0
++#define PAD_EX_INT1            0x4
++#define CPLD_GPIO10_INT_OFFSET 0xfc
++#define CPLD_BASE_ADDR         0x80000000
++#define CPLD_MASK              0x01030000
++#define CPLD_VALUE             0x01020000
++
++#define MAX_GHES                          3
++#define GENERIC_HARDWARE_ERROR_BLOCK_SIZE 0x1000
++#define HEST_TABLE_SIZE                   0x2000
++#define BOOT_ERROR_REGION_SIZE            0x1000
++#define GPIO_HEST_NOTIFIED_PIN            BIT8
++
++#define ERST_DATASTORE_SIZE               0x2000
++#endif
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c
+new file mode 100644
+index 0000000000..8769d88bff
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Apei.c
+@@ -0,0 +1,108 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++#include <Library/ArmSmcLib.h>
++#include <Library/BaseMemoryLib.h>
++#include <Library/DebugLib.h>
++#include <Library/IoLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include <Library/OemConfigData.h>
++#include <Library/UefiBootServicesTableLib.h>
++#include <Library/UefiLib.h>
++#include <Library/UefiRuntimeServicesTableLib.h>
++#include "Apei.h"
++#include "PlatformArch.h"
++#include "bert.h"
++#include "einj.h"
++#include "erst.h"
++#include "hest.h"
++
++EFI_ACPI_TABLE_PROTOCOL        *mAcpiTableProtocol = NULL;
++EFI_ACPI_SDT_PROTOCOL          *mAcpiSdtProtocol = NULL;
++APEI_TRUSTED_FIRMWARE_STRUCTURE      *mApeiTrustedfirmwareData;
++
++EFI_STATUS
++EFIAPI
++ApeiEntryPoint (
++  IN EFI_HANDLE          ImageHandle,
++  IN EFI_SYSTEM_TABLE    *SystemTable
++)
++{
++  EFI_STATUS              Status;
++  ARM_SMC_ARGS            SmcRegs = {0};
++  UINTN                   Size = sizeof (OEM_CONFIG_DATA);
++  OEM_CONFIG_DATA         SetupData;
++
++  Status = gRT->GetVariable (
++             OEM_CONFIG_NAME,
++             &gOemConfigGuid,
++             NULL,
++             &Size,
++             &SetupData
++             );
++  if (EFI_ERROR (Status)) {
++    SetupData.EnRasSupport = 1;
++    DEBUG ((DEBUG_ERROR, "[%a]GetVariable %r.Get default variable value\n",
++      __FUNCTION__, Status));
++  }
++  if (!SetupData.EnRasSupport) {
++    return EFI_ABORTED;
++  }
++  if (PcdGet64 (PcdTrustedFirmwareEnable) == 0) {
++    return EFI_ABORTED;
++  }
++  Status = gBS->LocateProtocol (
++                  &gEfiAcpiTableProtocolGuid,
++                  NULL,
++                  (VOID**)&mAcpiTableProtocol);
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  Status = gBS->LocateProtocol (
++                &gEfiAcpiSdtProtocolGuid,
++                NULL,
++                (VOID**)&mAcpiSdtProtocol);
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  Status = gBS->AllocatePool (
++             EfiReservedMemoryType,
++             sizeof (APEI_TRUSTED_FIRMWARE_STRUCTURE),
++             (VOID**)&mApeiTrustedfirmwareData
++           );
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  gBS->SetMem (
++    mApeiTrustedfirmwareData,
++    sizeof (APEI_TRUSTED_FIRMWARE_STRUCTURE),
++    0
++  );
++  Status = EFI_SUCCESS;
++  Status |= OemInitBertTable (ImageHandle);
++  Status |= OemInitHestTable (ImageHandle);
++  Status |= OemInitErstTable ();
++  Status |= OemInitEinjTable ();
++  // smc call
++  DEBUG ((DEBUG_INFO, "[%a]:[%dL]: %r\n", __FUNCTION__, __LINE__, Status));
++  if (Status == EFI_SUCCESS) {
++    SmcRegs.Arg0 = PRIVATE_ARM_SMC_ID_APEI;
++    SmcRegs.Arg1 = (UINTN)mApeiTrustedfirmwareData;
++    ArmCallSmc (&SmcRegs);
++  }
++  DEBUG ((DEBUG_INFO, "Acpi Apei init done.\n"));
++  return EFI_SUCCESS;
++}
++
++
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.c
+new file mode 100644
+index 0000000000..2953e22690
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Bert/bert.c
+@@ -0,0 +1,92 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include "bert.h"
++#include "ErrorSource/Ghes.h"
++#include <Library/BaseLib.h>
++#include <Library/BaseMemoryLib.h>
++#include <Library/DebugLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include "PlatformArch.h"
++
++VOID
++BertSetAcpiTable (
++  IN BERT_CONTEXT *Context
++)
++{
++  UINTN          AcpiTableHandle;
++  EFI_STATUS     Status;
++  if (Context == NULL) {
++    return;
++  }
++  EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER* Bert = Context->BertHeader;
++  Bert->Header.Checksum = CalculateCheckSum8 ((UINT8*)(Bert), Bert->Header.Length);
++  AcpiTableHandle = 0;
++  Status = mAcpiTableProtocol->InstallAcpiTable (
++                                 mAcpiTableProtocol,
++                                 Bert,
++                                 Bert->Header.Length,
++                                 &AcpiTableHandle);
++  ASSERT_EFI_ERROR (Status);
++  return;
++}
++
++BOOLEAN
++BertAddGenericErrorData (
++  IN EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER *Bert,
++  IN EFI_CPER_SECTION_TYPE                       TypeOfErrorData,
++  IN VOID                                        *GenericErrorData,
++  IN UINT32                                      SizeOfGenericErrorData,
++  IN ERROR_SEVERITY                              ErrorSeverity,
++  IN BOOLEAN                                     Correctable
++)
++{
++  DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: \n", __FUNCTION__, __LINE__));
++  BOOLEAN Status = ErrorBlockAddErrorData (
++                     (VOID*)Bert->BootErrorRegion,
++                     Bert->BootErrorRegionLength,
++                     TypeOfErrorData,
++                     GenericErrorData,
++                     SizeOfGenericErrorData,
++                     ErrorSeverity,
++                     Correctable);
++  return Status;
++}
++
++EFI_STATUS
++BertHeaderCreator (
++  IN BERT_CONTEXT  *Context,
++  IN UINT32        ErrorBlockSize
++)
++{
++  if (Context == NULL) {
++    return EFI_INVALID_PARAMETER;
++  }
++  Context->BertHeader = AllocateZeroPool (sizeof (EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER));
++  Context->Block = AllocateReservedZeroPool (ErrorBlockSize);
++  Context->BlockSize = ErrorBlockSize;
++  *Context->BertHeader = (EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER) {
++    ARM_ACPI_HEADER (
++      EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_SIGNATURE,
++      EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_HEADER,
++      EFI_ACPI_6_0_BOOT_ERROR_RECORD_TABLE_REVISION
++      ),
++    Context->BlockSize,
++    (UINT64)Context->Block
++  };
++  return EFI_SUCCESS;
++}
++
++
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.c
+new file mode 100644
+index 0000000000..c53f4cdb3c
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Einj/einj.c
+@@ -0,0 +1,349 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++#include "einj.h"
++#include <IndustryStandard/Acpi62.h>
++#include <Library/BaseLib.h>
++#include <Library/DebugLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include <Library/UefiBootServicesTableLib.h>
++#include "OemApeiHi1620.h"
++#include "PlatformArch.h"
++
++
++EINJ_TABLE mEinj = {
++  {
++    ARM_ACPI_HEADER (
++      EFI_ACPI_6_0_ERROR_INJECTION_TABLE_SIGNATURE,
++      EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER,
++      EFI_ACPI_6_0_ERROR_INJECTION_TABLE_REVISION
++    ),
++    sizeof (EFI_ACPI_6_0_ERROR_INJECTION_TABLE_HEADER),
++    0x0,
++    {
++      0x0,
++      0x0,
++      0x0
++    },
++    EINJ_ACTION_NO
++  },
++  {
++    {
++      // 0 EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION
++      EFI_ACPI_6_0_EINJ_BEGIN_INJECTION_OPERATION,
++      EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE,
++      EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      EINJ_BEGIN_OPERATION_VALUE,
++      EINJ_WRITE_MASK
++    },
++    {
++      // 1 EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE
++      EFI_ACPI_6_0_EINJ_GET_TRIGGER_ERROR_ACTION_TABLE,
++      EFI_ACPI_6_0_EINJ_READ_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      EINJ_READ_MASK
++    },
++    {
++      // 2 EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE
++      EFI_ACPI_6_0_EINJ_SET_ERROR_TYPE,
++      EFI_ACPI_6_0_EINJ_WRITE_REGISTER,
++      EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      EINJ_WRITE_MASK
++    },
++    {
++      // 3 EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE
++      EFI_ACPI_6_0_EINJ_GET_ERROR_TYPE,
++      EFI_ACPI_6_0_EINJ_READ_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      0xFFFFFFFF
++    },
++    {
++      // 4 EFI_ACPI_6_0_EINJ_END_OPERATION
++      EFI_ACPI_6_0_EINJ_END_OPERATION,
++      EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE,
++      EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      EINJ_END_OPERATION_VALUE,
++      0xFFFFFFFF
++    },
++    {
++      // 5 EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION
++      EFI_ACPI_6_0_EINJ_EXECUTE_OPERATION,
++      EFI_ACPI_6_0_EINJ_WRITE_REGISTER_VALUE,
++      EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        32,
++        0,
++        EFI_ACPI_6_0_DWORD,
++        GPIO1_BASE + GPIO_INT_MASK //0x40070008//0x4d000F00//GPIO0_BASE + GPIO0_SWPORT_DR_OFFSET
++      },
++      0,
++      0xFFFFFFFF //BIT0
++    },
++    {
++      // 6 EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS
++      EFI_ACPI_6_0_EINJ_CHECK_BUSY_STATUS,
++      EFI_ACPI_6_0_EINJ_READ_REGISTER_VALUE,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0x01,
++      0x01
++    },
++    {
++      // 7 EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS
++      EFI_ACPI_6_0_EINJ_GET_COMMAND_STATUS,
++      EFI_ACPI_6_0_EINJ_READ_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      0x3
++    },
++    {
++      // 8 EFI_ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS
++      EFI_ACPI_EINJ_SET_ERROR_TYPE_WITH_ADDRESS,
++      EFI_ACPI_6_0_EINJ_WRITE_REGISTER,
++      EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      0xFFFFFF
++    },
++    {
++      // 9 EFI_ACPI_EINJ_GET_EXCUTE_OPERATION_TIMINGS
++      EFI_ACPI_EINJ_GET_EXCUTE_OPERATION_TIMINGS,
++      EFI_ACPI_6_0_EINJ_WRITE_REGISTER,
++      EFI_ACPI_6_0_EINJ_PRESERVE_REGISTER,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      0xFFFFFF
++    }
++  }
++};
++
++EINJ_TRIGGER_ERROR_ACTION mEinjTriggerErrorAction = {
++  {
++    sizeof (EFI_ACPI_6_0_EINJ_TRIGGER_ACTION_TABLE),
++    0,
++    sizeof (EINJ_TRIGGER_ERROR_ACTION),
++    EINJ_TRIGGER_ERROR_ACTION_NO
++  },
++  {
++    {
++      EFI_ACPI_6_0_EINJ_TRIGGER_ERROR,
++      EFI_ACPI_6_0_EINJ_NOOP,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_DWORD,
++        0
++      },
++      0,
++      0
++    }
++  }
++};
++
++
++VOID
++EinjSetAcpiTable (
++  EINJ_CONTEXT *Context
++)
++{
++  UINTN                   AcpiTableHandle;
++  EFI_STATUS              Status;
++  UINT8                   Checksum;
++  EFI_ACPI_SDT_HEADER     *Table;
++  EFI_ACPI_TABLE_VERSION  TableVersion;
++  UINTN                   TableKey;
++  UINTN                   i;
++
++  Context->EINJ->EinjTableHeader.Header.Length = sizeof (EINJ_TABLE);
++  Checksum = CalculateCheckSum8 (
++               (UINT8*)(Context->EINJ),
++               Context->EINJ->EinjTableHeader.Header.Length);
++  Context->EINJ->EinjTableHeader.Header.Checksum = Checksum;
++  AcpiTableHandle = 0;
++  Status = mAcpiTableProtocol->InstallAcpiTable (
++             mAcpiTableProtocol,
++             Context->EINJ,
++             Context->EINJ->EinjTableHeader.Header.Length,
++             &AcpiTableHandle
++           );
++  for (i = 0; i < EFI_ACPI_MAX_NUM_TABLES; i++) {
++    Status = mAcpiSdtProtocol->GetAcpiTable (i, &Table, &TableVersion, &TableKey);
++    if (EFI_ERROR (Status)) {
++      break;
++    }
++    if (Table->Signature != EFI_ACPI_6_0_ERROR_INJECTION_TABLE_SIGNATURE) {
++      continue;
++    }
++    mApeiTrustedfirmwareData->EinjTableAddress = (EFI_PHYSICAL_ADDRESS)Table;
++    mApeiTrustedfirmwareData->EinjDataStruct = (EFI_PHYSICAL_ADDRESS)Context->EinjData;
++  }
++  ASSERT_EFI_ERROR (Status) ;
++}
++//V2
++EFI_STATUS
++EinjHeaderCreator (
++  EINJ_CONTEXT *Context
++)
++{
++  EFI_STATUS           Status;
++  EINJ_DATA_STRUCTURE  *EinjData = NULL;
++  Status = gBS->AllocatePool (
++             EfiReservedMemoryType,
++             sizeof (EINJ_DATA_STRUCTURE),
++             (VOID**)&EinjData
++           );
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  gBS->SetMem (
++    EinjData,
++    sizeof (EINJ_DATA_STRUCTURE),
++    0
++  );
++
++  DEBUG ((DEBUG_INFO, "EINJ EinjData is at 0x%X,size =0x%x\n",
++          EinjData, sizeof (EINJ_DATA_STRUCTURE)));
++  EinjData->TriggerErrorActionTablePtr =
++    (EINJ_TRIGGER_ERROR_ACTION*)(&(EinjData->TriggerErrorActionTable));
++  gBS->CopyMem (
++         EinjData->TriggerErrorActionTablePtr,
++         &mEinjTriggerErrorAction,
++         sizeof (EINJ_TRIGGER_ERROR_ACTION));
++  EinjData->OperationBegin = 0;
++  EinjData->ErrorType = 0;
++  EinjData->ErrorCapabilities = 0xFFF;
++  EinjData->BusyStatus = 0;
++  EinjData->CommandStatus = 0;
++  mEinj.EinjInstructionEntry[0].RegisterRegion.Address =
++    (UINT64)(&(EinjData->OperationBegin));
++  mEinj.EinjInstructionEntry[1].RegisterRegion.Address =
++    (UINT64)(&(EinjData->TriggerErrorActionTablePtr));
++  mEinj.EinjInstructionEntry[2].RegisterRegion.Address =
++    (UINT64)(&(EinjData->ErrorType));
++  mEinj.EinjInstructionEntry[3].RegisterRegion.Address =
++    (UINT64)(&(EinjData->ErrorCapabilities));
++  mEinj.EinjInstructionEntry[4].RegisterRegion.Address =
++    (UINT64)(&(EinjData->OperationBegin));
++  mEinj.EinjInstructionEntry[6].RegisterRegion.Address =
++    (UINT64)(&(EinjData->BusyStatus));
++  mEinj.EinjInstructionEntry[7].RegisterRegion.Address =
++    (UINT64)(&(EinjData->CommandStatus));
++  mEinj.EinjInstructionEntry[8].RegisterRegion.Address =
++    (UINT64)(&(EinjData->ErrorTypeWithAddress));
++  mEinj.EinjInstructionEntry[9].RegisterRegion.Address =
++    (UINT64)(&(EinjData->Timming));
++  EinjData->ErrorTypeWithAddress.VendorErrorTypeOffset =
++    (UINT32)((UINTN)&(EinjData->VendorErrorTypeExtension) -
++    (UINTN)&(EinjData->ErrorTypeWithAddress));
++  Context->EinjData = EinjData;
++  Context->EINJ = &mEinj;
++  Context->ExecuteOperationEntry = &mEinj.EinjInstructionEntry[5];
++  Context->GetErrorTypeEntry = &mEinj.EinjInstructionEntry[3];
++  return EFI_SUCCESS;
++}
++
++
++EFI_STATUS
++EinjConfigErrorInjectCapability (
++  EINJ_CONTEXT* Context,
++  UINT32        BitsSupportedErrorType
++)
++{
++  EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY* KeyEntry;
++  UINT32*                                        EinjCapablity;
++
++  KeyEntry = Context->GetErrorTypeEntry;
++  EinjCapablity = (UINT32*)KeyEntry->RegisterRegion.Address;
++  *EinjCapablity = BitsSupportedErrorType;
++  KeyEntry->Value = BitsSupportedErrorType;
++  return EFI_SUCCESS;
++}
++
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c
+new file mode 100644
+index 0000000000..6d69b90e9b
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/ErrorSource/Ghes.c
+@@ -0,0 +1,330 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include <Guid/Cper.h>
++#include "Ghes.h"
++#include <Library/DebugLib.h>
++#include <Library/UefiBootServicesTableLib.h>
++
++#define READ_ACK_PRESERVE 0xFFFFFFFE
++#define READ_ACK_WRITE 0x1
++
++EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE*
++ErrorBlockInitial (
++  VOID   *Block,
++  UINT32 Severity
++)
++{
++  EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE* BlockHeader = Block;
++  BlockHeader->BlockStatus = (EFI_ACPI_6_1_ERROR_BLOCK_STATUS) {0, 0, 0, 0, 0};
++  BlockHeader->RawDataOffset = 0;
++  BlockHeader->RawDataLength = 0;
++  BlockHeader->DataLength = 0;
++  BlockHeader->ErrorSeverity = Severity;
++  return BlockHeader;
++}
++
++
++BOOLEAN
++ErrorBlockUpdateStatusStructure (
++  VOID *ErrorBlock
++)
++{
++  if (ErrorBlock == NULL) {
++    return FALSE;
++  }
++  IN EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE *BlockHeader =  ErrorBlock;
++  VOID *EntriesBegin = ErrorBlock + sizeof (EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE);
++  if (BlockHeader->BlockStatus.ErrorDataEntryCount == 0) {
++    gBS->SetMem (EntriesBegin, BlockHeader->DataLength, 0);
++    BlockHeader->RawDataLength = 0;
++    BlockHeader->RawDataOffset = 0;
++    BlockHeader->DataLength = 0;
++  }
++  return TRUE;
++}
++
++
++BOOLEAN
++ErrorBlockAddErrorData (
++  IN VOID                  *ErrorBlock,
++  IN UINT32                MaxBlockLength,
++  IN EFI_CPER_SECTION_TYPE TypeOfErrorData,
++  IN VOID                  *GenericErrorData,
++  IN UINT32                SizeOfGenericErrorData,
++  IN ERROR_SEVERITY        ErrorSeverity,
++  IN BOOLEAN               Correctable
++)
++{
++  if (ErrorBlock == NULL || GenericErrorData == NULL) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL]Invalid Param \n", __FUNCTION__, __LINE__));
++    return FALSE;
++  }
++  EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE*  Entry;
++  EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE* BlockHeader = ErrorBlock;
++  EFI_ACPI_6_1_ERROR_BLOCK_STATUS* BlockStatus = &BlockHeader->BlockStatus;
++  (VOID)ErrorBlockUpdateStatusStructure (ErrorBlock);
++  UINT32 ExpectedNewDataLength = BlockHeader->DataLength +
++           sizeof (EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE) +
++           SizeOfGenericErrorData;
++  if (sizeof (EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE) + ExpectedNewDataLength >
++      MaxBlockLength) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL]Out of BlockSize \n", __FUNCTION__, __LINE__));
++    return FALSE;
++  }
++  // guid
++  EFI_GUID Guid;
++  switch (TypeOfErrorData) {
++    case PROCESSOR_GENERIC:
++      Guid = (EFI_GUID)EFI_ERROR_SECTION_PROCESSOR_GENERIC_GUID;
++      break;
++    case PROCESSOR_ARM:
++      Guid = (EFI_GUID)EFI_ERROR_SECTION_PROCESSOR_SPECIFIC_ARM_GUID;
++      break;
++    case PLATFORM_MEMORY:
++      Guid = (EFI_GUID)EFI_ERROR_SECTION_PLATFORM_MEMORY_GUID;
++      break;
++    case PLATFORM_MEMORY2:
++      Guid = (EFI_GUID)EFI_ERROR_SECTION_PLATFORM_MEMORY2_GUID;
++      break;
++    case PCIE_EXPRESS:
++      Guid = (EFI_GUID)EFI_ERROR_SECTION_PCIE_GUID;
++      break;
++    case FIRMWARE_ERROR:
++      Guid = (EFI_GUID)EFI_ERROR_SECTION_FW_ERROR_RECORD_GUID;
++      break;
++    case PCI_BUS:
++      Guid = (EFI_GUID)EFI_ERROR_SECTION_PCI_PCIX_BUS_GUID;
++      break;
++    case PCI_COMPONENT:
++      Guid = (EFI_GUID)EFI_ERROR_SECTION_PCI_DEVICE_GUID;
++      break;
++    default:
++      return FALSE;
++  }
++  //Block Status
++  if (Correctable == TRUE) {
++    if (BlockStatus->CorrectableErrorValid == 0) {
++      BlockStatus->CorrectableErrorValid = 1;
++    } else {
++      BlockStatus->MultipleCorrectableErrors = 1;
++    }
++  } else {
++    if (BlockStatus->UncorrectableErrorValid == 0) {
++      BlockStatus->UncorrectableErrorValid = 1;
++    } else {
++      BlockStatus->MultipleUncorrectableErrors = 1;
++    }
++  }
++  BlockStatus->ErrorDataEntryCount++;
++  // Entry
++  Entry = (EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE*)(ErrorBlock +
++           sizeof (EFI_ACPI_6_1_GENERIC_ERROR_STATUS_STRUCTURE) +
++           BlockHeader->DataLength);
++  gBS->SetMem (Entry, sizeof (EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE), 0);
++  gBS->CopyMem (&Entry->SectionType, &Guid, sizeof (EFI_GUID));
++  Entry->ErrorSeverity = ErrorSeverity;
++  Entry->Revision = EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_REVISION;
++  Entry->ErrorDataLength = SizeOfGenericErrorData;
++  VOID*  GenericErrorDataFollowEntry = (VOID*)Entry +
++           sizeof (EFI_ACPI_6_1_GENERIC_ERROR_DATA_ENTRY_STRUCTURE);
++  gBS->CopyMem (
++         GenericErrorDataFollowEntry,
++         GenericErrorData,
++         SizeOfGenericErrorData);
++  // BlockHeader
++  BlockHeader->RawDataOffset = 0;
++  BlockHeader->RawDataLength = 0;
++  BlockHeader->DataLength = ExpectedNewDataLength;
++  return TRUE;
++}
++
++VOID
++GhesV2Initial (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *GhesV2,
++  UINT32                                                         BlockLength
++)
++{
++  if (GhesV2 == NULL) {
++    return;
++  }
++  *GhesV2 = (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE) {
++    .Type = EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_VERSION_2,
++    .SourceId = 0,
++    .RelatedSourceId = 0xFFFF,
++    .Flags = 0,
++    .Enabled = 1,
++    .NumberOfRecordsToPreAllocate = 1,//ERROR BLOCK
++    .MaxSectionsPerRecord = 1,// Num Entries(section)
++    .MaxRawDataLength = BlockLength, // Max Size Of a Raw Data
++    .ErrorStatusAddress = {
++      .AddressSpaceId = EFI_ACPI_6_1_SYSTEM_MEMORY,
++      .RegisterBitWidth = 64,
++      .RegisterBitOffset = 0,
++      .AccessSize = EFI_ACPI_6_1_QWORD,
++      .Address = 0
++    },
++    .NotificationStructure = {
++      .Type = EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV,
++      .Length = sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE),
++      .ConfigurationWriteEnable = {0, 0, 0, 0, 0, 0, 0} ,
++      .PollInterval = 0,
++      .Vector = 0,
++      .SwitchToPollingThresholdValue = 0,
++      .SwitchToPollingThresholdWindow = 0,
++      .ErrorThresholdValue = 0,
++      .ErrorThresholdWindow = 0
++    },
++    .ErrorStatusBlockLength = BlockLength,
++    .ReadAckRegister = {
++      .AddressSpaceId = EFI_ACPI_6_1_SYSTEM_MEMORY,
++      .RegisterBitWidth = 64,
++      .RegisterBitOffset = 0,
++      .AccessSize = EFI_ACPI_6_1_QWORD,
++      .Address = 0
++    },
++    .ReadAckPreserve = READ_ACK_PRESERVE,
++    .ReadAckWrite = READ_ACK_WRITE
++  };
++  return;
++}
++
++VOID
++GhesV2AddNotification (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE  *This,
++  UINT8                                                           Type
++)
++{
++  This->NotificationStructure = (EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE) {
++    .Type = Type,
++    .Length = sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE),
++    .ConfigurationWriteEnable = {
++      .Type = 0,
++      .PollInterval = 1,
++      .SwitchToPollingThresholdValue = 1,
++      .SwitchToPollingThresholdWindow = 1,
++      .ErrorThresholdValue = 1,
++      .ErrorThresholdWindow = 1
++    },
++    .PollInterval = 20,
++    .Vector = 0,
++    .SwitchToPollingThresholdValue = 0,
++    .SwitchToPollingThresholdWindow = 0,
++    .ErrorThresholdValue = 0,
++    .ErrorThresholdWindow = 0
++  };
++  return;
++}
++
++EFI_STATUS
++GhesV2LinkErrorBlock (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE *GhesV2,
++  GHES_REGISTER                                                  *Register,
++  VOID                                                           *ErrorBlock
++)
++{
++  if (ErrorBlock == NULL || Register == NULL || GhesV2 == NULL) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  Register->ErrorStatusBlockAddress = (UINTN)ErrorBlock;
++  GhesV2->ErrorStatusAddress.Address = (UINTN)&(Register->ErrorStatusBlockAddress);
++  Register->AckRegister = READ_ACK_WRITE;
++  GhesV2->ReadAckRegister.Address = (UINT64)&(Register->AckRegister);
++  return EFI_SUCCESS;
++}
++
++
++VOID GhesV1Initial (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *GhesV1,
++  UINT32 BlockLength
++)
++{
++  if (GhesV1 == NULL) {
++    return;
++  }
++  *GhesV1 = (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE) {
++    .Type = EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR,
++    .SourceId = 0,
++    .RelatedSourceId = 0xFFFF,
++    .Flags = 0,
++    .Enabled = 1,
++    .NumberOfRecordsToPreAllocate = 1,//ERROR BLOCK
++    .MaxSectionsPerRecord = 1,// Num Entries(section)
++    .MaxRawDataLength = BlockLength, // Max Size Of a Raw Data
++    .ErrorStatusAddress = {
++      .AddressSpaceId = EFI_ACPI_6_1_SYSTEM_MEMORY,
++      .RegisterBitWidth = 64,
++      .RegisterBitOffset = 0,
++      .AccessSize = EFI_ACPI_6_1_QWORD,
++      .Address = 0
++    },
++    .NotificationStructure = {
++      .Type = EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV,
++      .Length = sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE),
++      .ConfigurationWriteEnable = {0, 0, 0, 0, 0, 0, 0},
++      .PollInterval = 0,
++      .Vector = 0,
++      .SwitchToPollingThresholdValue = 0,
++      .SwitchToPollingThresholdWindow = 0,
++      .ErrorThresholdValue = 0,
++      .ErrorThresholdWindow = 0
++    },
++    .ErrorStatusBlockLength = BlockLength,
++  };
++  return;
++}
++
++VOID
++GhesV1AddNotification (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *This,
++  UINT8                                                Type
++)
++{
++  This->NotificationStructure = (EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_STRUCTURE) {
++    .Type = Type,
++    .Length = sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE),
++    .ConfigurationWriteEnable = {
++      .Type = 0,
++      .PollInterval = 1,
++      .SwitchToPollingThresholdValue = 1,
++      .SwitchToPollingThresholdWindow = 1,
++      .ErrorThresholdValue = 1,
++      .ErrorThresholdWindow = 1
++    },
++    .PollInterval = 20,
++    .Vector = 0,
++    .SwitchToPollingThresholdValue = 0,
++    .SwitchToPollingThresholdWindow = 0,
++    .ErrorThresholdValue = 0,
++    .ErrorThresholdWindow = 0
++  };
++  return;
++}
++
++EFI_STATUS GhesV1LinkErrorBlock (
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE *This,
++  UINT64                                               *ptrBlockAddress,
++  VOID                                                 *ErrorBlock
++)
++{
++  if (ErrorBlock == NULL || ptrBlockAddress == NULL || This == NULL) {
++    return EFI_INVALID_PARAMETER;
++  }
++  *ptrBlockAddress = (UINTN)ErrorBlock;
++  This->ErrorStatusAddress.Address = (UINTN) ptrBlockAddress;
++  return EFI_SUCCESS;
++}
++
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.c
+new file mode 100644
+index 0000000000..80d7d43c5b
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Erst/erst.c
+@@ -0,0 +1,374 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++#include "erst.h"
++#include <Guid/Cper.h>
++#include <Library/BaseLib.h>
++#include <Library/DebugLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include "PlatformArch.h"
++
++typedef struct {
++  EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER ErstTableHeader;
++  EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY    ErstInstructionEntry[ERST_ACTION_NO];
++} ERST_TABLE;
++
++ERST_TABLE mErst = {
++  {
++    ARM_ACPI_HEADER (
++      EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_SIGNATURE,
++      EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER,
++      EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_REVISION
++    ),
++    sizeof (EFI_ACPI_6_0_ERROR_RECORD_SERIALIZATION_TABLE_HEADER),
++    {
++      0x0,
++      0x0,
++      0x0,
++      0x0
++    },
++    ERST_ACTION_NO,
++  },
++  {
++    {
++      // 0 EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION
++      EFI_ACPI_6_0_ERST_BEGIN_WRITE_OPERATION,
++      EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      ERST_BEGIN_WRITE_VALUE,
++      ERST_BEGIN_WRITE_MASK
++    },
++    {
++      // 1 EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION
++      EFI_ACPI_6_0_ERST_BEGIN_READ_OPERATION,
++      EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      ERST_BEGIN_READ_VALUE,
++      ERST_BEGIN_READ_MASK
++    },
++    {
++      // 2 EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION
++      EFI_ACPI_6_0_ERST_BEGIN_CLEAR_OPERATION,
++      EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      ERST_BEGIN_CLEAR_VALUE,
++      ERST_BEGIN_CLEAR_MASK
++    },
++    {
++      // 3 EFI_ACPI_6_0_ERST_END_OPERATION
++      EFI_ACPI_6_0_ERST_END_OPERATION,
++      EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE,
++      EFI_ACPI_6_0_ERST_PRESERVE_REGISTER,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      ERST_END_OPERATION_VALUE,
++      ERST_END_OPERATION_MASK
++    },
++    {
++      // 4 EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET
++      EFI_ACPI_6_0_ERST_SET_RECORD_OFFSET,
++      EFI_ACPI_6_0_ERST_WRITE_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      ERST_MASK
++    },
++    {
++      // 5 EFI_ACPI_6_0_ERST_EXECUTE_OPERATION
++      EFI_ACPI_6_0_ERST_EXECUTE_OPERATION,
++      EFI_ACPI_6_0_ERST_WRITE_REGISTER_VALUE,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_DWORD,
++        0x94730000
++      },
++      0x0002,
++      0x0002
++    },
++    {
++      // 6 EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS
++      EFI_ACPI_6_0_ERST_CHECK_BUSY_STATUS,
++      EFI_ACPI_6_0_ERST_READ_REGISTER_VALUE,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0x00000001,
++      0x00000001
++    },
++    {
++      // 7 EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS
++      EFI_ACPI_6_0_ERST_GET_COMMAND_STATUS,
++      EFI_ACPI_6_0_ERST_READ_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      ERST_MASK
++    },
++    {
++      // 8 EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER
++      EFI_ACPI_6_0_ERST_GET_RECORD_IDENTIFIER,
++      EFI_ACPI_6_0_ERST_READ_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      ERST_MASK
++    },
++    {
++      // 9 EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER
++      EFI_ACPI_6_0_ERST_SET_RECORD_IDENTIFIER,
++      EFI_ACPI_6_0_ERST_WRITE_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      ERST_MASK
++    },
++    {
++      // A EFI_ACPI_6_0_ERST_GET_RECORD_COUNT
++      EFI_ACPI_6_0_ERST_GET_RECORD_COUNT,
++      EFI_ACPI_6_0_ERST_READ_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      ERST_MASK
++    },
++    {
++      // B EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION
++      EFI_ACPI_6_0_ERST_BEGIN_DUMMY_WRITE_OPERATION,
++      EFI_ACPI_6_0_ERST_WRITE_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      ERST_MASK
++    },
++    {
++      // C RESERVED
++      0x0C,
++      EFI_ACPI_6_0_ERST_WRITE_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      ERST_MASK
++    },
++    {
++      // D EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE
++      EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE,
++      EFI_ACPI_6_0_ERST_READ_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      ERST_MASK
++    },
++    {
++      // E EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH
++      EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_LENGTH,
++      EFI_ACPI_6_0_ERST_READ_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      ERST_MASK
++    },
++    {
++      // F EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES
++      EFI_ACPI_6_0_ERST_GET_ERROR_LOG_ADDRESS_RANGE_ATTRIBUTES,
++      EFI_ACPI_6_0_ERST_READ_REGISTER,
++      0,
++      0,
++      {
++        EFI_ACPI_6_0_SYSTEM_MEMORY,
++        64,
++        0,
++        EFI_ACPI_6_0_QWORD,
++        0
++      },
++      0,
++      ERST_MASK
++    }
++  }
++};
++
++VOID
++ErstSetAcpiTable (
++  ERST_BOOT_CONTEXT *Context
++)
++{
++  UINTN                     AcpiTableHandle;
++  EFI_STATUS                Status;
++  UINT8                     Checksum;
++  mErst.ErstTableHeader.Header.Length = sizeof (ERST_TABLE);
++  Checksum = CalculateCheckSum8 ((UINT8*)(&mErst), mErst.ErstTableHeader.Header.Length);
++  mErst.ErstTableHeader.Header.Checksum = Checksum;
++  AcpiTableHandle = 0;
++  Status = mAcpiTableProtocol->InstallAcpiTable (
++             mAcpiTableProtocol,
++             &mErst,
++             mErst.ErstTableHeader.Header.Length,
++             &AcpiTableHandle
++             );
++  ASSERT_EFI_ERROR (Status) ;
++}
++
++EFI_STATUS
++ErstHeaderCreator (
++  ERST_BOOT_CONTEXT  *Context,
++  UINT64             BufferSize,//ERST_DATASTORE_SIZE
++  VOID               *NvRamAddrRange,
++  UINT64             NvRamAllRecordLength,
++  UINT64             NvRamAddrRangeLength
++)
++{
++  EFI_STATUS            Status = EFI_SUCCESS;
++  ERST_RT_CONTEXT       *ErstRtCtx;
++  //
++  ErstRtCtx = AllocateReservedZeroPool (sizeof (ERST_RT_CONTEXT));
++  ErstRtCtx->Operation = ERST_END_OPERATION;
++  ErstRtCtx->RecordOffset = 0;
++  ErstRtCtx->BusyStatus = 0;
++  ErstRtCtx->CommandStatus = 0;
++  ErstRtCtx->KeyRecordId = 0;
++  ErstRtCtx->MaxTimeOfExecuteOperation = MAX_UINT64;
++  ErstRtCtx->RecordCount = 0;
++  ErstRtCtx->ErrorLogAddressRange = (UINT64)AllocateReservedZeroPool (BufferSize);
++  ErstRtCtx->ErrorLogAddressRangeLength = BufferSize;
++  ErstRtCtx->ErrorLogAttributes = 0;
++  ErstRtCtx->NvRamLogAddrRange = NvRamAddrRange;
++  ErstRtCtx->NvRamLogAddrRangeLength = NvRamAddrRangeLength;
++  ErstRtCtx->NvRamRecordOffset = 0;
++  ErstRtCtx->NvRamNextVallidRecordId = MAX_UINT64;
++  ErstRtCtx->NvRamNextValidRecordOffset = 0;
++  ErstRtCtx->NvRamAllRecordLength = NvRamAllRecordLength;
++  mErst.ErstInstructionEntry[0].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->Operation));
++  mErst.ErstInstructionEntry[1].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->Operation));
++  mErst.ErstInstructionEntry[2].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->Operation));
++  mErst.ErstInstructionEntry[3].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->Operation));
++  mErst.ErstInstructionEntry[4].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->RecordOffset));
++  mErst.ErstInstructionEntry[6].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->BusyStatus));
++  mErst.ErstInstructionEntry[7].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->CommandStatus));
++  mErst.ErstInstructionEntry[8].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->NvRamNextVallidRecordId));
++  mErst.ErstInstructionEntry[9].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->KeyRecordId));
++  mErst.ErstInstructionEntry[10].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->RecordCount));
++  mErst.ErstInstructionEntry[11].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->DummyWrite));
++  mErst.ErstInstructionEntry[12].RegisterRegion.Address = 0;
++  mErst.ErstInstructionEntry[13].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->ErrorLogAddressRange));
++  mErst.ErstInstructionEntry[14].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->ErrorLogAddressRangeLength));
++  mErst.ErstInstructionEntry[15].RegisterRegion.Address = (UINT64)(&(ErstRtCtx->ErrorLogAttributes));
++  Context->ErstHeader = (EFI_ACPI_6_1_ERROR_RECORD_SERIALIZATION_TABLE_HEADER*)&mErst;
++  Context->ExecuteOperationEntry = &(mErst.ErstInstructionEntry[5]);
++  Context->GetErrorLogAddrRangeAttributes = &(mErst.ErstInstructionEntry[15]);
++  Context->Rt = ErstRtCtx;
++  return Status;
++};
++
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.c
+new file mode 100644
+index 0000000000..eea73af229
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/Hest/hest.c
+@@ -0,0 +1,119 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include "ErrorSource/Ghes.h"
++#include "hest.h"
++#include <IndustryStandard/Acpi62.h>
++#include <Library/BaseLib.h>
++#include <Library/DebugLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include <Library/UefiBootServicesTableLib.h>
++#include "PlatformArch.h"
++
++EFI_STATUS HestAddErrorSourceDescriptor (
++  IN OUT HEST_CONTEXT  *Context,
++  IN VOID              *ErrorSourceDescriptor,
++  IN UINT32            SizeOfDescriptor
++)
++{
++  UINT16                                          *pSourceId;
++  VOID                                            *Descriptor;
++  EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER *HestHeader;
++
++  if ((Context == NULL) || (ErrorSourceDescriptor == NULL)) {
++    return EFI_INVALID_PARAMETER;
++  }
++  HestHeader = Context->HestHeader;
++  if (HestHeader->Header.Length + SizeOfDescriptor > Context->OccupiedMemorySize) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: Hest Size Too small\n", __FUNCTION__, __LINE__));
++    return EFI_BUFFER_TOO_SMALL;
++  }
++  Descriptor = (UINT8*)HestHeader + HestHeader->Header.Length;
++  gBS->CopyMem ((VOID*)Descriptor , ErrorSourceDescriptor, SizeOfDescriptor);
++  pSourceId = Descriptor + sizeof (UINT16);
++  *pSourceId = HestHeader->ErrorSourceCount;
++  HestHeader->Header.Length += SizeOfDescriptor;
++  HestHeader->ErrorSourceCount++;
++  Context->KeyErrorSource = Descriptor;
++  return EFI_SUCCESS;
++}
++
++VOID
++HestSetAcpiTable (
++  IN HEST_CONTEXT  *Context
++)
++{
++  UINTN                     AcpiTableHandle;
++  EFI_STATUS                Status;
++  UINT8                     Checksum;
++  EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER *HestHeader;
++  EFI_ACPI_SDT_HEADER       *Table;
++  EFI_ACPI_TABLE_VERSION    TableVersion;
++  UINTN                     TableKey;
++  UINT32                    Index;
++  if (Context == NULL) {
++    DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: ERROR\n", __FUNCTION__, __LINE__));
++    return;
++  }
++
++  HestHeader = Context->HestHeader;
++  Checksum = CalculateCheckSum8 ((UINT8*)(HestHeader),  HestHeader->Header.Length);
++  HestHeader->Header.Checksum = Checksum;
++  AcpiTableHandle = 0;
++  // see AcpiTableProtocol.c InstallAcpiTable
++  Status = mAcpiTableProtocol->InstallAcpiTable (
++                                  mAcpiTableProtocol,
++                                  HestHeader,
++                                  HestHeader->Header.Length,
++                                  &AcpiTableHandle);
++  for (Index = 0; Index < EFI_ACPI_MAX_NUM_TABLES; Index++) {
++    Status = mAcpiSdtProtocol->GetAcpiTable (Index, &Table, &TableVersion, &TableKey);
++    if (EFI_ERROR (Status)) {
++      break;
++    }
++    if (Table->Signature != EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE) {
++      continue;
++    }
++    mApeiTrustedfirmwareData->HestTableAddress = (EFI_PHYSICAL_ADDRESS)Table;
++    DEBUG ((DEBUG_ERROR, "Acpi HestSetAcpiTable Table = 0x%x.\n", (EFI_PHYSICAL_ADDRESS)Table));
++  }
++  DEBUG ((DEBUG_ERROR, "[%a]:[%dL]:OUT %llx, IN %llx \n", __FUNCTION__, __LINE__,
++          AcpiTableHandle, Context->HestHeader));
++  return;
++}
++
++EFI_STATUS
++HestHeaderCreator (
++  HEST_CONTEXT  *Context,
++  UINT32        PreAllocatedHestSize
++)
++{
++  DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: \n", __FUNCTION__, __LINE__));
++  if (PreAllocatedHestSize < sizeof (EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER)) {
++    return EFI_BUFFER_TOO_SMALL;
++  }
++  Context->HestHeader = AllocateReservedZeroPool (PreAllocatedHestSize);
++  *Context->HestHeader = (EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER) {
++   ARM_ACPI_HEADER (
++      EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_SIGNATURE,
++      EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_HEADER,
++      EFI_ACPI_6_1_HARDWARE_ERROR_SOURCE_TABLE_REVISION
++    ),
++    0x0
++  };
++  Context->KeyErrorSource = Context->HestHeader + 1;
++  Context->OccupiedMemorySize = PreAllocatedHestSize;
++  return EFI_SUCCESS;
++}
+diff --git a/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c b/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c
+new file mode 100644
+index 0000000000..de972b8a9e
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Drivers/Apei/OemApeiHi1620.c
+@@ -0,0 +1,337 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include <Guid/Cper.h>
++#include <IndustryStandard/Acpi62.h>
++#include <Library/DebugLib.h>
++#include <Library/IoLib.h>
++#include <Library/MemoryAllocationLib.h>
++#include <Library/UefiBootServicesTableLib.h>
++
++#include "Bert/bert.h"
++#include "Einj/einj.h"
++#include "ErrorSource/Ghes.h"
++#include "Erst/erst.h"
++#include "Hest/hest.h"
++#include "OemApeiHi1620.h"
++
++VOID
++GpioCombInit (
++  UINTN  Base,
++  UINT32 Pin
++)
++{
++  UINT32 Val = MmioRead32 (Base + GPIO_INT_MASK);
++  MmioWrite32 (Base + GPIO_INT_MASK, Val | Pin);
++  Val = MmioRead32 (Base + GPIO_INT_EN);
++  MmioWrite32 (Base + GPIO_INT_EN, Val | Pin);
++  Val = MmioRead32 (Base + GPIO_SWPORT_DDR);
++  MmioWrite32 (Base + GPIO_SWPORT_DDR, Val & (~Pin));
++  Val = MmioRead32 (Base + GPIO_INT_TYPE);
++  MmioWrite32 (Base + GPIO_INT_TYPE, Val & (~Pin));
++  Val = MmioRead32 (Base + GPIO_INT_POLARITY);
++  MmioWrite32 (Base + GPIO_INT_POLARITY, Val | Pin);
++  Val = MmioRead32 (Base + GPIO_LS_SYNC);
++  MmioWrite32 (Base + GPIO_LS_SYNC, Val & (~Pin));
++  MmioWrite32 (Base + GPIO_INT_COMB, 1);
++  return;
++}
++/************************************************
++*************** HEST ***************
++************************************************/
++
++/*****************************************************************************
++* @param EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE* GhesV2,Vector of GhesV2
++* @param UINT8 NumOfGhesV2
++* @param_out
++* @retval EFI_STATUS
++*****************************************************************************/
++EFI_STATUS
++GhesV2ContextForHest (
++  IN EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE GhesV2[MAX_GHES],
++  IN UINT8                                                          NumOfGhesV2
++)
++{
++  // ensuce the size is expected
++  if ((GhesV2 == NULL) || (NumOfGhesV2 != MAX_GHES)) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  UINT8  NumOfBlockPerGhes = 1;
++  UINT8  Iter = 0;
++  UINT32 BlockMemorySize;
++  UINT32 ErrorSeverityArray[MAX_GHES] = {
++           EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE,
++           EFI_ACPI_6_2_ERROR_SEVERITY_FATAL,
++           EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED};
++  VOID   *ErrorBlockHead;
++  VOID   *ErrorBlock;
++  VOID   *BlockMemory;
++  GHES_REGISTER  *GhesRegisters;
++  EFI_STATUS     Status = EFI_SUCCESS;
++
++  BlockMemorySize = MAX_GHES *
++    (sizeof (GHES_REGISTER) + NumOfBlockPerGhes * GENERIC_HARDWARE_ERROR_BLOCK_SIZE);
++  Status = gBS->AllocatePool (
++             EfiReservedMemoryType,
++             BlockMemorySize,
++             &BlockMemory
++           );
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  gBS->SetMem (BlockMemory, BlockMemorySize, 0);
++  GhesRegisters = BlockMemory;
++  ErrorBlockHead = BlockMemory + MAX_GHES * sizeof (GHES_REGISTER);
++  ErrorBlock = ErrorBlockHead;
++  for (Iter = 0; Iter < MAX_GHES; Iter++) {
++    GhesV2Initial (&GhesV2[Iter], GENERIC_HARDWARE_ERROR_BLOCK_SIZE);
++    GhesV2AddNotification (&GhesV2[Iter], EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV);
++    ErrorBlockInitial (ErrorBlock, ErrorSeverityArray[Iter]);
++    GhesV2LinkErrorBlock (&GhesV2[Iter], &GhesRegisters[Iter], ErrorBlock);
++    ErrorBlock += GhesV2[Iter].ErrorStatusBlockLength;
++  }
++  return EFI_SUCCESS;
++}
++/*****************************************************************************
++* @param EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE* GhesV2,Vector of GhesV2
++* @param UINT8 NumOfGhesV2
++* @param_out
++* @retval EFI_STATUS
++*****************************************************************************/
++
++EFI_STATUS
++GhesV1ContextForHest (
++  IN EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_STRUCTURE GhesV1[MAX_GHES],
++  IN UINT8                                                NumOfGhesV1
++)
++{
++  // ensuce the size is expected
++  if ((GhesV1 == NULL) || (NumOfGhesV1 != MAX_GHES)) {
++    return EFI_INVALID_PARAMETER;
++  }
++
++  UINT8      NumOfBlockPerGhes = 1;
++  UINT8      Iter = 0;
++  UINT32     BlockMemorySize = MAX_GHES *
++             (sizeof (UINT64) + NumOfBlockPerGhes * GENERIC_HARDWARE_ERROR_BLOCK_SIZE);
++  UINT32     ErrorSeverityArray[MAX_GHES] = {
++             EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTABLE,
++             EFI_ACPI_6_2_ERROR_SEVERITY_FATAL,
++             EFI_ACPI_6_2_ERROR_SEVERITY_CORRECTED};
++  VOID       *ErrorBlockHead;
++  VOID       *ErrorBlock;
++  VOID       *BlockMemory;
++  UINT64     *ptrBlockAddress;
++  EFI_STATUS Status = EFI_SUCCESS;
++  Status = gBS->AllocatePool (
++             EfiReservedMemoryType,
++             BlockMemorySize,
++             &BlockMemory
++           );
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  gBS->SetMem (BlockMemory, BlockMemorySize, 0);
++  ptrBlockAddress = BlockMemory;
++  ErrorBlockHead = BlockMemory + MAX_GHES * sizeof (UINT64);
++  ErrorBlock = ErrorBlockHead;
++  for (Iter = 0; Iter < MAX_GHES; Iter++) {
++    GhesV1Initial (&GhesV1[Iter], GENERIC_HARDWARE_ERROR_BLOCK_SIZE);
++    GhesV1AddNotification (&GhesV1[Iter], EFI_ACPI_6_1_HARDWARE_ERROR_NOTIFICATION_GSIV);
++    ErrorBlockInitial (ErrorBlock, ErrorSeverityArray[Iter]);
++    GhesV1LinkErrorBlock (&GhesV1[Iter], &ptrBlockAddress[Iter], ErrorBlock);
++    ErrorBlock += GhesV1[Iter].ErrorStatusBlockLength;
++  }
++  return EFI_SUCCESS;
++}
++
++VOID
++OemHestInitialNotification ()
++{
++  // GPIO init
++  // use int_msk to simulate
++  UINTN Base = IOMUX_REG_BASE;
++  //GPIO9, in document 'PhosphorV680 Totemiomux' iomg051,
++  //Set GPIO9 to pad_ex_int1
++  MmioWrite32 (Base + IOMG051, PAD_EX_INT1);
++  return;
++}
++
++VOID
++OemEinjInitialNotification ()
++{
++  UINTN Base = IOMUX_REG_BASE;
++  //use TB_GPIO_PIN10 for EINJ
++  MmioWrite32 (Base + IOMG052, PAD_EX_INT1);
++  return;
++}
++
++EFI_STATUS
++OemInitHestTable (
++  IN EFI_HANDLE         ImageHandle
++)
++{
++  EFI_STATUS                                                     Status = EFI_SUCCESS;
++  HEST_CONTEXT                                                   HestContext;
++  EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE GhesV2[MAX_GHES];
++  Status = HestHeaderCreator (&HestContext, HEST_TABLE_SIZE);
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  Status = GhesV2ContextForHest(GhesV2, MAX_GHES);
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  Status |= HestAddErrorSourceDescriptor (
++              &HestContext,
++              &GhesV2[0],
++              sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE)
++              );
++  mApeiTrustedfirmwareData->HestRecoverableErrorGhesV2 = HestContext.KeyErrorSource;
++  Status |= HestAddErrorSourceDescriptor (
++              &HestContext,
++              &GhesV2[1],
++              sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE)
++              );
++  mApeiTrustedfirmwareData->HestFatalErrorGhesV2 = HestContext.KeyErrorSource;
++  Status |= HestAddErrorSourceDescriptor (
++              &HestContext,
++              &GhesV2[2],
++              sizeof (EFI_ACPI_6_1_GENERIC_HARDWARE_ERROR_SOURCE_VERSION_2_STRUCTURE)
++              );
++  mApeiTrustedfirmwareData->HestCorrectedErrorGhesV2 = HestContext.KeyErrorSource;
++  OemHestInitialNotification ();
++  HestSetAcpiTable (&HestContext);
++  return Status;
++}
++/************************************************
++*************** BERT ***************
++************************************************/
++
++EFI_STATUS
++OemInitBertTable (
++  IN EFI_HANDLE ImageHandle
++)
++{
++  BERT_CONTEXT Context;
++  BOOLEAN      Status;
++  Status = BertHeaderCreator (&Context, BOOT_ERROR_REGION_SIZE);
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  ErrorBlockInitial (Context.Block, EFI_ACPI_6_2_ERROR_SEVERITY_NONE);
++  BertSetAcpiTable (&Context);
++  DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: %r\n", __FUNCTION__, __LINE__, Status));
++  return EFI_SUCCESS;
++}
++/************************************************
++*************** EINJ ***************
++************************************************/
++EFI_STATUS
++OemEinjConfigExecuteOperationEntry (
++  EINJ_CONTEXT *Context
++)
++{
++  EFI_ACPI_6_0_EINJ_INJECTION_INSTRUCTION_ENTRY* KeyEntry = Context->ExecuteOperationEntry;
++  OemEinjInitialNotification ();
++  //use TB_GPIO_PIN10 for EINJ
++  KeyEntry->RegisterRegion.Address = PcdGet64 (PcdCpldBaseAddress) + CPLD_GPIO10_INT_OFFSET;
++  KeyEntry->Mask = CPLD_MASK;
++  KeyEntry->Value = CPLD_VALUE;
++  return EFI_SUCCESS;
++}
++
++EFI_STATUS
++OemInitEinjTable (
++)
++{
++  EFI_STATUS    Status;
++  EINJ_CONTEXT  Context;
++  Status = EinjHeaderCreator (&Context);
++  if (EFI_ERROR (Status)) {
++    return Status;
++  }
++  (VOID)EinjConfigErrorInjectCapability (&Context, 0xFFF);// TBD
++  (VOID)OemEinjConfigExecuteOperationEntry (&Context);
++  EinjSetAcpiTable (&Context);
++  DEBUG ((DEBUG_ERROR, "[%a]:[%dL]: %d\n", __FUNCTION__, __LINE__, Status));
++  return EFI_SUCCESS;
++}
++/************************************************
++*************** ERST ***************
++************************************************/
++
++EFI_STATUS
++OemErstConfigExecuteOperationEntry (
++  ERST_BOOT_CONTEXT *Context
++)
++{
++  EFI_ACPI_6_1_ERST_SERIALIZATION_INSTRUCTION_ENTRY *KeyEntry;
++  KeyEntry = Context->ExecuteOperationEntry;
++  KeyEntry->RegisterRegion.Address = GPIO1_BASE + GPIO_INT_MASK;
++  KeyEntry->Value = 0x10;
++  KeyEntry->Mask = 0xFFFFFFFF;
++  GpioCombInit (GPIO1_BASE, 0xFFFF);
++  return EFI_SUCCESS;
++}
++
++BOOLEAN
++GetNvRamRegion (
++  OUT  VOID  **NvRamAddrRange,
++  OUT UINT64 *NvRamAddrRangeLength
++)
++{
++  UINT32 Store = ERST_RECORD_STORE_IN_MEM;
++  switch (Store) {
++    case (ERST_RECORD_STORE_IN_NVRAM):
++      break;
++    case (ERST_RECORD_STORE_IN_MEM):
++      * NvRamAddrRangeLength = ERST_DATASTORE_SIZE;
++      * NvRamAddrRange = AllocateReservedZeroPool (ERST_DATASTORE_SIZE);
++      break;
++    case (ERST_RECORD_STORE_IN_SPI_FLASH):
++      break;
++    default:
++      ;
++  }
++  return TRUE;
++}
++
++/***OEM***/
++EFI_STATUS
++OemInitErstTable (
++)
++{
++  EFI_STATUS        Status = ERST_STATUS_SUCCESS;
++  ERST_BOOT_CONTEXT Context;
++  UINT64            BufferSize = ERST_DATASTORE_SIZE;
++  VOID              *NvRamAddrRange;
++  UINT64            NvRamAddrRangeLength;
++  UINT64            NvRamAllRecordLength;
++
++  GetNvRamRegion (&NvRamAddrRange, &NvRamAddrRangeLength);
++  NvRamAllRecordLength = 0;
++  Status = ErstHeaderCreator (
++             &Context,
++             BufferSize,
++             NvRamAddrRange,
++             NvRamAllRecordLength,
++             NvRamAddrRangeLength);
++  OemErstConfigExecuteOperationEntry (&Context);
++  mApeiTrustedfirmwareData->ErstContext = (VOID*)Context.Rt;
++  ErstSetAcpiTable (&Context);
++  return Status;
++};
+-- 
+2.17.0
+
diff --git a/v2/v2-0035-Silicon-Hisilicon-D06-Add-some-Lpc-macro-to-LpcLi.patch b/v2/v2-0035-Silicon-Hisilicon-D06-Add-some-Lpc-macro-to-LpcLi.patch
new file mode 100644
index 0000000000..725f165ed0
--- /dev/null
+++ b/v2/v2-0035-Silicon-Hisilicon-D06-Add-some-Lpc-macro-to-LpcLi.patch
@@ -0,0 +1,85 @@
+From a46c982393de6a4304c44b7f3841e106fb7fd6c9 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Mon, 23 Jul 2018 14:59:28 +0800
+Subject: [PATCH edk2-platforms v2 35/43] Silicon/Hisilicon/D06: Add some Lpc
+ macro to LpcLib.h
+
+Add some Lpc macro to LpcLib.h for D06.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Include/Library/LpcLib.h | 51 +++++++++++++++++++-
+ 1 file changed, 49 insertions(+), 2 deletions(-)
+
+diff --git a/Silicon/Hisilicon/Include/Library/LpcLib.h b/Silicon/Hisilicon/Include/Library/LpcLib.h
+index 236a52ba45..5cf08ccde1 100755
+--- a/Silicon/Hisilicon/Include/Library/LpcLib.h
++++ b/Silicon/Hisilicon/Include/Library/LpcLib.h
+@@ -1,7 +1,7 @@
+ /** @file
+ *
+-*  Copyright (c) 2016, Hisilicon Limited. All rights reserved.
+-*  Copyright (c) 2016, Linaro Limited. All rights reserved.
++*  Copyright (c) 2016-2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2016-2018, Linaro Limited. All rights reserved.
+ *
+ *  This program and the accompanying materials
+ *  are licensed and made available under the terms and conditions of the BSD License
+@@ -18,6 +18,53 @@
+ 
+ #include <Uefi.h>
+ 
++#define PCIE_SUBSYS_IOMUX       0x201100000
++#define PCIE_SUBSYS_IOMG019     (PCIE_SUBSYS_IOMUX + 0x48)
++#define PCIE_SUBSYS_IOMG020     (PCIE_SUBSYS_IOMUX + 0x4C)
++#define PCIE_SUBSYS_IOMG021     (PCIE_SUBSYS_IOMUX + 0x50)
++#define PCIE_SUBSYS_IOMG022     (PCIE_SUBSYS_IOMUX + 0x54)
++#define PCIE_SUBSYS_IOMG023     (PCIE_SUBSYS_IOMUX + 0x58)
++#define PCIE_SUBSYS_IOMG024     (PCIE_SUBSYS_IOMUX + 0x5C)
++#define PCIE_SUBSYS_IOMG025     (PCIE_SUBSYS_IOMUX + 0x60)
++#define PCIE_SUBSYS_IOMG028     (PCIE_SUBSYS_IOMUX + 0x6C)
++
++#define IO_MGMT_SUBCTRL_BASE    0x201070000
++#define SC_LPC_RESET_REQ_REG    (IO_MGMT_SUBCTRL_BASE + 0x0a58)
++#define SC_LPC_RESET_DREQ_REG   (IO_MGMT_SUBCTRL_BASE + 0x0a5c)
++#define SC_LPC_SEL              (IO_MGMT_SUBCTRL_BASE + 0x2400)
++
++
++#define LPCD06_BASE             0x201190000
++#define LPC_FIRM_SPACE0_CFG     (LPCD06_BASE + 0x100)
++#define LPC_FIRM_SPACE1_CFG     (LPCD06_BASE + 0x104)
++#define LPC_FIRM_SPACE2_CFG     (LPCD06_BASE + 0x108)
++#define LPC_FIRM_SPACE3_CFG     (LPCD06_BASE + 0x10C)
++#define LPC_FIRM_SPACE4_CFG     (LPCD06_BASE + 0x110)
++#define LPC_FIRM_SPACE5_CFG     (LPCD06_BASE + 0x114)
++#define LPC_FIRM_SPACE6_CFG     (LPCD06_BASE + 0x118)
++#define LPC_FIRM_SPACE7_CFG     (LPCD06_BASE + 0x11C)
++#define LPC_MEM_SPACE0_CFG      (LPCD06_BASE + 0x120)
++#define LPC_MEM_SPACE1_CFG      (LPCD06_BASE + 0x124)
++#define LPC_MEM_SPACE2_CFG      (LPCD06_BASE + 0x128)
++#define LPC_MEM_SPACE3_CFG      (LPCD06_BASE + 0x12C)
++#define LPC_MEM_SPACE4_CFG      (LPCD06_BASE + 0x130)
++#define LPC_MEM_SPACE5_CFG      (LPCD06_BASE + 0x134)
++#define LPC_MEM_SPACE6_CFG      (LPCD06_BASE + 0x138)
++
++#define LPCD06_START_REG        (LPCD06_BASE + 0x00)
++#define LPCD06_OP_STATUS_REG    (LPCD06_BASE + 0x04)
++#define LPCD06_IRQ_ST_REG       (LPCD06_BASE + 0x08)
++#define LPCD06_OP_LEN_REG       (LPCD06_BASE + 0x10)
++#define LPCD06_CMD_REG          (LPCD06_BASE + 0x14)
++#define LPCD06_ADDR_REG         (LPCD06_BASE + 0x20)
++#define LPCD06_WDATA_REG        (LPCD06_BASE + 0x24)
++#define LPCD06_RDATA_REG        (LPCD06_BASE + 0x28)
++
++#define LPC_SIRQ_CTR0           (LPCD06_BASE + 0x80)
++#define LPC_SIRQ_CTR1           (LPCD06_BASE + 0x84)
++#define LPC_SIRQ_INT_MASK       (LPCD06_BASE + 0x94)
++
++
+ #define PCIE_SUBSYS_IO_MUX      0xA0170000
+ #define PCIE_SUBSYS_IOMG033     (PCIE_SUBSYS_IO_MUX + 0x84)
+ #define PCIE_SUBSYS_IOMG035     (PCIE_SUBSYS_IO_MUX + 0x8C)
+-- 
+2.17.0
+
diff --git a/v2/v2-0036-Platform-Hisilicon-D06-Add-capsule-upgrade-suppor.patch b/v2/v2-0036-Platform-Hisilicon-D06-Add-capsule-upgrade-suppor.patch
new file mode 100644
index 0000000000..90ff020c24
--- /dev/null
+++ b/v2/v2-0036-Platform-Hisilicon-D06-Add-capsule-upgrade-suppor.patch
@@ -0,0 +1,434 @@
+From 896b986f7503e3150fd3fbfb5f8edead0c2a0f72 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Wed, 27 Jun 2018 16:05:26 +0800
+Subject: [PATCH edk2-platforms v2 36/43] Platform/Hisilicon/D06: Add capsule
+ upgrade support
+
+This module support updating the boot CPU firmware only.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                                           | 14 ++++
+ Platform/Hisilicon/D06/D06.fdf                                                           | 72 ++++++++++++++++-
+ Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf     | 50 ++++++++++++
+ Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c    | 70 +++++++++++++++++
+ Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini | 46 +++++++++++
+ Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc    | 81 ++++++++++++++++++++
+ 6 files changed, 332 insertions(+), 1 deletion(-)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 9550e0d497..fad6fcc747 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -121,6 +121,11 @@
+   gHisiTokenSpaceGuid.PcdIsItsSupported|TRUE
+   gArmTokenSpaceGuid.PcdArmGicV3WithV2Legacy|FALSE
+   gEfiMdeModulePkgTokenSpaceGuid.PcdHiiOsRuntimeSupport|FALSE
++[PcdsDynamicExDefault.common.DEFAULT]
++  gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor|{0x0}|VOID*|0x100
++  gEfiMdeModulePkgTokenSpaceGuid.PcdSystemFmpCapsuleImageTypeIdGuid|{0x29, 0x3d, 0x4b, 0xd3, 0x85, 0x00, 0xb3, 0x4a, 0x8b, 0xe8, 0x84, 0x18, 0x8c, 0xc5, 0x04, 0x89}
++  gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareFileGuid|{0xcf, 0x4f, 0x2e, 0x64, 0xf7, 0x2d, 0x15, 0x44, 0x8b, 0x70, 0xa0, 0x39, 0x09, 0xc5, 0x7b, 0x55}
++
+ 
+ [PcdsFixedAtBuild.common]
+   gArmPlatformTokenSpaceGuid.PcdCoreCount|48
+@@ -266,6 +271,7 @@
+   Platform/Hisilicon/D06/EarlyConfigPeim/EarlyConfigPeimD06.inf
+   Silicon/Hisilicon/Drivers/VersionInfoPeim/VersionInfoPeim.inf
+ 
++  Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+   MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf {
+     <LibraryClasses>
+       NULL|MdeModulePkg/Library/LzmaCustomDecompressLib/LzmaCustomDecompressLib.inf
+@@ -386,6 +392,8 @@
+   MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+   MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+   MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
++  SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
++  MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
+   #
+   # FAT filesystem + GPT/MBR partitioning
+   #
+@@ -434,6 +442,12 @@
+   MdeModulePkg/Universal/DisplayEngineDxe/DisplayEngineDxe.inf
+   MdeModulePkg/Universal/SetupBrowserDxe/SetupBrowserDxe.inf
+   MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
++  SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf {
++    <LibraryClasses>
++      FmpAuthenticationLib|SecurityPkg/Library/FmpAuthenticationLibPkcs7/FmpAuthenticationLibPkcs7.inf
++  }
++
++  MdeModulePkg/Application/CapsuleApp/CapsuleApp.inf
+ 
+   #
+   # UEFI application (Shell Embedded Boot Loader)
+diff --git a/Platform/Hisilicon/D06/D06.fdf b/Platform/Hisilicon/D06/D06.fdf
+index 90379b8558..8c3f4f9932 100644
+--- a/Platform/Hisilicon/D06/D06.fdf
++++ b/Platform/Hisilicon/D06/D06.fdf
+@@ -308,7 +308,9 @@ READ_LOCK_STATUS   = TRUE
+   INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+ 
+   INF Silicon/Hisilicon/Hi1620/Drivers/Pl011DebugSerialPortInitDxe/Pl011DebugSerialPortInitDxe.inf
+-  INF MdeModulePkg/Universal/Network/SnpDxe/SnpDxe.inf
++  INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareReportDxe.inf
++  INF MdeModulePkg/Universal/EsrtDxe/EsrtDxe.inf
++
+   #
+   # Build Shell from latest source code instead of prebuilt binary
+   #
+@@ -364,11 +366,79 @@ READ_LOCK_STATUS   = TRUE
+ 
+   INF MdeModulePkg/Core/DxeIplPeim/DxeIpl.inf
+ 
++  INF RuleOverride = FMP_IMAGE_DESC Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+   FILE FV_IMAGE = 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {
+     SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUIRED = TRUE {
+       SECTION FV_IMAGE = FVMAIN
+     }
+   }
++[FV.CapsuleDispatchFv]
++FvAlignment        = 16
++ERASE_POLARITY     = 1
++MEMORY_MAPPED      = TRUE
++STICKY_WRITE       = TRUE
++LOCK_CAP           = TRUE
++LOCK_STATUS        = TRUE
++WRITE_DISABLED_CAP = TRUE
++WRITE_ENABLED_CAP  = TRUE
++WRITE_STATUS       = TRUE
++WRITE_LOCK_CAP     = TRUE
++WRITE_LOCK_STATUS  = TRUE
++READ_DISABLED_CAP  = TRUE
++READ_ENABLED_CAP   = TRUE
++READ_STATUS        = TRUE
++READ_LOCK_CAP      = TRUE
++READ_LOCK_STATUS   = TRUE
++
++  INF SignedCapsulePkg/Universal/SystemFirmwareUpdate/SystemFirmwareUpdateDxe.inf
++
++[FV.SystemFirmwareUpdateCargo]
++FvAlignment        = 16
++ERASE_POLARITY     = 1
++MEMORY_MAPPED      = TRUE
++STICKY_WRITE       = TRUE
++LOCK_CAP           = TRUE
++LOCK_STATUS        = TRUE
++WRITE_DISABLED_CAP = TRUE
++WRITE_ENABLED_CAP  = TRUE
++WRITE_STATUS       = TRUE
++WRITE_LOCK_CAP     = TRUE
++WRITE_LOCK_STATUS  = TRUE
++READ_DISABLED_CAP  = TRUE
++READ_ENABLED_CAP   = TRUE
++READ_STATUS        = TRUE
++READ_LOCK_CAP      = TRUE
++READ_LOCK_STATUS   = TRUE
++
++  FILE RAW = 642e4fcf-2df7-4415-8b70-a03909c57b55 { # PcdEdkiiSystemFirmwareFileGuid
++    FD = D06
++  }
++
++  FILE RAW = ce57b167-b0e4-41e8-a897-5f4feb781d40 { # gEdkiiSystemFmpCapsuleDriverFvFileGuid
++    FV = CapsuleDispatchFv
++  }
++
++  FILE RAW = 812136D3-4D3A-433A-9418-29BB9BF78F6E { # gEdkiiSystemFmpCapsuleConfigFileGuid
++    Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
++  }
++
++[FmpPayload.FmpPayloadSystemFirmwarePkcs7]
++IMAGE_HEADER_INIT_VERSION = 0x02
++IMAGE_TYPE_ID             = df8fe8d1-e937-45b8-9691-c4b5e183874e # PcdSystemFmpCapsuleImageTypeIdGuid
++IMAGE_INDEX               = 0x1
++HARDWARE_INSTANCE         = 0x0
++MONOTONIC_COUNT           = 0x1
++CERTIFICATE_GUID          = 4AAFD29D-68DF-49EE-8AA9-347D375665A7 # PKCS7
++
++  FV = SystemFirmwareUpdateCargo
++
++[Capsule.D06FirmwareUpdateCapsuleFmpPkcs7]
++CAPSULE_GUID                = 6dcbd5ed-e82d-4c44-bda1-7194199ad92a # gEfiFmpCapsuleGuid
++CAPSULE_HEADER_SIZE         = 0x20
++CAPSULE_HEADER_INIT_VERSION = 0x1
++
++  FMP_PAYLOAD = FmpPayloadSystemFirmwarePkcs7
++
+ 
+ !include Silicon/Hisilicon/Hisilicon.fdf.inc
+ 
+diff --git a/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf b/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+new file mode 100644
+index 0000000000..fc1832fa5f
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.inf
+@@ -0,0 +1,50 @@
++## @file
++#  System Firmware descriptor.
++#
++#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#  Copyright (c) 2018, Linaro Limited. All rights reserved.
++#  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution.  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++##
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = SystemFirmwareDescriptor
++  FILE_GUID                      = 90B2B846-CA6D-4D6E-A8D3-C140A8E110AC
++  MODULE_TYPE                    = PEIM
++  VERSION_STRING                 = 1.0
++  ENTRY_POINT                    = SystemFirmwareDescriptorPeimEntry
++
++[Sources]
++  SystemFirmwareDescriptorPei.c
++  SystemFirmwareDescriptor.aslc
++
++[Packages]
++  ArmPkg/ArmPkg.dec
++  ArmPlatformPkg/ArmPlatformPkg.dec
++  MdeModulePkg/MdeModulePkg.dec
++  MdePkg/MdePkg.dec
++  SignedCapsulePkg/SignedCapsulePkg.dec
++
++[LibraryClasses]
++  DebugLib
++  PcdLib
++  PeimEntryPoint
++  PeiServicesLib
++
++[FixedPcd]
++  gArmTokenSpaceGuid.PcdFdSize
++
++[Pcd]
++  gEfiSignedCapsulePkgTokenSpaceGuid.PcdEdkiiSystemFirmwareImageDescriptor
++
++[Depex]
++  TRUE
+diff --git a/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c b/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
+new file mode 100644
+index 0000000000..27c0a718f8
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptorPei.c
+@@ -0,0 +1,70 @@
++/** @file
++  System Firmware descriptor producer.
++
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++  Copyright (c) 2018, Linaro Limited. All rights reserved.
++  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
++
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#include <PiPei.h>
++#include <Guid/EdkiiSystemFmpCapsule.h>
++#include <Library/DebugLib.h>
++#include <Library/PcdLib.h>
++#include <Library/PeiServicesLib.h>
++#include <Protocol/FirmwareManagement.h>
++
++/**
++  Entrypoint for SystemFirmwareDescriptor PEIM.
++
++  @param[in]  FileHandle  Handle of the file being invoked.
++  @param[in]  PeiServices Describes the list of possible PEI Services.
++
++  @retval EFI_SUCCESS            PPI successfully installed.
++**/
++EFI_STATUS
++EFIAPI
++SystemFirmwareDescriptorPeimEntry (
++  IN EFI_PEI_FILE_HANDLE     FileHandle,
++  IN CONST EFI_PEI_SERVICES  **PeiServices
++  )
++{
++  EFI_STATUS                              Status;
++  EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR  *Descriptor;
++  UINTN                                   Size;
++  UINTN                                   Index;
++  UINT32                                  AuthenticationStatus;
++
++  //
++  // Search RAW section.
++  //
++
++  Index = 0;
++  while (TRUE) {
++    Status = PeiServicesFfsFindSectionData3 (EFI_SECTION_RAW, Index, FileHandle, (VOID **)&Descriptor, &AuthenticationStatus);
++    if (EFI_ERROR (Status)) {
++      // Should not happen, must something wrong in FDF.
++      DEBUG ((DEBUG_ERROR, "Not found SystemFirmwareDescriptor in fdf !\n"));
++      return EFI_NOT_FOUND;
++    }
++    if (Descriptor->Signature == EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE) {
++      break;
++    }
++    Index++;
++  }
++
++  DEBUG ((DEBUG_INFO, "EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR size - 0x%x\n", Descriptor->Length));
++
++  Size = Descriptor->Length;
++  PcdSetPtrS (PcdEdkiiSystemFirmwareImageDescriptor, &Size, Descriptor);
++
++  return EFI_SUCCESS;
++}
+diff --git a/Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini b/Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
+new file mode 100644
+index 0000000000..80f253b235
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Capsule/SystemFirmwareUpdateConfig/SystemFirmwareUpdateConfig.ini
+@@ -0,0 +1,46 @@
++#
++#  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++#  Copyright (c) 2018, Linaro Limited. All rights reserved.
++#  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution.  The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php
++#
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++##
++
++[Head]
++NumOfUpdate = 3
++NumOfRecovery = 0
++Update0 = SysFvMain
++Update1 = SysCustom
++Update2 = SysNvRam
++
++[SysFvMain]
++FirmwareType  = 0             # 0 - SystemFirmware, 1 - NvRam
++AddressType   = 0             # 0 - relative address, 1 - absolute address.
++BaseAddress   = 0x00000000    # Base address offset on flash
++Length        = 0x003C0000    # Length
++ImageOffset   = 0x00000000    # Image offset of this SystemFirmware image
++FileGuid      = 642e4fcf-2df7-4415-8b70-a03909c57b55  # PcdEdkiiSystemFirmwareFileGuid
++
++[SysCustom]
++FirmwareType  = 0             # 0 - SystemFirmware, 1 - NvRam
++AddressType   = 0             # 0 - relative address, 1 - absolute address.
++BaseAddress   = 0x003F0000    # Base address offset on flash
++Length        = 0x00010000    # Length
++ImageOffset   = 0x003F0000    # Image offset of this SystemFirmware image
++FileGuid      = 642e4fcf-2df7-4415-8b70-a03909c57b55  # PcdEdkiiSystemFirmwareFileGuid
++
++[SysNvRam]
++FirmwareType  = 1             # 0 - SystemFirmware, 1 - NvRam
++AddressType   = 0             # 0 - relative address, 1 - absolute address.
++BaseAddress   = 0x003C0000    # Base address offset on flash
++Length        = 0x00020000    # Length
++ImageOffset   = 0x003C0000    # Image offset of this SystemFirmware image
++FileGuid      = 642e4fcf-2df7-4415-8b70-a03909c57b55  # PcdEdkiiSystemFirmwareFileGuid
++
+diff --git a/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc b/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
+new file mode 100644
+index 0000000000..36175338dd
+--- /dev/null
++++ b/Platform/Hisilicon/D06/Drivers/SystemFirmwareDescriptor/SystemFirmwareDescriptor.aslc
+@@ -0,0 +1,81 @@
++/** @file
++  System Firmware descriptor.
++
++  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++  Copyright (c) 2018, Linaro Limited. All rights reserved.
++  Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>
++
++  This program and the accompanying materials
++  are licensed and made available under the terms and conditions of the BSD License
++  which accompanies this distribution.  The full text of the license may be found at
++  http://opensource.org/licenses/bsd-license.php
++
++  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++
++**/
++
++#include <PiPei.h>
++#include <Guid/EdkiiSystemFmpCapsule.h>
++#include <Protocol/FirmwareManagement.h>
++
++#define PACKAGE_VERSION                     0xFFFFFFFF
++#define PACKAGE_VERSION_STRING              L"Unknown"
++
++#define CURRENT_FIRMWARE_VERSION            0x00000002
++#define CURRENT_FIRMWARE_VERSION_STRING     L"0x00000002"
++#define LOWEST_SUPPORTED_FIRMWARE_VERSION   0x00000001
++
++#define IMAGE_ID                            SIGNATURE_64('H','W','A', 'R', 'M', '_', 'F', 'd')
++#define IMAGE_ID_STRING                     L"ARMPlatformFd"
++
++// PcdSystemFmpCapsuleImageTypeIdGuid
++#define IMAGE_TYPE_ID_GUID                  { 0xdf8fe8d1, 0xe937, 0x45b8, { 0x96, 0x91, 0xc4, 0xb5, 0xe1, 0x83, 0x87, 0x4e } }
++
++typedef struct {
++  EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR  Descriptor;
++  // real string data
++  CHAR16                                  ImageIdNameStr[ARRAY_SIZE (IMAGE_ID_STRING)];
++  CHAR16                                  VersionNameStr[ARRAY_SIZE (CURRENT_FIRMWARE_VERSION_STRING)];
++  CHAR16                                  PackageVersionNameStr[ARRAY_SIZE (PACKAGE_VERSION_STRING)];
++} IMAGE_DESCRIPTOR;
++
++IMAGE_DESCRIPTOR mImageDescriptor =
++{
++  {
++    EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR_SIGNATURE,
++    sizeof (EDKII_SYSTEM_FIRMWARE_IMAGE_DESCRIPTOR),
++    sizeof (IMAGE_DESCRIPTOR),
++    PACKAGE_VERSION,                                       // PackageVersion
++    OFFSET_OF (IMAGE_DESCRIPTOR, PackageVersionNameStr),   // PackageVersionName
++    1,                                                     // ImageIndex;
++    {0x0},                                                 // Reserved
++    IMAGE_TYPE_ID_GUID,                                    // ImageTypeId;
++    IMAGE_ID,                                              // ImageId;
++    OFFSET_OF (IMAGE_DESCRIPTOR, ImageIdNameStr),          // ImageIdName;
++    CURRENT_FIRMWARE_VERSION,                              // Version;
++    OFFSET_OF (IMAGE_DESCRIPTOR, VersionNameStr),          // VersionName;
++    {0x0},                                                 // Reserved2
++    FixedPcdGet32 (PcdFdSize),                             // Size;
++    IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
++      IMAGE_ATTRIBUTE_RESET_REQUIRED |
++      IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
++      IMAGE_ATTRIBUTE_IN_USE,                              // AttributesSupported;
++    IMAGE_ATTRIBUTE_IMAGE_UPDATABLE |
++      IMAGE_ATTRIBUTE_RESET_REQUIRED |
++      IMAGE_ATTRIBUTE_AUTHENTICATION_REQUIRED |
++      IMAGE_ATTRIBUTE_IN_USE,                              // AttributesSetting;
++    0x0,                                                   // Compatibilities;
++    LOWEST_SUPPORTED_FIRMWARE_VERSION,                     // LowestSupportedImageVersion;
++    0x00000000,                                            // LastAttemptVersion;
++    0,                                                     // LastAttemptStatus;
++    {0x0},                                                 // Reserved3
++    0,                                                     // HardwareInstance;
++  },
++  // real string data
++  {IMAGE_ID_STRING},
++  {CURRENT_FIRMWARE_VERSION_STRING},
++  {PACKAGE_VERSION_STRING},
++};
++
++VOID* CONST ReferenceAcpiTable = &mImageDescriptor;
+-- 
+2.17.0
+
diff --git a/v2/v2-0037-Silicon-Hisilicon-D06-Modify-for-close-slave-core.patch b/v2/v2-0037-Silicon-Hisilicon-D06-Modify-for-close-slave-core.patch
new file mode 100644
index 0000000000..f92a3f1079
--- /dev/null
+++ b/v2/v2-0037-Silicon-Hisilicon-D06-Modify-for-close-slave-core.patch
@@ -0,0 +1,33 @@
+From 4ea5cbf0881cadf58ed3b10114748a4e3f331313 Mon Sep 17 00:00:00 2001
+From: ZhenYao <yaozhen6@huawei.com>
+Date: Fri, 13 Jul 2018 16:41:12 +0800
+Subject: [PATCH edk2-platforms v2 37/43] Silicon/Hisilicon/D06: Modify for
+ close slave core clock.
+
+When BIOS booting, the power consumption is too high, so need close
+some clusters clock that don't work to reduce power consumption.
+
+The implementation of functions is in edk2-non-osi.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: ZhenYao <yaozhen6@huawei.com>
+---
+ Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
+index ec2b9a36e7..3ccfc6bee3 100644
+--- a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
++++ b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
+@@ -102,5 +102,8 @@ VOID PlatformEventBroadcastConfig(VOID);
+ UINTN GetDjtagRegBase(UINT32 NodeId);
+ VOID LlcCleanInvalidateAsm(VOID);
+ VOID PlatformMdioInit(VOID);
++VOID DisableClusterClock(UINTN CpuClusterBase);
++VOID EnableClusterClock(UINTN CpuClusterBase);
++VOID DisableSocketClock (UINT8 Skt);
+ 
+ #endif
+-- 
+2.17.0
+
diff --git a/v2/v2-0038-Silicon-Hisilicon-D06-Add-I2C-Bus-Exception-handl.patch b/v2/v2-0038-Silicon-Hisilicon-D06-Add-I2C-Bus-Exception-handl.patch
new file mode 100644
index 0000000000..46c04cde4f
--- /dev/null
+++ b/v2/v2-0038-Silicon-Hisilicon-D06-Add-I2C-Bus-Exception-handl.patch
@@ -0,0 +1,38 @@
+From 32cf35394afae023397a9809a3519a5c677a1b50 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Wed, 11 Jul 2018 14:16:24 +0800
+Subject: [PATCH edk2-platforms v2 38/43] Silicon/Hisilicon/D06: Add I2C Bus
+ Exception handle function
+
+During the period of I2c accessing, if the board is reset
+unexpectedly, and because the I2c client can not reset,
+the SDA will be always pull down, then it cause I2C bus
+Exception.
+
+Follow the Hi1620 I2C FS chapter 1.8.2 design, add I2C
+Bus Exception handle function. It will Config SCL and SDA
+to GPIO, and set the reversal frequency of SCL to 10KHz.
+
+The implementation of functions is in edk2-non-osi.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h | 3 +++
+ 1 file changed, 3 insertions(+)
+
+diff --git a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
+index 3ccfc6bee3..a232e52ed7 100644
+--- a/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
++++ b/Silicon/Hisilicon/Include/Library/PlatformSysCtrlLib.h
+@@ -106,4 +106,7 @@ VOID DisableClusterClock(UINTN CpuClusterBase);
+ VOID EnableClusterClock(UINTN CpuClusterBase);
+ VOID DisableSocketClock (UINT8 Skt);
+ 
++EFI_STATUS EFIAPI HandleI2CException (UINT32 Socket, UINT32 Port);
++EFI_STATUS EFIAPI HandleI2CExceptionBySocket (UINT32 Socket);
++
+ #endif
+-- 
+2.17.0
+
diff --git a/v2/v2-0039-Silicon-Hisilicon-Setup-Support-SPCR-table-switch.patch b/v2/v2-0039-Silicon-Hisilicon-Setup-Support-SPCR-table-switch.patch
new file mode 100644
index 0000000000..4be0e70651
--- /dev/null
+++ b/v2/v2-0039-Silicon-Hisilicon-Setup-Support-SPCR-table-switch.patch
@@ -0,0 +1,84 @@
+From 7a637184582648fc75c233a3665be6fb9f3a043c Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Mon, 23 Jul 2018 17:20:16 +0800
+Subject: [PATCH edk2-platforms v2 39/43] Silicon/Hisilicon/Setup: Support SPCR
+ table switch
+
+If install SPCR table, KVM will not output while install or boot
+some OS, like ubuntu, so add SPCR switch setup item and set it
+disable by default.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+Signed-off-by: Heyi Guo <heyi.guo@linaro.org>
+---
+ Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf |  1 +
+ Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c   | 24 ++++++++++++++++++++
+ 2 files changed, 25 insertions(+)
+
+diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+index 281a4f2ebd..3d133aff85 100644
+--- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
++++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/AcpiPlatformDxe.inf
+@@ -51,6 +51,7 @@
+ 
+ [Guids]
+   gHisiEfiMemoryMapGuid
++  gOemConfigGuid
+ 
+ [Pcd]
+   gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiTableStorageFile    ## CONSUMES
+diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+index 54f49977c3..32878ca4f9 100644
+--- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
++++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+@@ -16,8 +16,10 @@
+ #include <Library/DebugLib.h>
+ #include <Library/HobLib.h>
+ #include <Library/HwMemInitLib.h>
++#include <Library/OemConfigData.h>
+ #include <Library/OemMiscLib.h>
+ #include <Library/UefiBootServicesTableLib.h>
++#include <Library/UefiRuntimeServicesTableLib.h>
+ #include <Library/UefiLib.h>
+ 
+ #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET)
+@@ -114,6 +116,25 @@ UpdateSlit (
+   return  EFI_SUCCESS;
+ }
+ 
++STATIC
++EFI_STATUS
++IsNeedSpcr (
++  IN OUT EFI_ACPI_DESCRIPTION_HEADER  *Table
++  )
++{
++  EFI_STATUS                     Status;
++  OEM_CONFIG_DATA                SetupData;
++  UINTN                          DataSize = sizeof (OEM_CONFIG_DATA);
++
++  Status = gRT->GetVariable (OEM_CONFIG_NAME, &gOemConfigGuid, NULL, &DataSize, &SetupData);
++  if (!EFI_ERROR (Status) && (SetupData.EnableSpcr == FALSE)) {
++    return EFI_ABORTED;
++  }
++
++  return EFI_SUCCESS;
++}
++
++
+ EFI_STATUS
+ UpdateAcpiTable (
+   IN OUT EFI_ACPI_DESCRIPTION_HEADER      *TableHeader
+@@ -130,6 +151,9 @@ UpdateAcpiTable (
+   case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE:
+     Status = UpdateSlit (TableHeader);
+     break;
++  case EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE:
++    Status = IsNeedSpcr (TableHeader);
++    break;
+   }
+   return Status;
+ }
+-- 
+2.17.0
+
diff --git a/v2/v2-0040-Silicon-Hisilicon-setup-Support-SMMU-switch.patch b/v2/v2-0040-Silicon-Hisilicon-setup-Support-SMMU-switch.patch
new file mode 100644
index 0000000000..51531065c6
--- /dev/null
+++ b/v2/v2-0040-Silicon-Hisilicon-setup-Support-SMMU-switch.patch
@@ -0,0 +1,124 @@
+From 2949491100ccf6f14ce41f0f9a113900f086cc9b Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Mon, 23 Jul 2018 18:29:58 +0800
+Subject: [PATCH edk2-platforms v2 40/43] Silicon/Hisilicon/setup: Support SMMU
+ switch
+
+Select without SMMU iort while SMMU item is disable,
+Select with SMMU iort while SMMU item is enable.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c | 88 ++++++++++++++++++++
+ 1 file changed, 88 insertions(+)
+
+diff --git a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+index 32878ca4f9..e0c29e0f57 100644
+--- a/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
++++ b/Silicon/Hisilicon/Drivers/HisiAcpiPlatformDxe/UpdateAcpiTable.c
+@@ -24,6 +24,90 @@
+ 
+ #define CORECOUNT(X) ((X) * CORE_NUM_PER_SOCKET)
+ 
++#define FIELD_IORT_NODE_OFFSET     40
++
++typedef enum {
++  NodeTypeIts = 0,
++  NodeTypeNameComponent,
++  NodeTypePciRC,
++  NodeTypeSmmuV1,
++  NodeTypeSmmuV3,
++  NodeTypePMCG
++} IORT_NODE_TYPE;
++
++#pragma pack(1)
++typedef struct {
++  UINT8   Type;
++  UINT16  Length;
++  UINT8   Revision;
++  UINT32  Reserved;
++  UINT32  IdMapNumber;
++  UINT32  IdArrayOffset;
++} IORT_NODE_HEAD;
++#pragma pack()
++
++BOOLEAN
++IsIortWithSmmu (
++  IN EFI_ACPI_DESCRIPTION_HEADER      *TableHeader
++  )
++{
++  UINT32           *NodeOffset;
++  UINT32           NextOffset;
++  IORT_NODE_HEAD   *Node;
++
++  NodeOffset = (UINT32 *)((UINT8 *)TableHeader + FIELD_IORT_NODE_OFFSET);
++  NextOffset = *NodeOffset;
++
++  while (NextOffset < TableHeader->Length) {
++    Node = (IORT_NODE_HEAD *)((UINT8 *)TableHeader + NextOffset);
++    NextOffset += Node->Length;
++
++    if ((Node->Type == NodeTypeSmmuV1) || (Node->Type == NodeTypeSmmuV3)) {
++      return TRUE;
++    }
++  }
++
++  return FALSE;
++}
++
++EFI_STATUS
++SelectIort (
++  IN EFI_ACPI_DESCRIPTION_HEADER      *TableHeader
++  )
++{
++  EFI_STATUS          Status;
++  UINTN               Size;
++  OEM_CONFIG_DATA     Configuration;
++
++  Configuration.EnableSmmu = 0;
++  Size = sizeof (OEM_CONFIG_DATA);
++  Status = gRT->GetVariable (
++                  OEM_CONFIG_NAME,
++                  &gOemConfigGuid,
++                  NULL,
++                  &Size,
++                  &Configuration
++                  );
++  if (EFI_ERROR (Status)) {
++    DEBUG ((DEBUG_ERROR, "Get OemConfig variable (%r).\n", Status));
++  }
++
++  Status =  EFI_SUCCESS;
++  if (IsIortWithSmmu (TableHeader)) {
++    if (!Configuration.EnableSmmu) {
++      Status = EFI_ABORTED;
++    }
++  } else {
++    if (Configuration.EnableSmmu) {
++      Status = EFI_ABORTED;
++    }
++  }
++  DEBUG ((DEBUG_INFO, "SmmuEnable=%x, return %r for Iort table.\n",
++          Configuration.EnableSmmu, Status));
++
++  return Status;
++}
++
+ STATIC
+ VOID
+ RemoveUnusedMemoryNode (
+@@ -151,6 +235,10 @@ UpdateAcpiTable (
+   case EFI_ACPI_6_0_SYSTEM_LOCALITY_INFORMATION_TABLE_SIGNATURE:
+     Status = UpdateSlit (TableHeader);
+     break;
++
++  case EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE:
++    Status = SelectIort (TableHeader);
++    break;
+   case EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE:
+     Status = IsNeedSpcr (TableHeader);
+     break;
+-- 
+2.17.0
+
diff --git a/v2/v2-0041-Hisilicon-D06-Add-PciPlatformLib.patch b/v2/v2-0041-Hisilicon-D06-Add-PciPlatformLib.patch
new file mode 100644
index 0000000000..f4c97edb77
--- /dev/null
+++ b/v2/v2-0041-Hisilicon-D06-Add-PciPlatformLib.patch
@@ -0,0 +1,141 @@
+From c3a91d2d249e890454c6c23c893eedf68869457b Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Mon, 23 Jul 2018 20:19:29 +0800
+Subject: [PATCH edk2-platforms v2 41/43] Hisilicon/D06: Add PciPlatformLib
+
+Add a Null PciPlatformLib for build D06. The switch generic
+PciHostBridge patch set add two api for PciPlatform driver,
+so need to implement the two api for D06.
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D06/D06.dsc                                                 |  1 +
+ Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf | 30 +++++++++
+ Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c   | 67 ++++++++++++++++++++
+ 3 files changed, 98 insertions(+)
+
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index fad6fcc747..053ea894d5 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -95,6 +95,7 @@
+   FileExplorerLib|MdeModulePkg/Library/FileExplorerLib/FileExplorerLib.inf
+ !endif
+   PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
++  PciPlatformLib|Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf
+ 
+ [LibraryClasses.common.SEC]
+   ArmPlatformLib|Silicon/Hisilicon/Library/ArmPlatformLibHisilicon/ArmPlatformLibSec.inf
+diff --git a/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf b/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf
+new file mode 100644
+index 0000000000..7648322522
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.inf
+@@ -0,0 +1,30 @@
++## @file
++# PCI Segment Library for Hisilicon Hi1610/Hi1616 SoC with multiple RCs
++#
++# Copyright (c) 2007 - 2014, Intel Corporation. All rights reserved.<BR>
++# Copyright (c) 2017 - 2018, Linaro Ltd. All rights reserved.<BR>
++# Copyright (c) 2018, Hisilicon Ltd. All rights reserved.<BR>
++#
++#  This program and the accompanying materials
++#  are licensed and made available under the terms and conditions of the BSD License
++#  which accompanies this distribution. The full text of the license may be found at
++#  http://opensource.org/licenses/bsd-license.php.
++#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++#
++#
++##
++
++[Defines]
++  INF_VERSION                    = 0x0001001A
++  BASE_NAME                      = Hi1620PciPlatformLib
++  FILE_GUID                      = 29ba30da-68bc-46a5-888f-c65dabb67fd8
++  MODULE_TYPE                    = BASE
++  VERSION_STRING                 = 1.0
++  LIBRARY_CLASS                  = PciPlatformLib
++
++[Sources]
++  Hi1620PciPlatformLib.c
++
++[Packages]
++  MdePkg/MdePkg.dec
+diff --git a/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c b/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c
+new file mode 100644
+index 0000000000..ff77974c0f
+--- /dev/null
++++ b/Silicon/Hisilicon/Hi1620/Library/Hi1620PciPlatformLib/Hi1620PciPlatformLib.c
+@@ -0,0 +1,67 @@
++/** @file
++*
++*  Copyright (c) 2018, Hisilicon Limited. All rights reserved.
++*  Copyright (c) 2018, Linaro Limited. All rights reserved.
++*
++*  This program and the accompanying materials
++*  are licensed and made available under the terms and conditions of the BSD License
++*  which accompanies this distribution.  The full text of the license may be found at
++*  http://opensource.org/licenses/bsd-license.php
++*
++*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
++*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
++*
++**/
++
++#include <Uefi.h>
++#include <Protocol/PciPlatform.h>
++
++
++/*++
++
++Routine Description:
++
++  Perform Platform initialization first in PciPlatform.
++
++Arguments:
++
++Returns:
++
++ VOID.
++
++--*/
++VOID
++EFIAPI
++PciInitPlatform (
++  VOID
++  )
++{
++  return;
++}
++
++/*++
++
++Routine Description:
++
++  Perform Platform initialization by the phase indicated.
++
++Arguments:
++
++  HostBridge    -  The associated PCI host bridge handle.
++  Phase         -  The phase of the PCI controller enumeration.
++  ChipsetPhase  -  Defines the execution phase of the PCI chipset driver.
++
++Returns:
++
++--*/
++VOID
++EFIAPI
++PhaseNotifyPlatform (
++  IN  EFI_HANDLE                                     HostBridge,
++  IN  EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PHASE  Phase,
++  IN  EFI_PCI_CHIPSET_EXECUTION_PHASE                ChipsetPhase
++  )
++{
++  return;
++}
++
+-- 
+2.17.0
+
diff --git a/v2/v2-0042-Hisilicon-D06-Add-edk2-non-osi-Shell-components.patch b/v2/v2-0042-Hisilicon-D06-Add-edk2-non-osi-Shell-components.patch
new file mode 100644
index 0000000000..ef247d1c85
--- /dev/null
+++ b/v2/v2-0042-Hisilicon-D06-Add-edk2-non-osi-Shell-components.patch
@@ -0,0 +1,74 @@
+From 8e0cf8078ead0303eea264393a4cd011b54649ad Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Mon, 30 Jul 2018 14:53:19 +0800
+Subject: [PATCH edk2-platforms v2 42/43] Hisilicon/D06: Add edk2-non-osi Shell
+ components
+
+Add Hisilicon Oem Shell libraries for some commands,such as
+biosupdate, getmac, setmac, provision, acpistartos, brdinfo,
+sfpinfo.
+
+biosupdate example:
+ifconfig -s eth2 static 192.168.2.68 255.255.255.0 192.168.2.1
+biosupdate serverIp -u user -p password -f D06.fd -m master
+
+acpistartos example:
+ifconfig -s eth2 static 192.168.2.69 255.255.255.0 192.168.2.1
+provision serverIp -u user -p password -f os\Image -a 0x80000
+2
+provision serverIp -u user -p password -f os\minifs.cpio.gz -a 0x07000000
+2
+acpistartos
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Silicon/Hisilicon/HisiPkg.dec  | 4 ++++
+ Platform/Hisilicon/D06/D06.dsc | 2 ++
+ 2 files changed, 6 insertions(+)
+
+diff --git a/Silicon/Hisilicon/HisiPkg.dec b/Silicon/Hisilicon/HisiPkg.dec
+index 858b840a57..010d501914 100644
+--- a/Silicon/Hisilicon/HisiPkg.dec
++++ b/Silicon/Hisilicon/HisiPkg.dec
+@@ -39,6 +39,7 @@
+   gPlatformSasProtocolGuid = {0x40e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x5d}}
+   gHisiPlatformSasProtocolGuid = {0x20e9829f, 0x3a2c, 0x479a, {0x9a, 0x93, 0x45, 0x7d, 0x13, 0x50, 0x96, 0x6d}}
+   gHisiSnpPlatformProtocolGuid = {0x81321f27, 0xff58, 0x4a1d, {0x99, 0x97, 0xd, 0xcc, 0xfa, 0x82, 0xf4, 0x6f}}
++  gOemNicProtocolGuid = {0xb5903955, 0x31e9, 0x4aaf, {0xb2, 0x83, 0x7, 0x9f, 0x3c, 0xc4, 0x71, 0x66}}
+ 
+ [Guids]
+   gHisiTokenSpaceGuid = {0xc8bc553e, 0x12bf, 0x11e6, {0x97, 0x4f, 0x87, 0xf7, 0x7c, 0xfd, 0x52, 0x1d}}
+@@ -49,6 +50,8 @@
+   gHisiOemVariableGuid = {0xac62b9a5, 0x9939, 0x41d3, {0xff, 0x5c, 0xc5, 0x80, 0x32, 0x7d, 0x9b, 0x29}}
+   gOemBootVariableGuid = {0xb7784577, 0x5aaf, 0x4557, {0xa1, 0x99, 0xd4, 0xa4, 0x2f, 0x45, 0x06, 0xf8}}
+   gEfiHisiSocControllerGuid = {0xee369cc3, 0xa743, 0x5382, {0x75, 0x64, 0x53, 0xe4, 0x31, 0x19, 0x38, 0x35}}
++  HisiShellSampleHiiGuid  = { 0x43859314, 0x82c1, 0x4592, { 0x8f, 0xf7, 0xc1, 0xbd, 0xf3, 0xb2, 0x0e, 0xd5 }}
++  HisiPlatformShellSampleHiiGuid = { 0x7924a5de, 0xc600, 0x40d5, { 0x91, 0x10, 0xf9, 0xc3, 0xe7, 0x25, 0x4d, 0x33 }}
+ 
+ [LibraryClasses]
+   PlatformSysCtrlLib|Include/Library/PlatformSysCtrlLib.h
+@@ -101,6 +104,7 @@
+   gHisiTokenSpaceGuid.PcdSlotPerChannelNum|0x0|UINT32|0x40000004
+ 
+   gHisiTokenSpaceGuid.PcdShellFile|{ 0x83, 0xA5, 0x04, 0x7C, 0x3E, 0x9E, 0x1C, 0x4F, 0xAD, 0x65, 0xE0, 0x52, 0x68, 0xD0, 0xB4, 0xD1 }|VOID*|0x30006554
++  gHisiTokenSpaceGuid.PcdStartOsParameter|L""|VOID*|0x5000000
+ 
+   #FDT File Address
+   gHisiTokenSpaceGuid.FdtFileAddress|0x0|UINT64|0x40000005
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 053ea894d5..544039e450 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -473,6 +473,8 @@
+ !if $(INCLUDE_DP) == TRUE
+       NULL|ShellPkg/Library/UefiDpLib/UefiDpLib.inf
+ !endif #$(INCLUDE_DP)
++      NULL|Silicon/Hisilicon/Library/HisiShellCmdLib/HisiShellCmdLib.inf
++      NULL|Silicon/Hisilicon/Hi1620/Library/HisiD06ShellCmdLib/HisiD06ShellCmdLib.inf
+ 
+     <PcdsFixedAtBuild>
+       gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0xFF
+-- 
+2.17.0
+
diff --git a/v2/v2-0043-Platform-Hisilicon-D0x-Update-version-string-to-1.patch b/v2/v2-0043-Platform-Hisilicon-D0x-Update-version-string-to-1.patch
new file mode 100644
index 0000000000..d42926a182
--- /dev/null
+++ b/v2/v2-0043-Platform-Hisilicon-D0x-Update-version-string-to-1.patch
@@ -0,0 +1,62 @@
+From 7181548f40616d5086dba15cc557703e517e9c50 Mon Sep 17 00:00:00 2001
+From: Ming Huang <ming.huang@linaro.org>
+Date: Tue, 24 Jul 2018 14:42:33 +0800
+Subject: [PATCH edk2-platforms v2 43/43] Platform/Hisilicon/D0x: Update
+ version string to 18.08
+
+Contributed-under: TianoCore Contribution Agreement 1.1
+Signed-off-by: Ming Huang <ming.huang@linaro.org>
+---
+ Platform/Hisilicon/D03/D03.dsc | 2 +-
+ Platform/Hisilicon/D05/D05.dsc | 2 +-
+ Platform/Hisilicon/D06/D06.dsc | 4 ++--
+ 3 files changed, 4 insertions(+), 4 deletions(-)
+
+diff --git a/Platform/Hisilicon/D03/D03.dsc b/Platform/Hisilicon/D03/D03.dsc
+index c12790ba59..add15b7f93 100644
+--- a/Platform/Hisilicon/D03/D03.dsc
++++ b/Platform/Hisilicon/D03/D03.dsc
+@@ -174,7 +174,7 @@
+   !ifdef $(FIRMWARE_VER)
+     gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+   !else
+-    gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 18.02 for Hisilicon D03"
++    gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 18.08 for Hisilicon D03"
+   !endif
+ 
+   gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
+diff --git a/Platform/Hisilicon/D05/D05.dsc b/Platform/Hisilicon/D05/D05.dsc
+index 94d386582e..76c0bd421e 100644
+--- a/Platform/Hisilicon/D05/D05.dsc
++++ b/Platform/Hisilicon/D05/D05.dsc
+@@ -192,7 +192,7 @@
+   !ifdef $(FIRMWARE_VER)
+     gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+   !else
+-    gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 18.02 for Hisilicon D05"
++    gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 18.08 for Hisilicon D05"
+   !endif
+ 
+   gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
+diff --git a/Platform/Hisilicon/D06/D06.dsc b/Platform/Hisilicon/D06/D06.dsc
+index 544039e450..09197922ad 100644
+--- a/Platform/Hisilicon/D06/D06.dsc
++++ b/Platform/Hisilicon/D06/D06.dsc
+@@ -165,12 +165,12 @@
+   !ifdef $(FIRMWARE_VER)
+     gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"$(FIRMWARE_VER)"
+   !else
+-    gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Hisilicon D06 UEFI RC0 - B308 (V0.38)"
++    gEfiMdeModulePkgTokenSpaceGuid.PcdFirmwareVersionString|L"Development build 18.08 for Hisilicon D06"
+   !endif
+ 
+   gHisiTokenSpaceGuid.PcdBiosVersionString|L"10.01.01T18"
+ 
+-  gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"0.38"
++  gHisiTokenSpaceGuid.PcdBiosVersionForBmc|L"0.42"
+ 
+   gHisiTokenSpaceGuid.PcdSystemProductName|L"D06"
+   gHisiTokenSpaceGuid.PcdSystemVersion|L"VER.A"
+-- 
+2.17.0
+
