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([185.25.64.249]) by mx.google.com with ESMTPSA id k41sm5521285eey.0.2014.01.24.08.43.46 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 24 Jan 2014 08:43:46 -0800 (PST) From: Julien Grall To: xen-devel@lists.xenproject.org Cc: patches@linaro.org, ian.campbell@citrix.com, tim@xen.org, stefano.stabellini@citrix.com, Julien Grall Subject: [PATCH for-4.5 1/8] xen/arm: irq: move gic {, un}lock in gic_set_irq_properties Date: Fri, 24 Jan 2014 16:43:35 +0000 Message-Id: <1390581822-32624-2-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1390581822-32624-1-git-send-email-julien.grall@linaro.org> References: <1390581822-32624-1-git-send-email-julien.grall@linaro.org> X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.173 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Precedence: list Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org List-ID: X-Google-Group-Id: 836684582541 List-Post: , List-Help: , List-Archive: List-Unsubscribe: , The function gic_set_irq_properties is only called in two places: - gic_route_irq: the gic.lock is only taken for the call to the former function. - gic_route_irq_to_guest: the gic.lock is taken for the duration of the function. But the lock is only useful when gic_set_irq_properties. So we can safely move the lock in gic_set_irq_properties and restrict the critical section for the gic.lock in gic_route_irq_to_guest. Signed-off-by: Julien Grall Acked-by: Ian Campbell --- xen/arch/arm/gic.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index e6257a7..1943f92 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -228,7 +228,11 @@ static void gic_set_irq_properties(unsigned int irq, bool_t level, { volatile unsigned char *bytereg; uint32_t cfg, edgebit; - unsigned int mask = gic_cpu_mask(cpu_mask); + unsigned int mask; + + spin_lock(&gic.lock); + + mask = gic_cpu_mask(cpu_mask); /* Set edge / level */ cfg = GICD[GICD_ICFGR + irq / 16]; @@ -247,6 +251,7 @@ static void gic_set_irq_properties(unsigned int irq, bool_t level, bytereg = (unsigned char *) (GICD + GICD_IPRIORITYR); bytereg[irq] = priority; + spin_unlock(&gic.lock); } /* Program the GIC to route an interrupt */ @@ -269,9 +274,7 @@ static int gic_route_irq(unsigned int irq, bool_t level, desc->handler = &gic_host_irq_type; - spin_lock(&gic.lock); gic_set_irq_properties(irq, level, cpu_mask, priority); - spin_unlock(&gic.lock); spin_unlock_irqrestore(&desc->lock, flags); return 0; @@ -769,7 +772,6 @@ int gic_route_irq_to_guest(struct domain *d, const struct dt_irq *irq, action->free_on_release = 1; spin_lock_irqsave(&desc->lock, flags); - spin_lock(&gic.lock); desc->handler = &gic_guest_irq_type; desc->status |= IRQ_GUEST; @@ -790,7 +792,6 @@ int gic_route_irq_to_guest(struct domain *d, const struct dt_irq *irq, p->desc = desc; out: - spin_unlock(&gic.lock); spin_unlock_irqrestore(&desc->lock, flags); return retval; }