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[50.57.142.19]) by mx.google.com with ESMTPS id wm4si608344vcb.79.2014.02.13.04.39.49 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Thu, 13 Feb 2014 04:39:50 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WDvYh-00026a-3w; Thu, 13 Feb 2014 12:38:27 +0000 Received: from mail6.bemta4.messagelabs.com ([85.158.143.247]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WDvYf-00025p-Of for xen-devel@lists.xen.org; Thu, 13 Feb 2014 12:38:26 +0000 Received: from [85.158.143.35:21452] by server-1.bemta-4.messagelabs.com id 08/E7-31661-1CCBCF25; Thu, 13 Feb 2014 12:38:25 +0000 X-Env-Sender: Ian.Campbell@citrix.com X-Msg-Ref: server-9.tower-21.messagelabs.com!1392295102!5414705!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 19213 invoked from network); 13 Feb 2014 12:38:23 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-9.tower-21.messagelabs.com with RC4-SHA encrypted SMTP; 13 Feb 2014 12:38:23 -0000 X-IronPort-AV: E=Sophos;i="4.95,838,1384300800"; d="scan'208";a="100426780" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 13 Feb 2014 12:38:10 +0000 Received: from norwich.cam.xci-test.com (10.80.248.129) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.2.342.4; Thu, 13 Feb 2014 07:38:09 -0500 Received: from drall.uk.xensource.com ([10.80.16.71] helo=drall.uk.xensource.com.) by norwich.cam.xci-test.com with esmtp (Exim 4.72) (envelope-from ) id 1WDvYP-0003Bw-7Y; Thu, 13 Feb 2014 12:38:09 +0000 From: Ian Campbell To: Date: Thu, 13 Feb 2014 12:38:06 +0000 Message-ID: <1392295088-24219-6-git-send-email-ian.campbell@citrix.com> X-Mailer: git-send-email 1.7.10.4 In-Reply-To: <1392295040.31985.7.camel@kazak.uk.xensource.com> References: <1392295040.31985.7.camel@kazak.uk.xensource.com> MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@linaro.org, tim@xen.org, Ian Campbell , stefano.stabellini@eu.citrix.com Subject: [Xen-devel] [PATCH for-4.5 v2 6/8] xen: arm: add scope to dsb and dmb macros X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: ian.campbell@citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Everywhere currently passes "sy"stem, so no actual change. Signed-off-by: Ian Campbell Acked-by: Stefano Stabellini Acked-by: Tim Deegan --- xen/arch/arm/domain.c | 2 +- xen/arch/arm/gic.c | 10 +++++----- xen/arch/arm/mm.c | 4 ++-- xen/arch/arm/platforms/vexpress.c | 6 +++--- xen/arch/arm/smpboot.c | 2 +- xen/arch/arm/time.c | 2 +- xen/drivers/video/arm_hdlcd.c | 2 +- xen/include/asm-arm/arm32/flushtlb.h | 16 ++++++++-------- xen/include/asm-arm/arm32/page.h | 4 ++-- xen/include/asm-arm/arm64/page.h | 4 ++-- xen/include/asm-arm/page.h | 4 ++-- xen/include/asm-arm/system.h | 16 ++++++++-------- 12 files changed, 36 insertions(+), 36 deletions(-) diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c index 8f20fdf..b27f32f 100644 --- a/xen/arch/arm/domain.c +++ b/xen/arch/arm/domain.c @@ -47,7 +47,7 @@ void idle_loop(void) local_irq_disable(); if ( cpu_is_haltable(smp_processor_id()) ) { - dsb(); + dsb(sy); wfi(); } local_irq_enable(); diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 13bbf48..1467b69 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -137,7 +137,7 @@ static void gic_irq_enable(struct irq_desc *desc) spin_lock_irqsave(&desc->lock, flags); spin_lock(&gic.lock); desc->status &= ~IRQ_DISABLED; - dsb(); + dsb(sy); /* Enable routing */ GICD[GICD_ISENABLER + irq / 32] = (1u << (irq % 32)); spin_unlock(&gic.lock); @@ -478,7 +478,7 @@ void send_SGI_mask(const cpumask_t *cpumask, enum gic_sgi sgi) cpumask_and(&online_mask, cpumask, &cpu_online_map); mask = gic_cpu_mask(&online_mask); - dsb(); + dsb(sy); GICD[GICD_SGIR] = GICD_SGI_TARGET_LIST | (mask<action = new; - dsb(); + dsb(sy); return 0; } diff --git a/xen/arch/arm/mm.c b/xen/arch/arm/mm.c index ff19e39..20dbb90 100644 --- a/xen/arch/arm/mm.c +++ b/xen/arch/arm/mm.c @@ -345,10 +345,10 @@ void flush_page_to_ram(unsigned long mfn) { void *p, *v = map_domain_page(mfn); - dsb(); /* So the CPU issues all writes to the range */ + dsb(sy); /* So the CPU issues all writes to the range */ for ( p = v; p < v + PAGE_SIZE ; p += cacheline_bytes ) asm volatile (__clean_and_invalidate_xen_dcache_one(0) : : "r" (p)); - dsb(); /* So we know the flushes happen before continuing */ + dsb(sy); /* So we know the flushes happen before continuing */ unmap_domain_page(v); } diff --git a/xen/arch/arm/platforms/vexpress.c b/xen/arch/arm/platforms/vexpress.c index 6132056..8e6a4ea 100644 --- a/xen/arch/arm/platforms/vexpress.c +++ b/xen/arch/arm/platforms/vexpress.c @@ -48,7 +48,7 @@ static inline int vexpress_ctrl_start(uint32_t *syscfg, int write, /* wait for complete flag to be set */ do { stat = syscfg[V2M_SYS_CFGSTAT/4]; - dsb(); + dsb(sy); } while ( !(stat & V2M_SYS_CFG_COMPLETE) ); /* check error status and return error flag if set */ @@ -113,10 +113,10 @@ static void vexpress_reset(void) /* switch to slow mode */ writel(0x3, sp810); - dsb(); isb(); + dsb(sy); isb(); /* writing any value to SCSYSSTAT reg will reset the system */ writel(0x1, sp810 + 4); - dsb(); isb(); + dsb(sy); isb(); iounmap(sp810); } diff --git a/xen/arch/arm/smpboot.c b/xen/arch/arm/smpboot.c index ce68d34..7f28b68 100644 --- a/xen/arch/arm/smpboot.c +++ b/xen/arch/arm/smpboot.c @@ -341,7 +341,7 @@ void stop_cpu(void) local_irq_disable(); cpu_is_dead = 1; /* Make sure the write happens before we sleep forever */ - dsb(); + dsb(sy); isb(); while ( 1 ) wfi(); diff --git a/xen/arch/arm/time.c b/xen/arch/arm/time.c index 81e3e28..93d957a 100644 --- a/xen/arch/arm/time.c +++ b/xen/arch/arm/time.c @@ -260,7 +260,7 @@ void udelay(unsigned long usecs) s_time_t deadline = get_s_time() + 1000 * (s_time_t) usecs; while ( get_s_time() - deadline < 0 ) ; - dsb(); + dsb(sy); isb(); } diff --git a/xen/drivers/video/arm_hdlcd.c b/xen/drivers/video/arm_hdlcd.c index 647f22c..e5ad18d 100644 --- a/xen/drivers/video/arm_hdlcd.c +++ b/xen/drivers/video/arm_hdlcd.c @@ -78,7 +78,7 @@ void (*video_puts)(const char *) = vga_noop_puts; static void hdlcd_flush(void) { - dsb(); + dsb(sy); } static int __init get_color_masks(const char* bpp, struct color_masks **masks) diff --git a/xen/include/asm-arm/arm32/flushtlb.h b/xen/include/asm-arm/arm32/flushtlb.h index 7183a07..bbcc82f 100644 --- a/xen/include/asm-arm/arm32/flushtlb.h +++ b/xen/include/asm-arm/arm32/flushtlb.h @@ -4,44 +4,44 @@ /* Flush local TLBs, current VMID only */ static inline void flush_tlb_local(void) { - dsb(); + dsb(sy); WRITE_CP32((uint32_t) 0, TLBIALL); - dsb(); + dsb(sy); isb(); } /* Flush inner shareable TLBs, current VMID only */ static inline void flush_tlb(void) { - dsb(); + dsb(sy); WRITE_CP32((uint32_t) 0, TLBIALLIS); - dsb(); + dsb(sy); isb(); } /* Flush local TLBs, all VMIDs, non-hypervisor mode */ static inline void flush_tlb_all_local(void) { - dsb(); + dsb(sy); WRITE_CP32((uint32_t) 0, TLBIALLNSNH); - dsb(); + dsb(sy); isb(); } /* Flush innershareable TLBs, all VMIDs, non-hypervisor mode */ static inline void flush_tlb_all(void) { - dsb(); + dsb(sy); WRITE_CP32((uint32_t) 0, TLBIALLNSNHIS); - dsb(); + dsb(sy); isb(); } diff --git a/xen/include/asm-arm/arm32/page.h b/xen/include/asm-arm/arm32/page.h index b8221ca..191a108 100644 --- a/xen/include/asm-arm/arm32/page.h +++ b/xen/include/asm-arm/arm32/page.h @@ -67,13 +67,13 @@ static inline void flush_xen_data_tlb(void) static inline void flush_xen_data_tlb_range_va(unsigned long va, unsigned long size) { unsigned long end = va + size; - dsb(); /* Ensure preceding are visible */ + dsb(sy); /* Ensure preceding are visible */ while ( va < end ) { asm volatile(STORE_CP32(0, TLBIMVAH) : : "r" (va) : "memory"); va += PAGE_SIZE; } - dsb(); /* Ensure completion of the TLB flush */ + dsb(sy); /* Ensure completion of the TLB flush */ isb(); } diff --git a/xen/include/asm-arm/arm64/page.h b/xen/include/asm-arm/arm64/page.h index 3352821..20b4c5a 100644 --- a/xen/include/asm-arm/arm64/page.h +++ b/xen/include/asm-arm/arm64/page.h @@ -60,13 +60,13 @@ static inline void flush_xen_data_tlb(void) static inline void flush_xen_data_tlb_range_va(unsigned long va, unsigned long size) { unsigned long end = va + size; - dsb(); /* Ensure preceding are visible */ + dsb(sy); /* Ensure preceding are visible */ while ( va < end ) { asm volatile("tlbi vae2, %0;" : : "r" (va>>PAGE_SHIFT) : "memory"); va += PAGE_SIZE; } - dsb(); /* Ensure completion of the TLB flush */ + dsb(sy); /* Ensure completion of the TLB flush */ isb(); } diff --git a/xen/include/asm-arm/page.h b/xen/include/asm-arm/page.h index 6dc7fa6..5e4678e 100644 --- a/xen/include/asm-arm/page.h +++ b/xen/include/asm-arm/page.h @@ -263,10 +263,10 @@ extern size_t cacheline_bytes; static inline void clean_xen_dcache_va_range(void *p, unsigned long size) { void *end; - dsb(); /* So the CPU issues all writes to the range */ + dsb(sy); /* So the CPU issues all writes to the range */ for ( end = p + size; p < end; p += cacheline_bytes ) asm volatile (__clean_xen_dcache_one(0) : : "r" (p)); - dsb(); /* So we know the flushes happen before continuing */ + dsb(sy); /* So we know the flushes happen before continuing */ } /* Macro for flushing a single small item. The predicate is always diff --git a/xen/include/asm-arm/system.h b/xen/include/asm-arm/system.h index 89c61ef..e1f126a 100644 --- a/xen/include/asm-arm/system.h +++ b/xen/include/asm-arm/system.h @@ -13,16 +13,16 @@ #define wfi() asm volatile("wfi" : : : "memory") #define isb() asm volatile("isb" : : : "memory") -#define dsb() asm volatile("dsb sy" : : : "memory") -#define dmb() asm volatile("dmb sy" : : : "memory") +#define dsb(scope) asm volatile("dsb " #scope : : : "memory") +#define dmb(scope) asm volatile("dmb " #scope : : : "memory") -#define mb() dsb() -#define rmb() dsb() -#define wmb() dsb() +#define mb() dsb(sy) +#define rmb() dsb(sy) +#define wmb() dsb(sy) -#define smp_mb() dmb() -#define smp_rmb() dmb() -#define smp_wmb() dmb() +#define smp_mb() dmb(sy) +#define smp_rmb() dmb(sy) +#define smp_wmb() dmb(sy) #define xchg(ptr,x) \ ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))