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[50.57.142.19]) by mx.google.com with ESMTPS id y3si4059111qas.156.2014.02.14.07.53.19 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 14 Feb 2014 07:53:20 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WEL3w-00082z-2F; Fri, 14 Feb 2014 15:52:24 +0000 Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WEL3t-00080B-VI for xen-devel@lists.xensource.com; Fri, 14 Feb 2014 15:52:22 +0000 Received: from [85.158.137.68:63338] by server-8.bemta-3.messagelabs.com id FB/40-16039-5BB3EF25; Fri, 14 Feb 2014 15:52:21 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-5.tower-31.messagelabs.com!1392393138!691212!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6608 invoked from network); 14 Feb 2014 15:52:20 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-5.tower-31.messagelabs.com with RC4-SHA encrypted SMTP; 14 Feb 2014 15:52:20 -0000 X-IronPort-AV: E=Sophos;i="4.95,845,1384300800"; d="scan'208";a="100823982" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 14 Feb 2014 15:51:46 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.2.342.4; Fri, 14 Feb 2014 10:51:45 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WEL3E-0004ww-Cv; Fri, 14 Feb 2014 15:51:40 +0000 From: Stefano Stabellini To: Date: Fri, 14 Feb 2014 15:51:30 +0000 Message-ID: <1392393098-7351-2-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA2 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH-4.5 v2 02/10] xen/arm: support HW interrupts in gic_set_lr X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.176 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: If the irq to be injected is an hardware irq (p->desc != NULL), set GICH_LR_HW. Remove the code to EOI a physical interrupt on behalf of the guest because it has become unnecessary. Also add a struct vcpu* parameter to gic_set_lr. Signed-off-by: Stefano Stabellini --- Changes in v2: - remove the EOI code, now unnecessary; - do not assume physical IRQ == virtual IRQ; - refactor gic_set_lr. --- xen/arch/arm/gic.c | 52 +++++++++++++++++----------------------------------- 1 file changed, 17 insertions(+), 35 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index acf7195..64c8aa7 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -618,20 +618,24 @@ int __init setup_dt_irq(const struct dt_irq *irq, struct irqaction *new) return rc; } -static inline void gic_set_lr(int lr, unsigned int virtual_irq, +static inline void gic_set_lr(struct vcpu *v, int lr, unsigned int irq, unsigned int state, unsigned int priority) { - int maintenance_int = GICH_LR_MAINTENANCE_IRQ; - struct pending_irq *p = irq_to_pending(current, virtual_irq); + struct pending_irq *p = irq_to_pending(v, irq); + uint32_t lr_reg; BUG_ON(lr >= nr_lrs); BUG_ON(lr < 0); BUG_ON(state & ~(GICH_LR_STATE_MASK<> 3) << GICH_LR_PRIORITY_SHIFT) | - ((virtual_irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT); + ((irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT); + if ( p->desc != NULL ) + lr_reg |= GICH_LR_HW | + ((p->desc->irq & GICH_LR_PHYSICAL_MASK) << GICH_LR_PHYSICAL_SHIFT); + + GICH[GICH_LR + lr] = lr_reg; set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); clear_bit(GIC_IRQ_GUEST_PENDING, &p->status); @@ -666,7 +670,7 @@ void gic_remove_from_queues(struct vcpu *v, unsigned int virtual_irq) spin_unlock(&gic.lock); } -void gic_set_guest_irq(struct vcpu *v, unsigned int virtual_irq, +void gic_set_guest_irq(struct vcpu *v, unsigned int irq, unsigned int state, unsigned int priority) { int i; @@ -679,12 +683,12 @@ void gic_set_guest_irq(struct vcpu *v, unsigned int virtual_irq, i = find_first_zero_bit(&this_cpu(lr_mask), nr_lrs); if (i < nr_lrs) { set_bit(i, &this_cpu(lr_mask)); - gic_set_lr(i, virtual_irq, state, priority); + gic_set_lr(v, i, irq, state, priority); goto out; } } - gic_add_to_lr_pending(v, virtual_irq, priority); + gic_add_to_lr_pending(v, irq, priority); out: spin_unlock_irqrestore(&gic.lock, flags); @@ -703,7 +707,7 @@ static void gic_restore_pending_irqs(struct vcpu *v) if ( i >= nr_lrs ) return; spin_lock_irqsave(&gic.lock, flags); - gic_set_lr(i, p->irq, GICH_LR_PENDING, p->priority); + gic_set_lr(v, i, p->irq, GICH_LR_PENDING, p->priority); list_del_init(&p->lr_queue); set_bit(i, &this_cpu(lr_mask)); spin_unlock_irqrestore(&gic.lock, flags); @@ -904,15 +908,9 @@ int gicv_setup(struct domain *d) } -static void gic_irq_eoi(void *info) -{ - int virq = (uintptr_t) info; - GICC[GICC_DIR] = virq; -} - static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) { - int i = 0, virq, pirq = -1; + int i = 0, virq; uint32_t lr; struct vcpu *v = current; uint64_t eisr = GICH[GICH_EISR0] | (((uint64_t) GICH[GICH_EISR1]) << 32); @@ -920,10 +918,8 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r while ((i = find_next_bit((const long unsigned int *) &eisr, 64, i)) < 64) { struct pending_irq *p, *p2; - int cpu; bool_t inflight; - cpu = -1; inflight = 0; spin_lock_irq(&gic.lock); @@ -933,12 +929,8 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r clear_bit(i, &this_cpu(lr_mask)); p = irq_to_pending(v, virq); - if ( p->desc != NULL ) { + if ( p->desc != NULL ) p->desc->status &= ~IRQ_INPROGRESS; - /* Assume only one pcpu needs to EOI the irq */ - cpu = p->desc->arch.eoi_cpu; - pirq = p->desc->irq; - } if ( test_bit(GIC_IRQ_GUEST_PENDING, &p->status) && test_bit(GIC_IRQ_GUEST_ENABLED, &p->status)) { @@ -950,7 +942,7 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r if ( !list_empty(&v->arch.vgic.lr_pending) ) { p2 = list_entry(v->arch.vgic.lr_pending.next, typeof(*p2), lr_queue); - gic_set_lr(i, p2->irq, GICH_LR_PENDING, p2->priority); + gic_set_lr(v, i, p2->irq, GICH_LR_PENDING, p2->priority); list_del_init(&p2->lr_queue); set_bit(i, &this_cpu(lr_mask)); } @@ -963,16 +955,6 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r spin_unlock_irq(&v->arch.vgic.lock); } - if ( p->desc != NULL ) { - /* this is not racy because we can't receive another irq of the - * same type until we EOI it. */ - if ( cpu == smp_processor_id() ) - gic_irq_eoi((void*)(uintptr_t)pirq); - else - on_selected_cpus(cpumask_of(cpu), - gic_irq_eoi, (void*)(uintptr_t)pirq, 0); - } - i++; } }