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[50.57.142.19]) by mx.google.com with ESMTPS id c2si2046063vct.67.2014.02.14.07.53.51 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 14 Feb 2014 07:53:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WEL3U-0007sw-PP; Fri, 14 Feb 2014 15:51:56 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WEL3S-0007ra-LP for xen-devel@lists.xensource.com; Fri, 14 Feb 2014 15:51:54 +0000 Received: from [193.109.254.147:31507] by server-12.bemta-14.messagelabs.com id 9F/29-17220-A9B3EF25; Fri, 14 Feb 2014 15:51:54 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1392393110!4409914!4 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6926 invoked from network); 14 Feb 2014 15:51:53 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-14.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 14 Feb 2014 15:51:53 -0000 X-IronPort-AV: E=Sophos;i="4.95,845,1384300800"; d="scan'208";a="102595723" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 14 Feb 2014 15:51:47 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.2.342.4; Fri, 14 Feb 2014 10:51:46 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WEL3E-0004ww-HP; Fri, 14 Feb 2014 15:51:40 +0000 From: Stefano Stabellini To: Date: Fri, 14 Feb 2014 15:51:34 +0000 Message-ID: <1392393098-7351-6-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH-4.5 v2 06/10] xen/arm: second irq injection while the first irq is still inflight X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.177 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Set GICH_LR_PENDING in the corresponding GICH_LR to inject a second irq while the first one is still active. If the first irq is already pending (not active), just clear GIC_IRQ_GUEST_PENDING because the irq has already been injected and is already visible by the guest. If the irq has already been EOI'ed then just clear the GICH_LR right away and move the interrupt to lr_pending so that it is going to be reinjected by gic_restore_pending_irqs on return to guest. If the target cpu is not the current cpu, then set GIC_IRQ_GUEST_PENDING and send an SGI. The target cpu is going to be interrupted and call gic_clear_lrs, that is going to take the same actions. Do not call vgic_vcpu_inject_irq from gic_inject if evtchn_upcall_pending is set. If we remove that call, we don't need to special case evtchn_irq in vgic_vcpu_inject_irq anymore. We also need to force the first injection of evtchn_irq (call gic_vcpu_inject_irq) from vgic_enable_irqs because evtchn_upcall_pending is already set by common code on vcpu creation. Signed-off-by: Stefano Stabellini --- xen/arch/arm/gic.c | 82 +++++++++++++++++++++++++-------------------- xen/arch/arm/vgic.c | 18 +++++++--- xen/include/asm-arm/gic.h | 1 + 3 files changed, 61 insertions(+), 40 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 5fca5be..0955d48 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -698,51 +698,64 @@ out: return; } -static void gic_clear_lrs(struct vcpu *v) +static void _gic_clear_lr(struct vcpu *v, int i) { - struct pending_irq *p; - int i = 0, irq; + int irq; uint32_t lr; - bool_t inflight; + struct pending_irq *p; ASSERT(!local_irq_is_enabled()); - while ((i = find_next_bit((const long unsigned int *) &this_cpu(lr_mask), - nr_lrs, i)) < nr_lrs) { - lr = GICH[GICH_LR + i]; - if ( !(lr & (GICH_LR_PENDING|GICH_LR_ACTIVE)) ) + lr = GICH[GICH_LR + i]; + irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK; + p = irq_to_pending(v, irq); + if ( lr & GICH_LR_ACTIVE ) + { + if ( test_bit(GIC_IRQ_GUEST_ENABLED, &p->status) && + test_and_clear_bit(GIC_IRQ_GUEST_PENDING, &p->status) ) + GICH[GICH_LR + i] = lr | GICH_LR_PENDING; + } else if ( lr & GICH_LR_PENDING ) { + clear_bit(GIC_IRQ_GUEST_PENDING, &p->status); + } else { + spin_lock(&gic.lock); + + GICH[GICH_LR + i] = 0; + clear_bit(i, &this_cpu(lr_mask)); + + if ( p->desc != NULL ) + p->desc->status &= ~IRQ_INPROGRESS; + clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); + p->lr = nr_lrs; + if ( test_bit(GIC_IRQ_GUEST_PENDING, &p->status) && + test_bit(GIC_IRQ_GUEST_ENABLED, &p->status)) { - inflight = 0; - GICH[GICH_LR + i] = 0; - clear_bit(i, &this_cpu(lr_mask)); - - irq = (lr >> GICH_LR_VIRTUAL_SHIFT) & GICH_LR_VIRTUAL_MASK; - spin_lock(&gic.lock); - p = irq_to_pending(v, irq); - if ( p->desc != NULL ) - p->desc->status &= ~IRQ_INPROGRESS; - clear_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); - p->lr = nr_lrs; - if ( test_bit(GIC_IRQ_GUEST_PENDING, &p->status) && - test_bit(GIC_IRQ_GUEST_ENABLED, &p->status)) - { - inflight = 1; - gic_add_to_lr_pending(v, irq, p->priority); - } - spin_unlock(&gic.lock); - if ( !inflight ) - { - spin_lock(&v->arch.vgic.lock); - list_del_init(&p->inflight); - spin_unlock(&v->arch.vgic.lock); - } + gic_add_to_lr_pending(v, irq, p->priority); + } else + list_del_init(&p->inflight); - } + spin_unlock(&gic.lock); + } +} + +static void gic_clear_lrs(struct vcpu *v) +{ + int i = 0; + while ((i = find_next_bit((const long unsigned int *) &this_cpu(lr_mask), + nr_lrs, i)) < nr_lrs) { + + spin_lock(&v->arch.vgic.lock); + _gic_clear_lr(v, i); + spin_unlock(&v->arch.vgic.lock); i++; } } +void gic_set_clear_lr(struct vcpu *v, struct pending_irq *p) +{ + _gic_clear_lr(v, p->lr); +} + static void gic_restore_pending_irqs(struct vcpu *v) { int i; @@ -801,9 +814,6 @@ void gic_inject(void) { gic_clear_lrs(current); - if ( vcpu_info(current, evtchn_upcall_pending) ) - vgic_vcpu_inject_irq(current, current->domain->arch.evtchn_irq); - gic_restore_pending_irqs(current); if (!gic_events_need_delivery()) gic_inject_irq_stop(); diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index da15f4d..210ac39 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -387,7 +387,11 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) irq = i + (32 * n); p = irq_to_pending(v, irq); set_bit(GIC_IRQ_GUEST_ENABLED, &p->status); - if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + if ( irq == v->domain->arch.evtchn_irq && + vcpu_info(current, evtchn_upcall_pending) && + list_empty(&p->inflight) ) + vgic_vcpu_inject_irq(v, irq); + else if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) gic_set_guest_irq(v, irq, GICH_LR_PENDING, p->priority); if ( p->desc != NULL ) p->desc->handler->enable(p->desc); @@ -696,10 +700,16 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq) if ( !list_empty(&n->inflight) ) { - if ( (irq != current->domain->arch.evtchn_irq) || - (!test_bit(GIC_IRQ_GUEST_VISIBLE, &n->status)) ) + if ( v == current ) + { + set_bit(GIC_IRQ_GUEST_PENDING, &n->status); + gic_set_clear_lr(v, n); + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + return; + } else { set_bit(GIC_IRQ_GUEST_PENDING, &n->status); - goto out; + goto out; + } } /* vcpu offline */ diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 6fce5c2..6de0d9b 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -184,6 +184,7 @@ extern void gic_remove_from_queues(struct vcpu *v, unsigned int virtual_irq); extern int gic_route_irq_to_guest(struct domain *d, const struct dt_irq *irq, const char * devname); +extern void gic_set_clear_lr(struct vcpu *v, struct pending_irq *p); /* Accept an interrupt from the GIC and dispatch its handler */ extern void gic_interrupt(struct cpu_user_regs *regs, int is_fiq);