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[50.57.142.19]) by mx.google.com with ESMTPS id uw4si2028677vdc.144.2014.02.14.07.53.54 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 14 Feb 2014 07:53:56 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WEL3S-0007rj-Qh; Fri, 14 Feb 2014 15:51:54 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WEL3R-0007rL-7P for xen-devel@lists.xensource.com; Fri, 14 Feb 2014 15:51:53 +0000 Received: from [193.109.254.147:40259] by server-7.bemta-14.messagelabs.com id 2E/73-23424-89B3EF25; Fri, 14 Feb 2014 15:51:52 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1392393110!4409914!2 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6638 invoked from network); 14 Feb 2014 15:51:51 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-14.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 14 Feb 2014 15:51:51 -0000 X-IronPort-AV: E=Sophos;i="4.95,845,1384300800"; d="scan'208";a="102595720" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 14 Feb 2014 15:51:47 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.2.342.4; Fri, 14 Feb 2014 10:51:46 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WEL3E-0004ww-Hs; Fri, 14 Feb 2014 15:51:40 +0000 From: Stefano Stabellini To: Date: Fri, 14 Feb 2014 15:51:35 +0000 Message-ID: <1392393098-7351-7-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH-4.5 v2 07/10] xen/arm: don't protect GICH and lr_queue accesses with gic.lock X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.180 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: GICH is banked, protect accesses by disabling interrupts. Protect lr_queue accesses with the vgic.lock only. gic.lock only protects accesses to GICD now. Signed-off-by: Stefano Stabellini --- xen/arch/arm/gic.c | 22 +++------------------- xen/arch/arm/vgic.c | 12 ++++++++++-- 2 files changed, 13 insertions(+), 21 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 0955d48..6386ccb 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -667,19 +667,14 @@ void gic_remove_from_queues(struct vcpu *v, unsigned int virtual_irq) { struct pending_irq *p = irq_to_pending(v, virtual_irq); - spin_lock(&gic.lock); if ( !list_empty(&p->lr_queue) ) list_del_init(&p->lr_queue); - spin_unlock(&gic.lock); } void gic_set_guest_irq(struct vcpu *v, unsigned int irq, unsigned int state, unsigned int priority) { int i; - unsigned long flags; - - spin_lock_irqsave(&gic.lock, flags); if ( v == current && list_empty(&v->arch.vgic.lr_pending) ) { @@ -687,15 +682,11 @@ void gic_set_guest_irq(struct vcpu *v, unsigned int irq, if (i < nr_lrs) { set_bit(i, &this_cpu(lr_mask)); gic_set_lr(v, i, irq, state, priority); - goto out; + return; } } gic_add_to_lr_pending(v, irq, priority); - -out: - spin_unlock_irqrestore(&gic.lock, flags); - return; } static void _gic_clear_lr(struct vcpu *v, int i) @@ -717,8 +708,6 @@ static void _gic_clear_lr(struct vcpu *v, int i) } else if ( lr & GICH_LR_PENDING ) { clear_bit(GIC_IRQ_GUEST_PENDING, &p->status); } else { - spin_lock(&gic.lock); - GICH[GICH_LR + i] = 0; clear_bit(i, &this_cpu(lr_mask)); @@ -732,8 +721,6 @@ static void _gic_clear_lr(struct vcpu *v, int i) gic_add_to_lr_pending(v, irq, p->priority); } else list_del_init(&p->inflight); - - spin_unlock(&gic.lock); } } @@ -767,11 +754,11 @@ static void gic_restore_pending_irqs(struct vcpu *v) i = find_first_zero_bit(&this_cpu(lr_mask), nr_lrs); if ( i >= nr_lrs ) return; - spin_lock_irqsave(&gic.lock, flags); + spin_lock_irqsave(&v->arch.vgic.lock, flags); gic_set_lr(v, i, p->irq, GICH_LR_PENDING, p->priority); list_del_init(&p->lr_queue); set_bit(i, &this_cpu(lr_mask)); - spin_unlock_irqrestore(&gic.lock, flags); + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); } } @@ -779,13 +766,10 @@ static void gic_restore_pending_irqs(struct vcpu *v) void gic_clear_pending_irqs(struct vcpu *v) { struct pending_irq *p, *t; - unsigned long flags; - spin_lock_irqsave(&gic.lock, flags); v->arch.lr_mask = 0; list_for_each_entry_safe ( p, t, &v->arch.vgic.lr_pending, lr_queue ) list_del_init(&p->lr_queue); - spin_unlock_irqrestore(&gic.lock, flags); } static void gic_inject_irq_start(void) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 210ac39..4bfab26 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -365,12 +365,15 @@ static void vgic_disable_irqs(struct vcpu *v, uint32_t r, int n) struct pending_irq *p; unsigned int irq; int i = 0; + unsigned long flags; while ( (i = find_next_bit((const long unsigned int *) &r, 32, i)) < 32 ) { irq = i + (32 * n); p = irq_to_pending(v, irq); + spin_lock_irqsave(&v->arch.vgic.lock, flags); clear_bit(GIC_IRQ_GUEST_ENABLED, &p->status); gic_remove_from_queues(v, irq); + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); if ( p->desc != NULL ) p->desc->handler->disable(p->desc); i++; @@ -391,8 +394,13 @@ static void vgic_enable_irqs(struct vcpu *v, uint32_t r, int n) vcpu_info(current, evtchn_upcall_pending) && list_empty(&p->inflight) ) vgic_vcpu_inject_irq(v, irq); - else if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) - gic_set_guest_irq(v, irq, GICH_LR_PENDING, p->priority); + else { + unsigned long flags; + spin_lock_irqsave(&v->arch.vgic.lock, flags); + if ( !list_empty(&p->inflight) && !test_bit(GIC_IRQ_GUEST_VISIBLE, &p->status) ) + gic_set_guest_irq(v, irq, GICH_LR_PENDING, p->priority); + spin_unlock_irqrestore(&v->arch.vgic.lock, flags); + } if ( p->desc != NULL ) p->desc->handler->enable(p->desc); i++;