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[50.57.142.19]) by mx.google.com with ESMTPS id sq4si2038093vdc.80.2014.02.14.07.53.31 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Fri, 14 Feb 2014 07:53:32 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WEL3S-0007rb-Cz; Fri, 14 Feb 2014 15:51:54 +0000 Received: from mail6.bemta14.messagelabs.com ([193.109.254.103]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WEL3Q-0007rJ-JB for xen-devel@lists.xensource.com; Fri, 14 Feb 2014 15:51:52 +0000 Received: from [193.109.254.147:40190] by server-12.bemta-14.messagelabs.com id 5D/19-17220-79B3EF25; Fri, 14 Feb 2014 15:51:51 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-14.tower-27.messagelabs.com!1392393110!4409914!1 X-Originating-IP: [66.165.176.89] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni44OSA9PiAyMDMwMDc=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 6091 invoked from network); 14 Feb 2014 15:51:51 -0000 Received: from smtp.citrix.com (HELO SMTP.CITRIX.COM) (66.165.176.89) by server-14.tower-27.messagelabs.com with RC4-SHA encrypted SMTP; 14 Feb 2014 15:51:51 -0000 X-IronPort-AV: E=Sophos;i="4.95,845,1384300800"; d="scan'208";a="102595721" Received: from accessns.citrite.net (HELO FTLPEX01CL01.citrite.net) ([10.9.154.239]) by FTLPIPO01.CITRIX.COM with ESMTP; 14 Feb 2014 15:51:47 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.78) with Microsoft SMTP Server id 14.2.342.4; Fri, 14 Feb 2014 10:51:46 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WEL3E-0004ww-Ir; Fri, 14 Feb 2014 15:51:40 +0000 From: Stefano Stabellini To: Date: Fri, 14 Feb 2014 15:51:37 +0000 Message-ID: <1392393098-7351-9-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH-4.5 v2 09/10] xen/arm: use GICH_ELSR[01] to avoid reading all the GICH_LRs in gic_clear_lrs X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.220.172 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: Read GICH_ELSR0 and GICH_ELSR1 to figure out which GICH_LR registers do not contain valid interrupts. Only call _gic_clear_lr on those. If a cpu is trying to inject an interrupt that is already inflight into another cpu, it sets GIC_IRQ_GUEST_PENDING and sends an SGI to it. The target cpu is going to be interrupted and _gic_clear_lr, called by gic_clear_lrs, will take care of setting GICH_LR_PENDING if the irq is active. In order to make sure that _gic_clear_lr is called for this irq, avoid filtering lr_mask with GICH_ELSR[01] in this case (so that in this situation we call _gic_clear_lr on all the GICH_LRs). Use a simple percpu bit, lr_clear_all, set by the sender cpu and reset by the receiver cpu, to understand whether we need to evaluate all GICH_LRs or we can filter them. Signed-off-by: Stefano Stabellini --- xen/arch/arm/gic.c | 27 ++++++++++++++++++++++----- xen/arch/arm/vgic.c | 1 + xen/include/asm-arm/gic.h | 1 + 3 files changed, 24 insertions(+), 5 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 54be9ca..b00f77c 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -55,6 +55,7 @@ static struct { static irq_desc_t irq_desc[NR_IRQS]; static DEFINE_PER_CPU(irq_desc_t[NR_LOCAL_IRQS], local_irq_desc); static DEFINE_PER_CPU(uint64_t, lr_mask); +static DEFINE_PER_CPU(uint8_t, lr_clear_all); static unsigned nr_lrs; @@ -67,7 +68,7 @@ static DEFINE_PER_CPU(u8, gic_cpu_id); /* Maximum cpu interface per GIC */ #define NR_GIC_CPU_IF 8 -static void gic_clear_lrs(struct vcpu *v); +static void gic_clear_lrs(struct vcpu *v, bool_t all); static unsigned int gic_cpu_mask(const cpumask_t *cpumask) { @@ -109,6 +110,7 @@ void gic_save_state(struct vcpu *v) v->arch.gic_lr[i] = GICH[GICH_LR + i]; v->arch.lr_mask = this_cpu(lr_mask); v->arch.gic_apr = GICH[GICH_APR]; + this_cpu(lr_clear_all) = 0ULL; /* Disable until next VCPU scheduled */ GICH[GICH_HCR] = 0; isb(); @@ -122,13 +124,14 @@ void gic_restore_state(struct vcpu *v) return; this_cpu(lr_mask) = v->arch.lr_mask; + this_cpu(lr_clear_all) = 0ULL; for ( i=0; iarch.gic_lr[i]; GICH[GICH_APR] = v->arch.gic_apr; GICH[GICH_HCR] = GICH_HCR_EN; isb(); - gic_clear_lrs(v); + gic_clear_lrs(v, 1); gic_restore_pending_irqs(v); } @@ -372,6 +375,7 @@ static void __cpuinit gic_hyp_init(void) GICH[GICH_MISR] = GICH_MISR_EOI; this_cpu(lr_mask) = 0ULL; + this_cpu(lr_clear_all) = 0ULL; } static void __cpuinit gic_hyp_disable(void) @@ -726,11 +730,19 @@ static void _gic_clear_lr(struct vcpu *v, int i, int vgic_locked) } } -static void gic_clear_lrs(struct vcpu *v) +static void gic_clear_lrs(struct vcpu *v, bool_t all) { int i = 0; + uint64_t elsr; + + if ( !all ) + { + elsr = GICH[GICH_ELSR0] | (((uint64_t) GICH[GICH_ELSR1]) << 32); + elsr &= this_cpu(lr_mask); + } else + elsr = this_cpu(lr_mask); - while ((i = find_next_bit((const long unsigned int *) &this_cpu(lr_mask), + while ((i = find_next_bit((const long unsigned int *) &elsr, nr_lrs, i)) < nr_lrs) { _gic_clear_lr(v, i, 0); @@ -743,6 +755,11 @@ void gic_set_clear_lr(struct vcpu *v, struct pending_irq *p) _gic_clear_lr(v, p->lr, 1); } +void gic_set_clear_lrs_other(struct vcpu *v) +{ + set_bit(0, &per_cpu(lr_clear_all, v->processor)); +} + static void gic_restore_pending_irqs(struct vcpu *v) { int i; @@ -796,7 +813,7 @@ int gic_events_need_delivery(void) void gic_inject(void) { - gic_clear_lrs(current); + gic_clear_lrs(current, test_and_clear_bit(0, &this_cpu(lr_clear_all))); gic_restore_pending_irqs(current); if (!gic_events_need_delivery()) diff --git a/xen/arch/arm/vgic.c b/xen/arch/arm/vgic.c index 4bfab26..02ad3cd 100644 --- a/xen/arch/arm/vgic.c +++ b/xen/arch/arm/vgic.c @@ -716,6 +716,7 @@ void vgic_vcpu_inject_irq(struct vcpu *v, unsigned int irq) return; } else { set_bit(GIC_IRQ_GUEST_PENDING, &n->status); + gic_set_clear_lrs_other(v); goto out; } } diff --git a/xen/include/asm-arm/gic.h b/xen/include/asm-arm/gic.h index 6de0d9b..8d36f7c 100644 --- a/xen/include/asm-arm/gic.h +++ b/xen/include/asm-arm/gic.h @@ -185,6 +185,7 @@ extern int gic_route_irq_to_guest(struct domain *d, const struct dt_irq *irq, const char * devname); extern void gic_set_clear_lr(struct vcpu *v, struct pending_irq *p); +extern void gic_set_clear_lrs_other(struct vcpu *v); /* Accept an interrupt from the GIC and dispatch its handler */ extern void gic_interrupt(struct cpu_user_regs *regs, int is_fiq);