From patchwork Wed Feb 26 18:39:48 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefano Stabellini X-Patchwork-Id: 25398 Return-Path: X-Original-To: linaro@patches.linaro.org Delivered-To: linaro@patches.linaro.org Received: from mail-pb0-f69.google.com (mail-pb0-f69.google.com [209.85.160.69]) by ip-10-151-82-157.ec2.internal (Postfix) with ESMTPS id 995CA203C4 for ; Wed, 26 Feb 2014 18:41:29 +0000 (UTC) Received: by mail-pb0-f69.google.com with SMTP id ma3sf3137814pbc.4 for ; Wed, 26 Feb 2014 10:41:28 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:delivered-to:from:to:date:message-id:in-reply-to :references:mime-version:cc:subject:precedence:list-id :list-unsubscribe:list-post:list-help:list-subscribe:sender :errors-to:x-original-sender:x-original-authentication-results :mailing-list:list-archive:content-type:content-transfer-encoding; bh=Q/rzpNjVb+BRojEXVTKrBjColnV1zCx/xXR0HC8q/aI=; b=YRk4KGsRPsgxwBy0egCNGm+QCH/UzTALeLZDhlQYjxbDKlLXEVdd0Q6bDLbfL0ngxn G3R+aoj2FopYp4g55TnsWpZ+bmhIkNMBLg1j3s/r0YHidA2BKji8ZRYQ7YeNCG1L+qXN HujhIT4QWUdAgEfeXOb/3sCTxd+It9whQBAGrqJRR4sLl0uf9w53QDoRPkR0thVYpuN/ Fg1I6wib4rkXkwait2L/TQ438i6McfrE3SjwoH5sJSuoukRQFkgWjJhE4kiyvWOUxQcX 8vfQYM2QKK9VMCvVdFesJm3kT2VS7DyjIGNbKcWe5uzILj14IdawARv89zCw6uM+NOIZ KcEQ== X-Gm-Message-State: ALoCoQnpxfc1z5j81OxxEYtMObDKcyljK7rkcARTdSFQ7Afk42ZDiQ355HZ29qwvWXrFzrV1cUN2 X-Received: by 10.66.231.132 with SMTP id tg4mr3849997pac.31.1393440088703; Wed, 26 Feb 2014 10:41:28 -0800 (PST) X-BeenThere: patchwork-forward@linaro.org Received: by 10.140.100.146 with SMTP id s18ls423868qge.8.gmail; Wed, 26 Feb 2014 10:41:28 -0800 (PST) X-Received: by 10.220.200.6 with SMTP id eu6mr1019449vcb.35.1393440088475; Wed, 26 Feb 2014 10:41:28 -0800 (PST) Received: from mail-ve0-f171.google.com (mail-ve0-f171.google.com [209.85.128.171]) by mx.google.com with ESMTPS id sg4si456156vcb.86.2014.02.26.10.41.28 for (version=TLSv1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Wed, 26 Feb 2014 10:41:28 -0800 (PST) Received-SPF: neutral (google.com: 209.85.128.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) client-ip=209.85.128.171; Received: by mail-ve0-f171.google.com with SMTP id oz11so2595516veb.2 for ; Wed, 26 Feb 2014 10:41:28 -0800 (PST) X-Received: by 10.52.246.42 with SMTP id xt10mr5880726vdc.9.1393440088316; Wed, 26 Feb 2014 10:41:28 -0800 (PST) X-Forwarded-To: patchwork-forward@linaro.org X-Forwarded-For: patch@linaro.org patchwork-forward@linaro.org Delivered-To: patch@linaro.org Received: by 10.220.174.196 with SMTP id u4csp46832vcz; Wed, 26 Feb 2014 10:41:28 -0800 (PST) X-Received: by 10.58.145.9 with SMTP id sq9mr353130veb.53.1393440087807; Wed, 26 Feb 2014 10:41:27 -0800 (PST) Received: from lists.xen.org (lists.xen.org. [50.57.142.19]) by mx.google.com with ESMTPS id l4si458835vch.54.2014.02.26.10.41.27 for (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 26 Feb 2014 10:41:27 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xen.org designates 50.57.142.19 as permitted sender) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WIjP6-0007w8-H2; Wed, 26 Feb 2014 18:40:24 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1WIjOy-0007tt-3i for xen-devel@lists.xensource.com; Wed, 26 Feb 2014 18:40:16 +0000 Received: from [85.158.139.211:33302] by server-5.bemta-5.messagelabs.com id D4/6A-32749-F053E035; Wed, 26 Feb 2014 18:40:15 +0000 X-Env-Sender: Stefano.Stabellini@citrix.com X-Msg-Ref: server-9.tower-206.messagelabs.com!1393440013!6451951!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n X-StarScan-Received: X-StarScan-Version: 6.9.16; banners=-,-,- X-VirusChecked: Checked Received: (qmail 9442 invoked from network); 26 Feb 2014 18:40:14 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-9.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 26 Feb 2014 18:40:14 -0000 X-IronPort-AV: E=Sophos;i="4.97,549,1389744000"; d="scan'208";a="104388723" Received: from accessns.citrite.net (HELO FTLPEX01CL03.citrite.net) ([10.9.154.239]) by FTLPIPO02.CITRIX.COM with ESMTP; 26 Feb 2014 18:40:11 +0000 Received: from ukmail1.uk.xensource.com (10.80.16.128) by smtprelay.citrix.com (10.13.107.80) with Microsoft SMTP Server id 14.2.342.4; Wed, 26 Feb 2014 13:40:10 -0500 Received: from kaball.uk.xensource.com ([10.80.2.59]) by ukmail1.uk.xensource.com with esmtp (Exim 4.69) (envelope-from ) id 1WIjOm-0004S3-4A; Wed, 26 Feb 2014 18:40:04 +0000 From: Stefano Stabellini To: Date: Wed, 26 Feb 2014 18:39:48 +0000 Message-ID: <1393439997-26936-3-git-send-email-stefano.stabellini@eu.citrix.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: References: MIME-Version: 1.0 X-DLP: MIA1 Cc: julien.grall@citrix.com, jtd@galois.com, Ian.Campbell@citrix.com, Stefano Stabellini Subject: [Xen-devel] [PATCH-4.5 v3 03/12] xen/arm: support HW interrupts in gic_set_lr X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: stefano.stabellini@eu.citrix.com X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.128.171 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: If the irq to be injected is an hardware irq (p->desc != NULL), set GICH_LR_HW. Remove the code to EOI a physical interrupt on behalf of the guest because it has become unnecessary. Also add a struct vcpu* parameter to gic_set_lr. This patch needs the following patch to work correctly. It has been sent separately to make it easier to review. Signed-off-by: Stefano Stabellini Acked-by: Julien Grall --- Changes in v2: - remove the EOI code, now unnecessary; - do not assume physical IRQ == virtual IRQ; - refactor gic_set_lr. --- xen/arch/arm/gic.c | 52 +++++++++++++++++----------------------------------- 1 file changed, 17 insertions(+), 35 deletions(-) diff --git a/xen/arch/arm/gic.c b/xen/arch/arm/gic.c index 6f27630..fd42922 100644 --- a/xen/arch/arm/gic.c +++ b/xen/arch/arm/gic.c @@ -620,20 +620,24 @@ int __init setup_dt_irq(const struct dt_irq *irq, struct irqaction *new) return rc; } -static inline void gic_set_lr(int lr, unsigned int virtual_irq, +static inline void gic_set_lr(struct vcpu *v, int lr, unsigned int irq, unsigned int state, unsigned int priority) { - int maintenance_int = GICH_LR_MAINTENANCE_IRQ; - struct pending_irq *p = irq_to_pending(current, virtual_irq); + struct pending_irq *p = irq_to_pending(v, irq); + uint32_t lr_reg; BUG_ON(lr >= nr_lrs); BUG_ON(lr < 0); BUG_ON(state & ~(GICH_LR_STATE_MASK<> 3) << GICH_LR_PRIORITY_SHIFT) | - ((virtual_irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT); + ((irq & GICH_LR_VIRTUAL_MASK) << GICH_LR_VIRTUAL_SHIFT); + if ( p->desc != NULL ) + lr_reg |= GICH_LR_HW | + ((p->desc->irq & GICH_LR_PHYSICAL_MASK) << GICH_LR_PHYSICAL_SHIFT); + + GICH[GICH_LR + lr] = lr_reg; set_bit(GIC_IRQ_GUEST_VISIBLE, &p->status); clear_bit(GIC_IRQ_GUEST_PENDING, &p->status); @@ -668,7 +672,7 @@ void gic_remove_from_queues(struct vcpu *v, unsigned int virtual_irq) spin_unlock(&gic.lock); } -void gic_set_guest_irq(struct vcpu *v, unsigned int virtual_irq, +void gic_set_guest_irq(struct vcpu *v, unsigned int irq, unsigned int state, unsigned int priority) { int i; @@ -681,12 +685,12 @@ void gic_set_guest_irq(struct vcpu *v, unsigned int virtual_irq, i = find_first_zero_bit(&this_cpu(lr_mask), nr_lrs); if (i < nr_lrs) { set_bit(i, &this_cpu(lr_mask)); - gic_set_lr(i, virtual_irq, state, priority); + gic_set_lr(v, i, irq, state, priority); goto out; } } - gic_add_to_lr_pending(v, virtual_irq, priority); + gic_add_to_lr_pending(v, irq, priority); out: spin_unlock_irqrestore(&gic.lock, flags); @@ -705,7 +709,7 @@ static void gic_restore_pending_irqs(struct vcpu *v) if ( i >= nr_lrs ) return; spin_lock_irqsave(&gic.lock, flags); - gic_set_lr(i, p->irq, GICH_LR_PENDING, p->priority); + gic_set_lr(v, i, p->irq, GICH_LR_PENDING, p->priority); list_del_init(&p->lr_queue); set_bit(i, &this_cpu(lr_mask)); spin_unlock_irqrestore(&gic.lock, flags); @@ -886,15 +890,9 @@ int gicv_setup(struct domain *d) } -static void gic_irq_eoi(void *info) -{ - int virq = (uintptr_t) info; - GICC[GICC_DIR] = virq; -} - static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *regs) { - int i = 0, virq, pirq = -1; + int i = 0, virq; uint32_t lr; struct vcpu *v = current; uint64_t eisr = GICH[GICH_EISR0] | (((uint64_t) GICH[GICH_EISR1]) << 32); @@ -902,10 +900,8 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r while ((i = find_next_bit((const long unsigned int *) &eisr, 64, i)) < 64) { struct pending_irq *p, *p2; - int cpu; bool_t inflight; - cpu = -1; inflight = 0; spin_lock_irq(&gic.lock); @@ -915,12 +911,8 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r clear_bit(i, &this_cpu(lr_mask)); p = irq_to_pending(v, virq); - if ( p->desc != NULL ) { + if ( p->desc != NULL ) p->desc->status &= ~IRQ_INPROGRESS; - /* Assume only one pcpu needs to EOI the irq */ - cpu = p->desc->arch.eoi_cpu; - pirq = p->desc->irq; - } if ( test_bit(GIC_IRQ_GUEST_PENDING, &p->status) && test_bit(GIC_IRQ_GUEST_ENABLED, &p->status)) { @@ -932,7 +924,7 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r if ( !list_empty(&v->arch.vgic.lr_pending) ) { p2 = list_entry(v->arch.vgic.lr_pending.next, typeof(*p2), lr_queue); - gic_set_lr(i, p2->irq, GICH_LR_PENDING, p2->priority); + gic_set_lr(v, i, p2->irq, GICH_LR_PENDING, p2->priority); list_del_init(&p2->lr_queue); set_bit(i, &this_cpu(lr_mask)); } @@ -945,16 +937,6 @@ static void maintenance_interrupt(int irq, void *dev_id, struct cpu_user_regs *r spin_unlock_irq(&v->arch.vgic.lock); } - if ( p->desc != NULL ) { - /* this is not racy because we can't receive another irq of the - * same type until we EOI it. */ - if ( cpu == smp_processor_id() ) - gic_irq_eoi((void*)(uintptr_t)pirq); - else - on_selected_cpus(cpumask_of(cpu), - gic_irq_eoi, (void*)(uintptr_t)pirq, 0); - } - i++; } }