diff --git a/xen/arch/arm/domain.c b/xen/arch/arm/domain.c
index 2ae6941..e595a71 100644
--- a/xen/arch/arm/domain.c
+++ b/xen/arch/arm/domain.c
@@ -779,6 +779,19 @@ void vcpu_mark_events_pending(struct vcpu *v)
     vgic_vcpu_inject_irq(v, v->domain->arch.evtchn_irq, 1);
 }
 
+void vcpu_block_event(struct vcpu *v)
+{
+    vcpu_block();
+    /* The ARM spec declares that even if local irqs are masked in
+    * the CPSR register, an irq should wake up a cpu from WFI anyway.
+    * For this reason we need to check for irqs that need delivery,
+    * ignoring the CPSR register, *after* calling SCHEDOP_block to
+    * avoid races with vgic_vcpu_inject_irq.
+    */
+    if ( local_events_need_delivery_nomask() )
+        vcpu_unblock(current);
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/xen/arch/arm/domain_build.c b/xen/arch/arm/domain_build.c
index c424793..ebd4170 100644
--- a/xen/arch/arm/domain_build.c
+++ b/xen/arch/arm/domain_build.c
@@ -388,6 +388,9 @@ static int make_hypervisor_node(struct domain *d,
 static int make_psci_node(void *fdt, const struct dt_device_node *parent)
 {
     int res;
+    const char compat[] =
+        "arm,psci-0.2""\0"
+        "arm,psci";
 
     DPRINT("Create PSCI node\n");
 
@@ -396,7 +399,7 @@ static int make_psci_node(void *fdt, const struct dt_device_node *parent)
     if ( res )
         return res;
 
-    res = fdt_property_string(fdt, "compatible", "arm,psci");
+    res = fdt_property(fdt, "compatible", compat, sizeof(compat));
     if ( res )
         return res;
 
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index 03a3da6..e42fb07 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -1030,7 +1030,7 @@ static arm_hypercall_t arm_hypercall_table[] = {
     HYPERCALL_ARM(vcpu_op, 3),
 };
 
-typedef int (*arm_psci_fn_t)(uint32_t, register_t);
+typedef int (*arm_psci_fn_t)(register_t, register_t, register_t);
 
 typedef struct {
     arm_psci_fn_t fn;
@@ -1046,6 +1046,17 @@ typedef struct {
 static arm_psci_t arm_psci_table[] = {
     PSCI(cpu_off, 1),
     PSCI(cpu_on, 2),
+    PSCI(0_2_version,0),
+    PSCI(0_2_cpu_suspend,3),
+    PSCI(0_2_cpu_off,0),
+    PSCI(0_2_cpu_on,3),
+    PSCI(0_2_affinity_info,2),
+    PSCI(0_2_migrate,1),
+    PSCI(0_2_migrate_info_type,0),
+    PSCI(0_2_migrate_info_up_cpu,0),
+    PSCI(0_2_system_off,0),
+    PSCI(0_2_system_reset,0),
+
 };
 
 #ifndef NDEBUG
@@ -1082,24 +1093,37 @@ static void do_debug_trap(struct cpu_user_regs *regs, unsigned int code)
 #ifdef CONFIG_ARM_64
 #define PSCI_OP_REG(r) (r)->x0
 #define PSCI_RESULT_REG(r) (r)->x0
-#define PSCI_ARGS(r) (r)->x1, (r)->x2
+#define PSCI_ARGS(r) (r)->x1, (r)->x2, (r)->x3
 #else
 #define PSCI_OP_REG(r) (r)->r0
 #define PSCI_RESULT_REG(r) (r)->r0
-#define PSCI_ARGS(r) (r)->r1, (r)->r2
+#define PSCI_ARGS(r) (r)->r1, (r)->r2, (r)->r3
 #endif
 
 static void do_trap_psci(struct cpu_user_regs *regs)
 {
     arm_psci_fn_t psci_call = NULL;
+    unsigned int fn_index ;
+    struct domain *d = current->domain;
+
+    if ( PSCI_OP_REG(regs) < PSCI_0_1_MAX )
+        fn_index = PSCI_OP_REG(regs);
+    else if ( is_64bit_domain(d) )
+    {
+        fn_index = ( ( PSCI_OP_REG(regs) - PSCI_0_2_FN_OFFSET ) );
+        if ( fn_index > PSCI_0_2_64BIT )
+            fn_index -= PSCI_0_2_64BIT;
+    }
+    else
+        fn_index = ( PSCI_OP_REG(regs) - PSCI_0_2_FN_OFFSET ) ;
 
-    if ( PSCI_OP_REG(regs) >= ARRAY_SIZE(arm_psci_table) )
+    if ( fn_index >= ARRAY_SIZE(arm_psci_table) )
     {
         domain_crash_synchronous();
         return;
     }
 
-    psci_call = arm_psci_table[PSCI_OP_REG(regs)].fn;
+    psci_call = arm_psci_table[fn_index].fn;
     if ( psci_call == NULL )
     {
         domain_crash_synchronous();
diff --git a/xen/arch/arm/vpsci.c b/xen/arch/arm/vpsci.c
index 1ceb8cb..d29c097 100644
--- a/xen/arch/arm/vpsci.c
+++ b/xen/arch/arm/vpsci.c
@@ -17,6 +17,8 @@
 #include <asm/current.h>
 #include <asm/gic.h>
 #include <asm/psci.h>
+#include <public/sched.h>
+#include <asm-arm/event.h>
 
 int do_psci_cpu_on(uint32_t vcpuid, register_t entry_point)
 {
@@ -83,6 +85,171 @@ int do_psci_cpu_off(uint32_t power_state)
     return PSCI_SUCCESS;
 }
 
+int do_psci_0_2_version(void)
+{
+    return XEN_PSCI_V_0_2;
+}
+
+int do_psci_0_2_cpu_suspend(uint32_t power_state, register_t entry_point,
+                            register_t context_id)
+{
+    struct vcpu *v = current;
+    struct domain *d = v->domain;
+    struct cpu_user_regs *regs = &v->arch.cpu_info->guest_cpu_user_regs;
+
+    if ( is_32bit_domain(d) )
+    {
+        regs->pc32 = entry_point;
+        regs->r0 = context_id;
+    }
+#ifdef CONFIG_ARM_64
+    else
+    {
+        regs->pc = entry_point;
+        regs->x0 = context_id;
+    }
+#endif
+    vcpu_block_event(v);
+    return PSCI_SUCCESS;
+}
+
+int do_psci_0_2_cpu_off(void)
+{
+    uint32_t power_state = 0 ;
+    return do_psci_cpu_off(power_state);
+}
+
+int do_psci_0_2_cpu_on(register_t target_cpu, register_t entry_point,
+                       register_t context_id)
+{
+    struct vcpu *v;
+    struct domain *d = current->domain;
+    struct vcpu_guest_context *ctxt;
+    int rc;
+    int is_thumb = entry_point & 1;
+    uint32_t vcpuid = target_cpu & MPIDR_HWID_MASK;
+
+    if ( (vcpuid < 0) || (vcpuid >= MAX_VIRT_CPUS) )
+        return PSCI_EINVAL;
+
+    if ( vcpuid >= d->max_vcpus || (v = d->vcpu[vcpuid]) == NULL )
+        return PSCI_EINVAL;
+
+    /* THUMB set is not allowed with 64-bit domain */
+    if ( is_64bit_domain(d) && is_thumb )
+        return PSCI_EINVAL;
+
+    if ( !test_bit(_VPF_down, &v->pause_flags) )
+        return PSCI_ALREADY_ON;
+
+    if ( (ctxt = alloc_vcpu_guest_context()) == NULL )
+        return PSCI_DENIED;
+
+    vgic_clear_pending_irqs(v);
+
+    memset(ctxt, 0, sizeof(*ctxt));
+    ctxt->user_regs.pc64 = (u64) entry_point;
+    ctxt->sctlr = SCTLR_GUEST_INIT;
+    ctxt->ttbr0 = 0;
+    ctxt->ttbr1 = 0;
+    ctxt->ttbcr = 0; /* Defined Reset Value */
+    if ( is_32bit_domain(d) )
+    {
+        ctxt->user_regs.cpsr = PSR_GUEST32_INIT;
+        ctxt->user_regs.r0_usr = context_id;
+    }
+#ifdef CONFIG_ARM_64
+    else
+    {
+        ctxt->user_regs.cpsr = PSR_GUEST64_INIT;
+        ctxt->user_regs.x0 = context_id;
+    }
+#endif
+
+    /* Start the VCPU with THUMB set if it's requested by the kernel */
+    if ( is_thumb )
+        ctxt->user_regs.cpsr |= PSR_THUMB;
+    ctxt->flags = VGCF_online;
+
+    domain_lock(d);
+    rc = arch_set_info_guest(v, ctxt);
+    free_vcpu_guest_context(ctxt);
+
+    if ( rc < 0 )
+    {
+        domain_unlock(d);
+        return PSCI_DENIED;
+    }
+    domain_unlock(d);
+
+    vcpu_wake(v);
+
+    return PSCI_SUCCESS;
+}
+
+int do_psci_0_2_affinity_info(register_t target_affinity,
+                              uint32_t lowest_affinity_level)
+{
+    unsigned long target_affinity_mask;
+    unsigned int mpidr;
+    struct vcpu *v = current;
+
+    switch ( lowest_affinity_level )
+    {
+    case MPIDR_AFF0_SHIFT:
+    case MPIDR_AFF1_SHIFT:
+    case MPIDR_AFF2_SHIFT:
+        target_affinity_mask
+            = ( MPIDR_HWID_MASK & AFFINITY_MASK( lowest_affinity_level ) );
+        break;
+    case MPIDR_AFF3_SHIFT:
+        target_affinity_mask
+            = ( MPIDR_HWID_MASK & AFFINITY_MASK(lowest_affinity_level+1) );
+        break;
+    default:
+        return PSCI_EINVAL;
+    }
+
+    target_affinity &= target_affinity_mask;
+    mpidr = v->arch.vmpidr;
+    if ( ( mpidr & target_affinity_mask ) == target_affinity )
+        return PSCI_0_2_AFFINITY_LEVEL_ON;
+    else
+        return PSCI_0_2_AFFINITY_LEVEL_OFF;
+
+}
+
+int do_psci_0_2_migrate(uint32_t target_cpu)
+{
+    return PSCI_ENOSYS;
+}
+
+
+int do_psci_0_2_migrate_info_type(void)
+{
+    return PSCI_0_2_TOS_MP;
+}
+
+
+register_t do_psci_0_2_migrate_info_up_cpu(void)
+{
+    return PSCI_ENOSYS;
+}
+
+
+void do_psci_0_2_system_off( void )
+{
+    struct domain *d = current->domain;
+    domain_shutdown(d,SHUTDOWN_poweroff);
+}
+
+
+void do_psci_0_2_system_reset(void)
+{
+    struct domain *d = current->domain;
+    domain_shutdown(d,SHUTDOWN_reboot);
+}
+
 /*
  * Local variables:
  * mode: C
diff --git a/xen/include/asm-arm/event.h b/xen/include/asm-arm/event.h
index dd3ad13..6aba939 100644
--- a/xen/include/asm-arm/event.h
+++ b/xen/include/asm-arm/event.h
@@ -6,6 +6,7 @@
 
 void vcpu_kick(struct vcpu *v);
 void vcpu_mark_events_pending(struct vcpu *v);
+void vcpu_block_event(struct vcpu *v);
 
 static inline int vcpu_event_delivery_is_enabled(struct vcpu *v)
 {
@@ -55,6 +56,7 @@ static inline int arch_virq_is_global(int virq)
     return 1;
 }
 
+
 #endif
 /*
  * Local variables:
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 9267c1b..bf9d782 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -13,9 +13,15 @@
 #define _MPIDR_SMP          (31)
 #define MPIDR_SMP           (_AC(1,U) << _MPIDR_SMP)
 #define MPIDR_AFF0_SHIFT    (0)
+#define MPIDR_AFF1_SHIFT    (1)
+#define MPIDR_AFF2_SHIFT    (2)
+#define MPIDR_AFF3_SHIFT    (3)
 #define MPIDR_AFF0_MASK     (_AC(0xff,U) << MPIDR_AFF0_SHIFT)
 #define MPIDR_HWID_MASK     _AC(0xffffff,U)
 #define MPIDR_INVALID       (~MPIDR_HWID_MASK)
+#define MPIDR_AFF_BIT_SHIFT (8)
+#define AFFINITY_MASK(level) (_AC(0xff,U) << ((level)*MPIDR_AFF_BIT_SHIFT))
+
 
 /* TTBCR Translation Table Base Control Register */
 #define TTBCR_EAE    _AC(0x80000000,U)
diff --git a/xen/include/asm-arm/psci.h b/xen/include/asm-arm/psci.h
index 189964b..3487380 100644
--- a/xen/include/asm-arm/psci.h
+++ b/xen/include/asm-arm/psci.h
@@ -1,11 +1,6 @@
 #ifndef __ASM_PSCI_H__
 #define __ASM_PSCI_H__
 
-#define PSCI_SUCCESS  0
-#define PSCI_ENOSYS  -1
-#define PSCI_EINVAL  -2
-#define PSCI_DENIED  -3
-
 /* availability of PSCI on the host for SMP bringup */
 extern bool_t psci_available;
 
@@ -18,6 +13,123 @@ int do_psci_cpu_off(uint32_t power_state);
 int do_psci_cpu_suspend(uint32_t power_state, register_t entry_point);
 int do_psci_migrate(uint32_t vcpuid);
 
+/* PSCI 0.2 functions to handle guest PSCI requests */
+int do_psci_0_2_version(void);
+int do_psci_0_2_cpu_suspend(uint32_t power_state, register_t entry_point,
+                            register_t context_id);
+int do_psci_0_2_cpu_off(void);
+int do_psci_0_2_cpu_on(register_t target_cpu, register_t entry_point,
+                       register_t context_id);
+int do_psci_0_2_affinity_info(register_t target_affinity,
+                              uint32_t lowest_affinity_level);
+int do_psci_0_2_migrate(uint32_t target_cpu);
+int do_psci_0_2_migrate_info_type(void);
+register_t do_psci_0_2_migrate_info_up_cpu(void);
+void do_psci_0_2_system_off(void);
+void do_psci_0_2_system_reset(void);
+int do_psci_0_2_fn64_cpu_suspend(uint32_t power_state,
+                                 uint32_t entry_point, register_t context_id);
+int do_psci_0_2_fn64_cpu_on(register_t target_cpu, register_t entry_point,
+                            register_t context_id);
+int do_psci_0_2_fn64_affinity_info(register_t target_affinity,
+                                   uint32_t lowest_affinity_level);
+int do_psci_0_2_fn64_migrate(uint32_t target_cpu);
+int do_psci_0_2_fn64_migrate_info_up_cpu(void);
+
+/* PSCI version */
+#define XEN_PSCI_V_0_1 1
+#define XEN_PSCI_V_0_2 2
+
+/* PSCI v0.2 id's internal to xen */
+
+#define PSCI_0_2_version                  5
+#define PSCI_0_2_cpu_suspend              6
+#define PSCI_0_2_cpu_off                  7
+#define PSCI_0_2_cpu_on                   8
+#define PSCI_0_2_affinity_info            9
+#define PSCI_0_2_migrate                  10
+#define PSCI_0_2_migrate_info_type        11
+#define PSCI_0_2_migrate_info_up_cpu      12
+#define PSCI_0_2_system_off               13
+#define PSCI_0_2_system_reset             14
+
+#define PSCI_0_2_fn64_cpu_suspend         15
+#define PSCI_0_2_fn64_cpu_on              16
+#define PSCI_0_2_fn64_affinity_info       17
+#define PSCI_0_2_fn64_migrate             18
+#define PSCI_0_2_fn64_migrate_info_up_cpu 19
+
+/* PSCI v0.2 xen mapping mask */
+#define PSCI_0_2_FN_OFFSET         	0x83FFFFFB
+
+/* PSCI v0.2 interface */
+#define PSCI_0_2_FN_BASE			0x84000000
+#define PSCI_0_2_FN(n)				(PSCI_0_2_FN_BASE + (n))
+#define PSCI_0_2_64BIT				0x40000000
+#define PSCI_0_2_FN64_BASE			\
+					(PSCI_0_2_FN_BASE + PSCI_0_2_64BIT)
+#define PSCI_0_2_FN64(n)			(PSCI_0_2_FN64_BASE + (n))
+
+#define PSCI_0_2_FN_PSCI_VERSION		PSCI_0_2_FN(0)
+#define PSCI_0_2_FN_CPU_SUSPEND			PSCI_0_2_FN(1)
+#define PSCI_0_2_FN_CPU_OFF			PSCI_0_2_FN(2)
+#define PSCI_0_2_FN_CPU_ON			PSCI_0_2_FN(3)
+#define PSCI_0_2_FN_AFFINITY_INFO		PSCI_0_2_FN(4)
+#define PSCI_0_2_FN_MIGRATE			PSCI_0_2_FN(5)
+#define PSCI_0_2_FN_MIGRATE_INFO_TYPE		PSCI_0_2_FN(6)
+#define PSCI_0_2_FN_MIGRATE_INFO_UP_CPU		PSCI_0_2_FN(7)
+#define PSCI_0_2_FN_SYSTEM_OFF			PSCI_0_2_FN(8)
+#define PSCI_0_2_FN_SYSTEM_RESET		PSCI_0_2_FN(9)
+
+#define PSCI_0_2_FN64_CPU_SUSPEND		PSCI_0_2_FN64(1)
+#define PSCI_0_2_FN64_CPU_ON			PSCI_0_2_FN64(3)
+#define PSCI_0_2_FN64_AFFINITY_INFO		PSCI_0_2_FN64(4)
+#define PSCI_0_2_FN64_MIGRATE			PSCI_0_2_FN64(5)
+#define PSCI_0_2_FN64_MIGRATE_INFO_UP_CPU	PSCI_0_2_FN64(7)
+
+/* PSCI v0.2 power state encoding for CPU_SUSPEND function */
+#define PSCI_0_2_POWER_STATE_ID_MASK		0xffff
+#define PSCI_0_2_POWER_STATE_ID_SHIFT		0
+#define PSCI_0_2_POWER_STATE_TYPE_SHIFT		16
+#define PSCI_0_2_POWER_STATE_TYPE_MASK		\
+				(0x1 << PSCI_0_2_POWER_STATE_TYPE_SHIFT)
+#define PSCI_0_2_POWER_STATE_AFFL_SHIFT		24
+#define PSCI_0_2_POWER_STATE_AFFL_MASK		\
+				(0x3 << PSCI_0_2_POWER_STATE_AFFL_SHIFT)
+
+/* PSCI v0.2 affinity level state returned by AFFINITY_INFO */
+#define PSCI_0_2_AFFINITY_LEVEL_ON		0
+#define PSCI_0_2_AFFINITY_LEVEL_OFF		1
+#define PSCI_0_2_AFFINITY_LEVEL_ON_PENDING	2
+
+/* PSCI v0.2 multicore support in Trusted OS returned by MIGRATE_INFO_TYPE */
+#define PSCI_0_2_TOS_UP_MIGRATE			0
+#define PSCI_0_2_TOS_UP_NO_MIGRATE		1
+#define PSCI_0_2_TOS_MP				2
+
+/* PSCI version decoding (independent of PSCI version) */
+#define PSCI_VERSION_MAJOR_SHIFT		16
+#define PSCI_VERSION_MINOR_MASK			\
+		((1U << PSCI_VERSION_MAJOR_SHIFT) - 1)
+#define PSCI_VERSION_MAJOR_MASK			~PSCI_VERSION_MINOR_MASK
+#define PSCI_VERSION_MAJOR(ver)			\
+		(((ver) & PSCI_VERSION_MAJOR_MASK) >> PSCI_VERSION_MAJOR_SHIFT)
+#define PSCI_VERSION_MINOR(ver)			\
+		((ver) & PSCI_VERSION_MINOR_MASK)
+
+
+/* PSCI return values (inclusive of all PSCI versions) */
+#define PSCI_SUCCESS             0
+#define PSCI_ENOSYS             -1
+#define PSCI_EINVAL             -2
+#define PSCI_DENIED             -3
+#define PSCI_ALREADY_ON			-4
+#define PSCI_ON_PENDING			-5
+#define PSCI_INTERNAL_FAILURE	-6
+#define PSCI_NOT_PRESENT		-7
+#define PSCI_DISABLED			-8
+
+
 #endif /* __ASM_PSCI_H__ */
 
 /*
diff --git a/xen/include/public/arch-arm.h b/xen/include/public/arch-arm.h
index 7496556..93803e4 100644
--- a/xen/include/public/arch-arm.h
+++ b/xen/include/public/arch-arm.h
@@ -385,6 +385,7 @@ typedef uint64_t xen_callback_t;
 #define PSCI_cpu_off     1
 #define PSCI_cpu_on      2
 #define PSCI_migrate     3
+#define PSCI_0_1_MAX     4
 
 #endif
 
