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([185.25.64.249]) by mx.google.com with ESMTPSA id hl8sm3203005wjb.38.2015.03.19.12.31.21 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 19 Mar 2015 12:31:21 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xenproject.org Date: Thu, 19 Mar 2015 19:29:56 +0000 Message-Id: <1426793399-6283-31-git-send-email-julien.grall@linaro.org> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1426793399-6283-1-git-send-email-julien.grall@linaro.org> References: <1426793399-6283-1-git-send-email-julien.grall@linaro.org> Cc: Wei Liu , ian.campbell@citrix.com, tim@xen.org, Julien Grall , Ian Jackson , stefano.stabellini@citrix.com Subject: [Xen-devel] [PATCH v4 30/33] tools/libxl: arm: Use an higher value for the GIC phandle X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , MIME-Version: 1.0 Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: julien.grall@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.215.44 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: The partial device tree may contains phandle. The Device Tree Compiler tends to allocate the phandle from 1. Reserve the ID 65000 for the GIC phandle. I think we can safely assume that the partial device tree will never contain a such ID. Signed-off-by: Julien Grall Cc: Ian Jackson Cc: Wei Liu --- It's not easily possible to track the maximum phandle in the partial device tree. We would need to parse it twice: one for looking the maximum phandle, and one for copying the nodes. This is because we have to know the phandle of the GIC when we create the properties of the root. As the phandle is encoded an unsigned 32 bits, I could use an higher value. Though, having 65000 phandle is already a lot... TODO: If it's necessary, I can check if the value has been used by another phandle in the device tree. Changes in v3: - Patch added --- tools/libxl/libxl_arm.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index 54d197b..0723a47 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -80,10 +80,11 @@ static struct arch_info { {"xen-3.0-aarch64", "arm,armv8-timer", "arm,armv8" }, }; -enum { - PHANDLE_NONE = 0, - PHANDLE_GIC, -}; +/* + * The device tree compiler (DTC) is allocating the phandle from 1 to + * onwards. Reserve a high value for the GIC phandle. + */ +#define PHANDLE_GIC (65000) typedef uint32_t be32; typedef be32 gic_interrupt[3];