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[50.57.142.19]) by mx.google.com with ESMTPS id yf7si1695988vdc.30.2015.04.01.09.50.02 (version=TLSv1 cipher=RC4-SHA bits=128/128); Wed, 01 Apr 2015 09:50:03 -0700 (PDT) Received-SPF: none (google.com: xen-devel-bounces@lists.xen.org does not designate permitted sender hosts) client-ip=50.57.142.19; Received: from localhost ([127.0.0.1] helo=lists.xen.org) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YdLoE-0001fX-CO; Wed, 01 Apr 2015 16:48:06 +0000 Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xen.org with esmtp (Exim 4.72) (envelope-from ) id 1YdLoD-0001fN-9p for xen-devel@lists.xenproject.org; Wed, 01 Apr 2015 16:48:05 +0000 Received: from [85.158.139.211] by server-7.bemta-5.messagelabs.com id 86/D9-02028-4412C155; Wed, 01 Apr 2015 16:48:04 +0000 X-Env-Sender: julien.grall@citrix.com X-Msg-Ref: server-4.tower-206.messagelabs.com!1427906882!13297215!1 X-Originating-IP: [66.165.176.63] X-SpamReason: No, hits=0.0 required=7.0 tests=sa_preprocessor: VHJ1c3RlZCBJUDogNjYuMTY1LjE3Ni42MyA9PiAzMDYwNDg=\n, received_headers: No Received headers X-StarScan-Received: X-StarScan-Version: 6.13.6; banners=-,-,- X-VirusChecked: Checked Received: (qmail 10495 invoked from network); 1 Apr 2015 16:48:03 -0000 Received: from smtp02.citrix.com (HELO SMTP02.CITRIX.COM) (66.165.176.63) by server-4.tower-206.messagelabs.com with RC4-SHA encrypted SMTP; 1 Apr 2015 16:48:03 -0000 X-IronPort-AV: E=Sophos;i="5.11,504,1422921600"; d="scan'208";a="250401359" From: Julien Grall To: Date: Wed, 1 Apr 2015 17:21:47 +0100 Message-ID: <1427905307-23749-15-git-send-email-julien.grall@citrix.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1427905307-23749-1-git-send-email-julien.grall@citrix.com> References: <1427905307-23749-1-git-send-email-julien.grall@citrix.com> MIME-Version: 1.0 X-DLP: MIA1 Cc: Zoltan Kiss , ian.campbell@citrix.com, Julien Grall , tim@xen.org, Frediano Ziglio , stefano.stabellini@citrix.com Subject: [Xen-devel] [PATCH v5 p1 14/14] xen/arm: gic: GICv2 & GICv3 only supports 1020 physical interrupts X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: List-Unsubscribe: , List-Post: , List-Help: , List-Subscribe: , Sender: xen-devel-bounces@lists.xen.org Errors-To: xen-devel-bounces@lists.xen.org X-Removed-Original-Auth: Dkim didn't pass. X-Original-Sender: patch@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 209.85.217.171 as permitted sender) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org Mailing-list: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org X-Google-Group-Id: 836684582541 List-Archive: From: Julien Grall GICD_TYPER.ITLinesNumber can encode up to 1024 interrupts. Although, IRQ 1020-1023 are reserved for special purpose. The result is used by the callers of gic_number_lines in order to check the validity of an IRQ. Signed-off-by: Julien Grall Acked-by: Ian Campbell Cc: Frediano Ziglio Cc: Zoltan Kiss --- The GIC HIP04 driver would need a similar if they have some IRQ reserved below 512. Maintainers are CCed. Changes in v5: - Add Ian's ack Changes in v4: - This patch was formerly sent separatly https://patches.linaro.org/45373/ - s/(unsigned)1020/1020U/ --- xen/arch/arm/gic-v2.c | 16 ++++++++++------ xen/arch/arm/gic-v3.c | 16 ++++++++++------ 2 files changed, 20 insertions(+), 12 deletions(-) diff --git a/xen/arch/arm/gic-v2.c b/xen/arch/arm/gic-v2.c index 3be4ad6..cfefb39 100644 --- a/xen/arch/arm/gic-v2.c +++ b/xen/arch/arm/gic-v2.c @@ -256,6 +256,7 @@ static void __init gicv2_dist_init(void) uint32_t type; uint32_t cpumask; uint32_t gic_cpus; + unsigned int nr_lines; int i; cpumask = readl_gicd(GICD_ITARGETSR) & 0xff; @@ -266,31 +267,34 @@ static void __init gicv2_dist_init(void) writel_gicd(0, GICD_CTLR); type = readl_gicd(GICD_TYPER); - gicv2_info.nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1); + nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1); gic_cpus = 1 + ((type & GICD_TYPE_CPUS) >> 5); printk("GICv2: %d lines, %d cpu%s%s (IID %8.8x).\n", - gicv2_info.nr_lines, gic_cpus, (gic_cpus == 1) ? "" : "s", + nr_lines, gic_cpus, (gic_cpus == 1) ? "" : "s", (type & GICD_TYPE_SEC) ? ", secure" : "", readl_gicd(GICD_IIDR)); /* Default all global IRQs to level, active low */ - for ( i = 32; i < gicv2_info.nr_lines; i += 16 ) + for ( i = 32; i < nr_lines; i += 16 ) writel_gicd(0x0, GICD_ICFGR + (i / 16) * 4); /* Route all global IRQs to this CPU */ - for ( i = 32; i < gicv2_info.nr_lines; i += 4 ) + for ( i = 32; i < nr_lines; i += 4 ) writel_gicd(cpumask, GICD_ITARGETSR + (i / 4) * 4); /* Default priority for global interrupts */ - for ( i = 32; i < gicv2_info.nr_lines; i += 4 ) + for ( i = 32; i < nr_lines; i += 4 ) writel_gicd(GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 | GIC_PRI_IRQ << 8 | GIC_PRI_IRQ, GICD_IPRIORITYR + (i / 4) * 4); /* Disable all global interrupts */ - for ( i = 32; i < gicv2_info.nr_lines; i += 32 ) + for ( i = 32; i < nr_lines; i += 32 ) writel_gicd(~0x0, GICD_ICENABLER + (i / 32) * 4); + /* Only 1020 interrupts are supported */ + gicv2_info.nr_lines = min(1020U, nr_lines); + /* Turn on the distributor */ writel_gicd(GICD_CTL_ENABLE, GICD_CTLR); } diff --git a/xen/arch/arm/gic-v3.c b/xen/arch/arm/gic-v3.c index 48772f1..b0f498e 100644 --- a/xen/arch/arm/gic-v3.c +++ b/xen/arch/arm/gic-v3.c @@ -528,23 +528,24 @@ static void __init gicv3_dist_init(void) uint32_t type; uint32_t priority; uint64_t affinity; + unsigned int nr_lines; int i; /* Disable the distributor */ writel_relaxed(0, GICD + GICD_CTLR); type = readl_relaxed(GICD + GICD_TYPER); - gicv3_info.nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1); + nr_lines = 32 * ((type & GICD_TYPE_LINES) + 1); printk("GICv3: %d lines, (IID %8.8x).\n", - gicv3_info.nr_lines, readl_relaxed(GICD + GICD_IIDR)); + nr_lines, readl_relaxed(GICD + GICD_IIDR)); /* Default all global IRQs to level, active low */ - for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 16 ) + for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 16 ) writel_relaxed(0, GICD + GICD_ICFGR + (i / 16) * 4); /* Default priority for global interrupts */ - for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 4 ) + for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 4 ) { priority = (GIC_PRI_IRQ << 24 | GIC_PRI_IRQ << 16 | GIC_PRI_IRQ << 8 | GIC_PRI_IRQ); @@ -552,7 +553,7 @@ static void __init gicv3_dist_init(void) } /* Disable all global interrupts */ - for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i += 32 ) + for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i += 32 ) writel_relaxed(0xffffffff, GICD + GICD_ICENABLER + (i / 32) * 4); gicv3_dist_wait_for_rwp(); @@ -566,8 +567,11 @@ static void __init gicv3_dist_init(void) /* Make sure we don't broadcast the interrupt */ affinity &= ~GICD_IROUTER_SPI_MODE_ANY; - for ( i = NR_GIC_LOCAL_IRQS; i < gicv3_info.nr_lines; i++ ) + for ( i = NR_GIC_LOCAL_IRQS; i < nr_lines; i++ ) writeq_relaxed(affinity, GICD + GICD_IROUTER + i * 8); + + /* Only 1020 interrupts are supported */ + gicv3_info.nr_lines = min(1020U, nr_lines); } static int gicv3_enable_redist(void)