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banners=-,-,- X-VirusChecked: Checked Received: (qmail 44270 invoked from network); 10 May 2017 14:38:03 -0000 Received: from mail-pf0-f176.google.com (HELO mail-pf0-f176.google.com) (209.85.192.176) by server-12.tower-206.messagelabs.com with AES128-GCM-SHA256 encrypted SMTP; 10 May 2017 14:38:03 -0000 Received: by mail-pf0-f176.google.com with SMTP id m17so16892523pfg.3 for ; Wed, 10 May 2017 07:38:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=pZJbGwtFrFjhxXZhX2CofCVXtTjcHxZ2asByuzAQ4qs=; b=drRdTcY4zDgOtZYGu0EAMCXnSPPFmGQrXOvAWKxq4X/hopDmWyOKN5SPtvpeOM7hYC ZMqIlWP18nAgXhAgwebZ470mYPeiSSBBLEbx4rjOCZNP7SAoudhZ1bxxFGEDeQHPt0gh EYlN9apRM0CbVaRWcsP+V5e/1+PzNWKIHDi00= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=pZJbGwtFrFjhxXZhX2CofCVXtTjcHxZ2asByuzAQ4qs=; b=c40tSVFP6CCNa42r6NzaT/hVGjDD6H/WvGjRuLAX/5tJ8elJxtGq7Cjhy8gLfAfvEQ 41Wtmx0wp0kmA0jgXxAvni+36URIyUD8K5NEowfZj9mm3yfdIqdosOCgB2T/ekyD7CsS MbruaAHC5uz82VfCEHo23zwU4qnjF4GzIzzUY37jl78RHvJAa7nW7uvSWF//hVpUr/zX 8Wo2I3IuwA3/Y5sGZjjYl57ztAL567zJPi2wco0q4jyWTxRWhOBzhYKlweK1dXHCJNCZ zW+uhmYCo4E00osVdrDEv+KBjVMAJ1LQnV7Ckw4mUfUJCeC4siscoJLhO6y+kymaNxCN GW6Q== X-Gm-Message-State: AODbwcD+9rQgoVMUi7CiOzXgGjj4aqnxlB1s792GyZySV19i2RTF3D9X 0kpilXQvwt1KMeX+ X-Received: by 10.84.135.129 with SMTP id 1mr3336353plj.57.1494427081385; Wed, 10 May 2017 07:38:01 -0700 (PDT) Received: from blr-ubuntu-linaro.wlan.qualcomm.com ([61.0.91.57]) by smtp.gmail.com with ESMTPSA id r73sm6167781pfa.65.2017.05.10.07.37.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 10 May 2017 07:38:00 -0700 (PDT) From: Bhupinder Thakur To: xen-devel@lists.xenproject.org Date: Wed, 10 May 2017 20:05:17 +0530 Message-Id: <1494426918-32737-6-git-send-email-bhupinder.thakur@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1494426918-32737-1-git-send-email-bhupinder.thakur@linaro.org> References: <1494426918-32737-1-git-send-email-bhupinder.thakur@linaro.org> Cc: Wei Liu , Ian Jackson Subject: [Xen-devel] [PATCH 11/12 v3] xen/arm: vpl011: Add a pl011 uart DT node in the guest device tree X-BeenThere: xen-devel@lists.xen.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" The SBSA uart node format is as specified in Documentation/devicetree/bindings/serial/arm_sbsa_uart.txt and given below: ARM SBSA defined generic UART ------------------------------ This UART uses a subset of the PL011 registers and consequently lives in the PL011 driver. It's baudrate and other communication parameters cannot be adjusted at runtime, so it lacks a clock specifier here. Required properties: - compatible: must be "arm,sbsa-uart" - reg: exactly one register range - interrupts: exactly one interrupt specifier - current-speed: the (fixed) baud rate set by the firmware Signed-off-by: Bhupinder Thakur Reviewed-by: Stefano Stabellini --- Changes since v2: - Currently device discovery using ACPI is not supported. - Dropped the reviewed-by tag by Stefano as there were some IRQ related changes done later. tools/libxl/libxl_arm.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 51 insertions(+), 2 deletions(-) diff --git a/tools/libxl/libxl_arm.c b/tools/libxl/libxl_arm.c index d842d88..f88ef0d 100644 --- a/tools/libxl/libxl_arm.c +++ b/tools/libxl/libxl_arm.c @@ -44,10 +44,23 @@ int libxl__arch_domain_prepare_config(libxl__gc *gc, uint32_t nr_spis = 0; unsigned int i; + /* + * If pl011 vuart is enabled then increment the nr_spis to allow allocation + * of SPI VIRQ for pl011. + */ + if (d_config->b_info.vuart) + nr_spis += (GUEST_VPL011_SPI - 32) + 1; + for (i = 0; i < d_config->b_info.num_irqs; i++) { uint32_t irq = d_config->b_info.irqs[i]; uint32_t spi; + if (d_config->b_info.vuart && (irq == GUEST_VPL011_SPI)) + { + LOG(ERROR, "Physical IRQ %u conflicting with pl011 SPI\n", irq); + return ERROR_FAIL; + } + if (irq < 32) continue; @@ -130,9 +143,10 @@ static struct arch_info { const char *guest_type; const char *timer_compat; const char *cpu_compat; + const char *uart_compat; } arch_info[] = { - {"xen-3.0-armv7l", "arm,armv7-timer", "arm,cortex-a15" }, - {"xen-3.0-aarch64", "arm,armv8-timer", "arm,armv8" }, + {"xen-3.0-armv7l", "arm,armv7-timer", "arm,cortex-a15", "arm,sbsa-uart" }, + {"xen-3.0-aarch64", "arm,armv8-timer", "arm,armv8", "arm,sbsa-uart" }, }; /* @@ -590,6 +604,38 @@ static int make_hypervisor_node(libxl__gc *gc, void *fdt, return 0; } +static int make_vpl011_uart_node(libxl__gc *gc, void *fdt, + const struct arch_info *ainfo, + struct xc_dom_image *dom) +{ + int res; + gic_interrupt intr; + + res = fdt_begin_node(fdt, "sbsa-pl011"); + if (res) return res; + + res = fdt_property_compat(gc, fdt, 1, ainfo->uart_compat); + if (res) return res; + + res = fdt_property_regs(gc, fdt, ROOT_ADDRESS_CELLS, ROOT_SIZE_CELLS, + 1, + GUEST_PL011_BASE, GUEST_PL011_SIZE); + if (res) return res; + + set_interrupt(intr, GUEST_VPL011_SPI, 0xf, DT_IRQ_TYPE_LEVEL_HIGH); + + res = fdt_property_interrupts(gc, fdt, &intr, 1); + if (res) return res; + + /* Use a default baud rate of 115200. */ + fdt_property_u32(fdt, "current-speed", 115200); + + res = fdt_end_node(fdt); + if (res) return res; + + return 0; +} + static const struct arch_info *get_arch_info(libxl__gc *gc, const struct xc_dom_image *dom) { @@ -889,6 +935,9 @@ next_resize: FDT( make_timer_node(gc, fdt, ainfo, xc_config->clock_frequency) ); FDT( make_hypervisor_node(gc, fdt, vers) ); + if (info->vuart) + FDT( make_vpl011_uart_node(gc, fdt, ainfo, dom) ); + if (pfdt) FDT( copy_partial_fdt(gc, fdt, pfdt) );