From patchwork Tue Sep 25 17:20:38 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 147515 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp987545lji; Tue, 25 Sep 2018 10:23:16 -0700 (PDT) X-Google-Smtp-Source: ACcGV63RZMk4EbGQFvPdzZ/+BH8Solh1aOGaoGu62JLIlA99SNvJf06pj5EcC5ZsBk/XN1FjTqqn X-Received: by 2002:a02:c7d1:: with SMTP id s17-v6mr1984175jao.27.1537896196550; Tue, 25 Sep 2018 10:23:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1537896196; cv=none; d=google.com; s=arc-20160816; b=OpjTrsHsO77Ddu8i27bLpTES7ss4Ht4waNID0fPsbRYtxF3NNkvs2bKUp/0Hd2pWjE llgnCAPo075gyDp5INFVMDidwOb0irB+qFKWpp0AnaAy4zsanuXzqX0tvRviL297Fa0Q 7wkwOzuPGk2LFbLbZ3geD4PaL4CdNm856Zxhn6Mlf8SLDgelUa7TVXZBOi18rAyMHkk1 ECspP6cwIDODc+ItG/hbqe0O515CZTNEX2+vRl/mYEYP+grpjXen6oPA8yTCLPri7pgd 7On1OfPq4o6tZRUUQQmOktyn2Snqw44oIYwVgi7OmggJC2bm2afxPPDl7ArOFNwXHv7Q CL2g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=96wDaMr60MeqLREVWPgznJFf6IQyOjNNtSLdoPb7eVA=; b=HAMzLgn8HxrGRkuUbOKvLwQnhqcFvTJ4wwx4P/u+iQy7GcKI9Kb5Gf17oZzJqC4C2N iHPRcaaSQVmtwUN1aJBsvMXqIwwnAzr0eQ1+LjXL24GEYSyrPTe3DdVI2NWvq6qt5+0j auRT/3vAPXTTh387YqE2uHQX9ph686TZ6INL/HMbv+gD2skm/JIyT8/9SmIn4U9VEuDs ixTeHgLaw7RN9XMINT4m/S9B8/Hts28Fy3CY6MyK7OnWAD83J6BpWJgN5nRESCTcUvD3 xyJkvzy4tbogfrERU6EVuwZLOxaABN94eiYRJMlDOZ4DO18KlrTfC5S/7/rWG6AVTgwk YpkA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id e17-v6si1711220itf.105.2018.09.25.10.23.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 25 Sep 2018 10:23:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r14-0004AW-QW; Tue, 25 Sep 2018 17:20:54 +0000 Received: from us1-rack-dfw2.inumbo.com ([104.130.134.6]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g4r13-0004A9-SJ for xen-devel@lists.xen.org; Tue, 25 Sep 2018 17:20:53 +0000 X-Inumbo-ID: 0c147c4c-c0e7-11e8-a8a5-bc764e045a96 Received: from foss.arm.com (unknown [217.140.101.70]) by us1-rack-dfw2.inumbo.com (Halon) with ESMTP id 0c147c4c-c0e7-11e8-a8a5-bc764e045a96; Tue, 25 Sep 2018 19:18:40 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A49415AD; Tue, 25 Sep 2018 10:20:51 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.Emea.Arm.com [10.4.12.35]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7A0213F5BD; Tue, 25 Sep 2018 10:20:50 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Tue, 25 Sep 2018 18:20:38 +0100 Message-Id: <20180925172043.20248-2-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20180925172043.20248-1-julien.grall@arm.com> References: <20180925172043.20248-1-julien.grall@arm.com> Subject: [Xen-devel] [PATCH v2 1/6] xen/arm: smccc-1.1: Make return values unsigned long X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier , Julien Grall , sstabellini@kernel.org, volodymyr_babchuk@epam.com MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" From: Marc Zyngier An unfortunate consequence of having a strong typing for the input values to the SMC call is that it also affects the type of the return values, limiting r0 to 32 bits and r{1,2,3} to whatever was passed as an input. Let's turn everything into "unsigned long", which satisfies the requirements of both architectures, and allows for the full range of return values. Reported-by: Stefano Stabellini Signed-off-by: Marc Zyngier Signed-off-by: Julien Grall Reviewed-by: Volodymyr Babchuk Reviewed-by: Stefano Stabellini --- Changes in v2: - Add Volodymyr reviewed-by --- xen/include/asm-arm/smccc.h | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/xen/include/asm-arm/smccc.h b/xen/include/asm-arm/smccc.h index 74c13f8419..a31d67a1de 100644 --- a/xen/include/asm-arm/smccc.h +++ b/xen/include/asm-arm/smccc.h @@ -119,35 +119,35 @@ struct arm_smccc_res { #define __declare_arg_0(a0, res) \ struct arm_smccc_res *___res = res; \ - register uin32_t r0 asm("r0") = a0; \ + register unsigned long r0 asm("r0") = (uint32_t)a0;\ register unsigned long r1 asm("r1"); \ register unsigned long r2 asm("r2"); \ register unsigned long r3 asm("r3") #define __declare_arg_1(a0, a1, res) \ struct arm_smccc_res *___res = res; \ - register uint32_t r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ + register unsigned long r0 asm("r0") = (uint32_t)a0;\ + register unsigned long r1 asm("r1") = a1; \ register unsigned long r2 asm("r2"); \ register unsigned long r3 asm("r3") #define __declare_arg_2(a0, a1, a2, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ - register typeof(a2) r2 asm("r2") = a2; \ + register unsigned long r0 asm("r0") = (uint32_t)a0;\ + register unsigned long r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2") = a2; \ register unsigned long r3 asm("r3") #define __declare_arg_3(a0, a1, a2, a3, res) \ struct arm_smccc_res *___res = res; \ - register u32 r0 asm("r0") = a0; \ - register typeof(a1) r1 asm("r1") = a1; \ - register typeof(a2) r2 asm("r2") = a2; \ - register typeof(a3) r3 asm("r3") = a3 + register unsigned long r0 asm("r0") = (uint32_t)a0;\ + register unsigned long r1 asm("r1") = a1; \ + register unsigned long r2 asm("r2") = a2; \ + register unsigned long r3 asm("r3") = a3 #define __declare_arg_4(a0, a1, a2, a3, a4, res) \ __declare_arg_3(a0, a1, a2, a3, res); \ - register typeof(a4) r4 asm("r4") = a4 + register unsigned long r4 asm("r4") = a4 #define __declare_arg_5(a0, a1, a2, a3, a4, a5, res) \ __declare_arg_4(a0, a1, a2, a3, a4, res); \