From patchwork Mon Oct 8 18:33:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Julien Grall X-Patchwork-Id: 148422 Delivered-To: patch@linaro.org Received: by 2002:a2e:8595:0:0:0:0:0 with SMTP id b21-v6csp3982023lji; Mon, 8 Oct 2018 11:36:14 -0700 (PDT) X-Google-Smtp-Source: ACcGV62evaISXo/IK4AY4pex8ogfqN8Z9a8X7zLXSd+9m4QXoBdBffyb30wtgono+nMvaBbLWlbv X-Received: by 2002:a24:6907:: with SMTP id e7-v6mr216542itc.113.1539023774418; Mon, 08 Oct 2018 11:36:14 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1539023774; cv=none; d=google.com; s=arc-20160816; b=Soeo6oX2/yOktDemSRO0sqU6St2x0bLvT4J4aldy94fpETmJXzvUz+OP+0LcSCNejj rmdrUyRbSTE3xa5xc1wyrpKxiwjPeHG04TLrgZaAk+QQBpjqKu8tLrNpbDKV4Fh8vVA6 eiq34AELNBubxeJf++AW1qV165yR9zlQWhzpDXTIEcAuajGD9BuEjSQiQ2POd3PpNb+Q cx8yMlGH8urVJkYFnkO5KLVu9OvJcEx7BlAocKFXW4M6VtwAoNRzgyq7zgK3if2rsctA soVxy4064ctu3XGOmqQwt/sNVBaBqNDvh23WVKGCbL9UeXum4omlDYALYSfqI1pZHicD 2ulA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version:cc :list-subscribe:list-help:list-post:list-unsubscribe:list-id :precedence:subject:references:in-reply-to:message-id:date:to:from; bh=w3/kZYZI1JWQaiMp+++HsyTaNqWuc3Hh6dx7GIqX+18=; b=Vcvcm5OhincetbOm85N6iCJKjIGm8cWWJ2WgcOtgI1CraFAjaEcIPyLL4byy6p5U3q PFWzXg7lYJ1RMrAejTffv2dtUrzs7ZlveG8yWXiuszzxavYzX9RTSL5JVtZNH7XN2tfa EaejMui8DIWuKXIgeN+33z85VSvAwTUXHZq7cJZGrY+zEGeoMHomtDqqibP19PMYizVO 1emssb7O1YnsSqrcnxje2zCVPsLBDn1cKyemYR2lIVel1jDgZu7/JiZBJY79kIlkkzfE 6nMAzi3RAw3UYZOfMOZeyapMHAkFtelZwlxNALIeLIOQ6CR8VMTPUYsDBzHnNBF6XKYQ 6/qw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Return-Path: Received: from lists.xenproject.org (lists.xenproject.org. [192.237.175.120]) by mx.google.com with ESMTPS id h79-v6si8117867ita.135.2018.10.08.11.36.14 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 08 Oct 2018 11:36:14 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of xen-devel-bounces@lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org Received: from localhost ([127.0.0.1] helo=lists.xenproject.org) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMC-0005lc-A4; Mon, 08 Oct 2018 18:34:16 +0000 Received: from all-amaz-eas1.inumbo.com ([34.197.232.57]) by lists.xenproject.org with esmtp (Exim 4.89) (envelope-from ) id 1g9aMB-0005k6-6A for xen-devel@lists.xen.org; Mon, 08 Oct 2018 18:34:15 +0000 X-Inumbo-ID: ef3678fa-cb28-11e8-a6a9-d7ebe60f679a Received: from foss.arm.com (unknown [217.140.101.70]) by us1-amaz-eas1.inumbo.com (Halon) with ESMTP id ef3678fa-cb28-11e8-a6a9-d7ebe60f679a; Mon, 08 Oct 2018 18:35:30 +0000 (UTC) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id D042715B2; Mon, 8 Oct 2018 11:34:13 -0700 (PDT) Received: from e108454-lin.cambridge.arm.com (e108454-lin.cambridge.arm.com [10.1.196.50]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id E582C3F5B3; Mon, 8 Oct 2018 11:34:12 -0700 (PDT) From: Julien Grall To: xen-devel@lists.xen.org Date: Mon, 8 Oct 2018 19:33:47 +0100 Message-Id: <20181008183352.16291-12-julien.grall@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20181008183352.16291-1-julien.grall@arm.com> References: <20181008183352.16291-1-julien.grall@arm.com> Subject: [Xen-devel] [RFC 11/16] xen/arm: vsysreg: Add wrapper to handle sysreg access trapped by HCR_EL2.TVM X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Julien Grall , sstabellini@kernel.org, andre.przywara@linaro.org MIME-Version: 1.0 Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" A follow-up patch will require to emulate some accesses to system registers trapped by HCR_EL2.TVM. When set, all NS EL1 writes to the virtual memory control registers will be trapped to the hypervisor. This patch adds the infrastructure to passthrough the access to the host registers. Note that HCR_EL2.TVM will be set in a follow-up patch dynamically. Signed-off-by: Julien Grall Reviewed-by: Stefano Stabellini --- xen/arch/arm/arm64/vsysreg.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c index 6e60824572..1517879697 100644 --- a/xen/arch/arm/arm64/vsysreg.c +++ b/xen/arch/arm/arm64/vsysreg.c @@ -23,6 +23,46 @@ #include #include +/* + * Macro to help generating helpers for registers trapped when + * HCR_EL2.TVM is set. + * + * Note that it only traps NS write access from EL1. + */ +#define TVM_REG(reg) \ +static bool vreg_emulate_##reg(struct cpu_user_regs *regs, \ + uint64_t *r, bool read) \ +{ \ + GUEST_BUG_ON(read); \ + WRITE_SYSREG64(*r, reg); \ + \ + return true; \ +} + +/* Defining helpers for emulating sysreg registers. */ +TVM_REG(SCTLR_EL1) +TVM_REG(TTBR0_EL1) +TVM_REG(TTBR1_EL1) +TVM_REG(TCR_EL1) +TVM_REG(ESR_EL1) +TVM_REG(FAR_EL1) +TVM_REG(AFSR0_EL1) +TVM_REG(AFSR1_EL1) +TVM_REG(MAIR_EL1) +TVM_REG(AMAIR_EL1) +TVM_REG(CONTEXTIDR_EL1) + +/* Macro to generate easily case for co-processor emulation */ +#define GENERATE_CASE(reg) \ + case HSR_SYSREG_##reg: \ + { \ + bool res; \ + \ + res = vreg_emulate_sysreg64(regs, hsr, vreg_emulate_##reg); \ + ASSERT(res); \ + break; \ + } + void do_sysreg(struct cpu_user_regs *regs, const union hsr hsr) { @@ -44,6 +84,23 @@ void do_sysreg(struct cpu_user_regs *regs, break; /* + * HCR_EL2.TVM + * + * ARMv8 (DDI 0487B.b): Table D1-37 + */ + GENERATE_CASE(SCTLR_EL1) + GENERATE_CASE(TTBR0_EL1) + GENERATE_CASE(TTBR1_EL1) + GENERATE_CASE(TCR_EL1) + GENERATE_CASE(ESR_EL1) + GENERATE_CASE(FAR_EL1) + GENERATE_CASE(AFSR0_EL1) + GENERATE_CASE(AFSR1_EL1) + GENERATE_CASE(MAIR_EL1) + GENERATE_CASE(AMAIR_EL1) + GENERATE_CASE(CONTEXTIDR_EL1) + + /* * MDCR_EL2.TDRA * * ARMv8 (DDI 0487A.d): D1-1508 Table D1-57