diff --git a/xen/arch/arm/arm64/traps.c b/xen/arch/arm/arm64/traps.c
index e5240190e6..babfc1d884 100644
--- a/xen/arch/arm/arm64/traps.c
+++ b/xen/arch/arm/arm64/traps.c
@@ -18,6 +18,7 @@
 
 #include <xen/lib.h>
 
+#include <asm/hsr.h>
 #include <asm/system.h>
 #include <asm/processor.h>
 
diff --git a/xen/arch/arm/traps.c b/xen/arch/arm/traps.c
index b9323672fc..0b8d342c1a 100644
--- a/xen/arch/arm/traps.c
+++ b/xen/arch/arm/traps.c
@@ -43,6 +43,7 @@
 #include <asm/debugger.h>
 #include <asm/event.h>
 #include <asm/flushtlb.h>
+#include <asm/hsr.h>
 #include <asm/mmio.h>
 #include <asm/monitor.h>
 #include <asm/psci.h>
diff --git a/xen/include/asm-arm/arm64/hsr.h b/xen/include/asm-arm/arm64/hsr.h
new file mode 100644
index 0000000000..ca931dd2fe
--- /dev/null
+++ b/xen/include/asm-arm/arm64/hsr.h
@@ -0,0 +1,122 @@
+#ifndef __ASM_ARM_ARM64_HSR_H
+#define __ASM_ARM_ARM64_HSR_H
+
+/* AArch 64 System Register Encodings */
+#define __HSR_SYSREG_c0  0
+#define __HSR_SYSREG_c1  1
+#define __HSR_SYSREG_c2  2
+#define __HSR_SYSREG_c3  3
+#define __HSR_SYSREG_c4  4
+#define __HSR_SYSREG_c5  5
+#define __HSR_SYSREG_c6  6
+#define __HSR_SYSREG_c7  7
+#define __HSR_SYSREG_c8  8
+#define __HSR_SYSREG_c9  9
+#define __HSR_SYSREG_c10 10
+#define __HSR_SYSREG_c11 11
+#define __HSR_SYSREG_c12 12
+#define __HSR_SYSREG_c13 13
+#define __HSR_SYSREG_c14 14
+#define __HSR_SYSREG_c15 15
+
+#define __HSR_SYSREG_0   0
+#define __HSR_SYSREG_1   1
+#define __HSR_SYSREG_2   2
+#define __HSR_SYSREG_3   3
+#define __HSR_SYSREG_4   4
+#define __HSR_SYSREG_5   5
+#define __HSR_SYSREG_6   6
+#define __HSR_SYSREG_7   7
+
+/* These are used to decode traps with HSR.EC==HSR_EC_SYSREG */
+#define HSR_SYSREG(op0,op1,crn,crm,op2) \
+    (((__HSR_SYSREG_##op0) << HSR_SYSREG_OP0_SHIFT) | \
+     ((__HSR_SYSREG_##op1) << HSR_SYSREG_OP1_SHIFT) | \
+     ((__HSR_SYSREG_##crn) << HSR_SYSREG_CRN_SHIFT) | \
+     ((__HSR_SYSREG_##crm) << HSR_SYSREG_CRM_SHIFT) | \
+     ((__HSR_SYSREG_##op2) << HSR_SYSREG_OP2_SHIFT))
+
+#define HSR_SYSREG_DCISW          HSR_SYSREG(1,0,c7,c6,2)
+#define HSR_SYSREG_DCCSW          HSR_SYSREG(1,0,c7,c10,2)
+#define HSR_SYSREG_DCCISW         HSR_SYSREG(1,0,c7,c14,2)
+
+#define HSR_SYSREG_MDSCR_EL1      HSR_SYSREG(2,0,c0,c2,2)
+#define HSR_SYSREG_MDRAR_EL1      HSR_SYSREG(2,0,c1,c0,0)
+#define HSR_SYSREG_OSLAR_EL1      HSR_SYSREG(2,0,c1,c0,4)
+#define HSR_SYSREG_OSLSR_EL1      HSR_SYSREG(2,0,c1,c1,4)
+#define HSR_SYSREG_OSDLR_EL1      HSR_SYSREG(2,0,c1,c3,4)
+#define HSR_SYSREG_DBGPRCR_EL1    HSR_SYSREG(2,0,c1,c4,4)
+#define HSR_SYSREG_MDCCSR_EL0     HSR_SYSREG(2,3,c0,c1,0)
+
+#define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4)
+#define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5)
+#define HSR_SYSREG_DBGWVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,6)
+#define HSR_SYSREG_DBGWCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,7)
+
+#define HSR_SYSREG_DBG_CASES(REG) case HSR_SYSREG_##REG##n_EL1(0):  \
+                                  case HSR_SYSREG_##REG##n_EL1(1):  \
+                                  case HSR_SYSREG_##REG##n_EL1(2):  \
+                                  case HSR_SYSREG_##REG##n_EL1(3):  \
+                                  case HSR_SYSREG_##REG##n_EL1(4):  \
+                                  case HSR_SYSREG_##REG##n_EL1(5):  \
+                                  case HSR_SYSREG_##REG##n_EL1(6):  \
+                                  case HSR_SYSREG_##REG##n_EL1(7):  \
+                                  case HSR_SYSREG_##REG##n_EL1(8):  \
+                                  case HSR_SYSREG_##REG##n_EL1(9):  \
+                                  case HSR_SYSREG_##REG##n_EL1(10): \
+                                  case HSR_SYSREG_##REG##n_EL1(11): \
+                                  case HSR_SYSREG_##REG##n_EL1(12): \
+                                  case HSR_SYSREG_##REG##n_EL1(13): \
+                                  case HSR_SYSREG_##REG##n_EL1(14): \
+                                  case HSR_SYSREG_##REG##n_EL1(15)
+
+#define HSR_SYSREG_SCTLR_EL1      HSR_SYSREG(3,0,c1, c0,0)
+#define HSR_SYSREG_ACTLR_EL1      HSR_SYSREG(3,0,c1, c0,1)
+#define HSR_SYSREG_TTBR0_EL1      HSR_SYSREG(3,0,c2, c0,0)
+#define HSR_SYSREG_TTBR1_EL1      HSR_SYSREG(3,0,c2, c0,1)
+#define HSR_SYSREG_TCR_EL1        HSR_SYSREG(3,0,c2, c0,2)
+#define HSR_SYSREG_AFSR0_EL1      HSR_SYSREG(3,0,c5, c1,0)
+#define HSR_SYSREG_AFSR1_EL1      HSR_SYSREG(3,0,c5, c1,1)
+#define HSR_SYSREG_ESR_EL1        HSR_SYSREG(3,0,c5, c2,0)
+#define HSR_SYSREG_FAR_EL1        HSR_SYSREG(3,0,c6, c0,0)
+#define HSR_SYSREG_PMINTENSET_EL1 HSR_SYSREG(3,0,c9,c14,1)
+#define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2)
+#define HSR_SYSREG_MAIR_EL1       HSR_SYSREG(3,0,c10,c2,0)
+#define HSR_SYSREG_AMAIR_EL1      HSR_SYSREG(3,0,c10,c3,0)
+#define HSR_SYSREG_ICC_SGI1R_EL1  HSR_SYSREG(3,0,c12,c11,5)
+#define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6)
+#define HSR_SYSREG_ICC_SGI0R_EL1  HSR_SYSREG(3,2,c12,c11,7)
+#define HSR_SYSREG_ICC_SRE_EL1    HSR_SYSREG(3,0,c12,c12,5)
+#define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
+
+#define HSR_SYSREG_PMCR_EL0       HSR_SYSREG(3,3,c9,c12,0)
+#define HSR_SYSREG_PMCNTENSET_EL0 HSR_SYSREG(3,3,c9,c12,1)
+#define HSR_SYSREG_PMCNTENCLR_EL0 HSR_SYSREG(3,3,c9,c12,2)
+#define HSR_SYSREG_PMOVSCLR_EL0   HSR_SYSREG(3,3,c9,c12,3)
+#define HSR_SYSREG_PMSWINC_EL0    HSR_SYSREG(3,3,c9,c12,4)
+#define HSR_SYSREG_PMSELR_EL0     HSR_SYSREG(3,3,c9,c12,5)
+#define HSR_SYSREG_PMCEID0_EL0    HSR_SYSREG(3,3,c9,c12,6)
+#define HSR_SYSREG_PMCEID1_EL0    HSR_SYSREG(3,3,c9,c12,7)
+
+#define HSR_SYSREG_PMCCNTR_EL0    HSR_SYSREG(3,3,c9,c13,0)
+#define HSR_SYSREG_PMXEVTYPER_EL0 HSR_SYSREG(3,3,c9,c13,1)
+#define HSR_SYSREG_PMXEVCNTR_EL0  HSR_SYSREG(3,3,c9,c13,2)
+
+#define HSR_SYSREG_PMUSERENR_EL0  HSR_SYSREG(3,3,c9,c14,0)
+#define HSR_SYSREG_PMOVSSET_EL0   HSR_SYSREG(3,3,c9,c14,3)
+
+#define HSR_SYSREG_CNTPCT_EL0     HSR_SYSREG(3,3,c14,c0,0)
+#define HSR_SYSREG_CNTP_TVAL_EL0  HSR_SYSREG(3,3,c14,c2,0)
+#define HSR_SYSREG_CNTP_CTL_EL0   HSR_SYSREG(3,3,c14,c2,1)
+#define HSR_SYSREG_CNTP_CVAL_EL0  HSR_SYSREG(3,3,c14,c2,2)
+
+#endif /* __ASM_ARM_ARM64_HSR_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/arm64/sysregs.h b/xen/include/asm-arm/arm64/sysregs.h
index 1811234249..f510925a2a 100644
--- a/xen/include/asm-arm/arm64/sysregs.h
+++ b/xen/include/asm-arm/arm64/sysregs.h
@@ -3,115 +3,6 @@
 
 #include <xen/stringify.h>
 
-/* AArch 64 System Register Encodings */
-#define __HSR_SYSREG_c0  0
-#define __HSR_SYSREG_c1  1
-#define __HSR_SYSREG_c2  2
-#define __HSR_SYSREG_c3  3
-#define __HSR_SYSREG_c4  4
-#define __HSR_SYSREG_c5  5
-#define __HSR_SYSREG_c6  6
-#define __HSR_SYSREG_c7  7
-#define __HSR_SYSREG_c8  8
-#define __HSR_SYSREG_c9  9
-#define __HSR_SYSREG_c10 10
-#define __HSR_SYSREG_c11 11
-#define __HSR_SYSREG_c12 12
-#define __HSR_SYSREG_c13 13
-#define __HSR_SYSREG_c14 14
-#define __HSR_SYSREG_c15 15
-
-#define __HSR_SYSREG_0   0
-#define __HSR_SYSREG_1   1
-#define __HSR_SYSREG_2   2
-#define __HSR_SYSREG_3   3
-#define __HSR_SYSREG_4   4
-#define __HSR_SYSREG_5   5
-#define __HSR_SYSREG_6   6
-#define __HSR_SYSREG_7   7
-
-/* These are used to decode traps with HSR.EC==HSR_EC_SYSREG */
-#define HSR_SYSREG(op0,op1,crn,crm,op2) \
-    (((__HSR_SYSREG_##op0) << HSR_SYSREG_OP0_SHIFT) | \
-     ((__HSR_SYSREG_##op1) << HSR_SYSREG_OP1_SHIFT) | \
-     ((__HSR_SYSREG_##crn) << HSR_SYSREG_CRN_SHIFT) | \
-     ((__HSR_SYSREG_##crm) << HSR_SYSREG_CRM_SHIFT) | \
-     ((__HSR_SYSREG_##op2) << HSR_SYSREG_OP2_SHIFT))
-
-#define HSR_SYSREG_DCISW          HSR_SYSREG(1,0,c7,c6,2)
-#define HSR_SYSREG_DCCSW          HSR_SYSREG(1,0,c7,c10,2)
-#define HSR_SYSREG_DCCISW         HSR_SYSREG(1,0,c7,c14,2)
-
-#define HSR_SYSREG_MDSCR_EL1      HSR_SYSREG(2,0,c0,c2,2)
-#define HSR_SYSREG_MDRAR_EL1      HSR_SYSREG(2,0,c1,c0,0)
-#define HSR_SYSREG_OSLAR_EL1      HSR_SYSREG(2,0,c1,c0,4)
-#define HSR_SYSREG_OSLSR_EL1      HSR_SYSREG(2,0,c1,c1,4)
-#define HSR_SYSREG_OSDLR_EL1      HSR_SYSREG(2,0,c1,c3,4)
-#define HSR_SYSREG_DBGPRCR_EL1    HSR_SYSREG(2,0,c1,c4,4)
-#define HSR_SYSREG_MDCCSR_EL0     HSR_SYSREG(2,3,c0,c1,0)
-
-#define HSR_SYSREG_DBGBVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,4)
-#define HSR_SYSREG_DBGBCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,5)
-#define HSR_SYSREG_DBGWVRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,6)
-#define HSR_SYSREG_DBGWCRn_EL1(n) HSR_SYSREG(2,0,c0,c##n,7)
-
-#define HSR_SYSREG_DBG_CASES(REG) case HSR_SYSREG_##REG##n_EL1(0):  \
-                                  case HSR_SYSREG_##REG##n_EL1(1):  \
-                                  case HSR_SYSREG_##REG##n_EL1(2):  \
-                                  case HSR_SYSREG_##REG##n_EL1(3):  \
-                                  case HSR_SYSREG_##REG##n_EL1(4):  \
-                                  case HSR_SYSREG_##REG##n_EL1(5):  \
-                                  case HSR_SYSREG_##REG##n_EL1(6):  \
-                                  case HSR_SYSREG_##REG##n_EL1(7):  \
-                                  case HSR_SYSREG_##REG##n_EL1(8):  \
-                                  case HSR_SYSREG_##REG##n_EL1(9):  \
-                                  case HSR_SYSREG_##REG##n_EL1(10): \
-                                  case HSR_SYSREG_##REG##n_EL1(11): \
-                                  case HSR_SYSREG_##REG##n_EL1(12): \
-                                  case HSR_SYSREG_##REG##n_EL1(13): \
-                                  case HSR_SYSREG_##REG##n_EL1(14): \
-                                  case HSR_SYSREG_##REG##n_EL1(15)
-
-#define HSR_SYSREG_SCTLR_EL1      HSR_SYSREG(3,0,c1, c0,0)
-#define HSR_SYSREG_ACTLR_EL1      HSR_SYSREG(3,0,c1, c0,1)
-#define HSR_SYSREG_TTBR0_EL1      HSR_SYSREG(3,0,c2, c0,0)
-#define HSR_SYSREG_TTBR1_EL1      HSR_SYSREG(3,0,c2, c0,1)
-#define HSR_SYSREG_TCR_EL1        HSR_SYSREG(3,0,c2, c0,2)
-#define HSR_SYSREG_AFSR0_EL1      HSR_SYSREG(3,0,c5, c1,0)
-#define HSR_SYSREG_AFSR1_EL1      HSR_SYSREG(3,0,c5, c1,1)
-#define HSR_SYSREG_ESR_EL1        HSR_SYSREG(3,0,c5, c2,0)
-#define HSR_SYSREG_FAR_EL1        HSR_SYSREG(3,0,c6, c0,0)
-#define HSR_SYSREG_PMINTENSET_EL1 HSR_SYSREG(3,0,c9,c14,1)
-#define HSR_SYSREG_PMINTENCLR_EL1 HSR_SYSREG(3,0,c9,c14,2)
-#define HSR_SYSREG_MAIR_EL1       HSR_SYSREG(3,0,c10,c2,0)
-#define HSR_SYSREG_AMAIR_EL1      HSR_SYSREG(3,0,c10,c3,0)
-#define HSR_SYSREG_ICC_SGI1R_EL1  HSR_SYSREG(3,0,c12,c11,5)
-#define HSR_SYSREG_ICC_ASGI1R_EL1 HSR_SYSREG(3,1,c12,c11,6)
-#define HSR_SYSREG_ICC_SGI0R_EL1  HSR_SYSREG(3,2,c12,c11,7)
-#define HSR_SYSREG_ICC_SRE_EL1    HSR_SYSREG(3,0,c12,c12,5)
-#define HSR_SYSREG_CONTEXTIDR_EL1 HSR_SYSREG(3,0,c13,c0,1)
-
-#define HSR_SYSREG_PMCR_EL0       HSR_SYSREG(3,3,c9,c12,0)
-#define HSR_SYSREG_PMCNTENSET_EL0 HSR_SYSREG(3,3,c9,c12,1)
-#define HSR_SYSREG_PMCNTENCLR_EL0 HSR_SYSREG(3,3,c9,c12,2)
-#define HSR_SYSREG_PMOVSCLR_EL0   HSR_SYSREG(3,3,c9,c12,3)
-#define HSR_SYSREG_PMSWINC_EL0    HSR_SYSREG(3,3,c9,c12,4)
-#define HSR_SYSREG_PMSELR_EL0     HSR_SYSREG(3,3,c9,c12,5)
-#define HSR_SYSREG_PMCEID0_EL0    HSR_SYSREG(3,3,c9,c12,6)
-#define HSR_SYSREG_PMCEID1_EL0    HSR_SYSREG(3,3,c9,c12,7)
-
-#define HSR_SYSREG_PMCCNTR_EL0    HSR_SYSREG(3,3,c9,c13,0)
-#define HSR_SYSREG_PMXEVTYPER_EL0 HSR_SYSREG(3,3,c9,c13,1)
-#define HSR_SYSREG_PMXEVCNTR_EL0  HSR_SYSREG(3,3,c9,c13,2)
-
-#define HSR_SYSREG_PMUSERENR_EL0  HSR_SYSREG(3,3,c9,c14,0)
-#define HSR_SYSREG_PMOVSSET_EL0   HSR_SYSREG(3,3,c9,c14,3)
-
-#define HSR_SYSREG_CNTPCT_EL0     HSR_SYSREG(3,3,c14,c0,0)
-#define HSR_SYSREG_CNTP_TVAL_EL0  HSR_SYSREG(3,3,c14,c2,0)
-#define HSR_SYSREG_CNTP_CTL_EL0   HSR_SYSREG(3,3,c14,c2,1)
-#define HSR_SYSREG_CNTP_CVAL_EL0  HSR_SYSREG(3,3,c14,c2,2)
-
 /*
  * GIC System register assembly aliases picked from kernel
  */
diff --git a/xen/include/asm-arm/hsr.h b/xen/include/asm-arm/hsr.h
new file mode 100644
index 0000000000..29d4531f40
--- /dev/null
+++ b/xen/include/asm-arm/hsr.h
@@ -0,0 +1,217 @@
+#ifndef __ASM_ARM_HSR_H
+#define __ASM_ARM_HSR_H
+
+#include <xen/types.h>
+
+#if defined(CONFIG_ARM_64)
+# include <asm/arm64/hsr.h>
+#endif
+
+/* HSR data abort size definition */
+enum dabt_size {
+    DABT_BYTE        = 0,
+    DABT_HALF_WORD   = 1,
+    DABT_WORD        = 2,
+    DABT_DOUBLE_WORD = 3,
+};
+
+union hsr {
+    uint32_t bits;
+    struct {
+        unsigned long iss:25;  /* Instruction Specific Syndrome */
+        unsigned long len:1;   /* Instruction length */
+        unsigned long ec:6;    /* Exception Class */
+    };
+
+    /* Common to all conditional exception classes (0x0N, except 0x00). */
+    struct hsr_cond {
+        unsigned long iss:20;  /* Instruction Specific Syndrome */
+        unsigned long cc:4;    /* Condition Code */
+        unsigned long ccvalid:1;/* CC Valid */
+        unsigned long len:1;   /* Instruction length */
+        unsigned long ec:6;    /* Exception Class */
+    } cond;
+
+    struct hsr_wfi_wfe {
+        unsigned long ti:1;    /* Trapped instruction */
+        unsigned long sbzp:19;
+        unsigned long cc:4;    /* Condition Code */
+        unsigned long ccvalid:1;/* CC Valid */
+        unsigned long len:1;   /* Instruction length */
+        unsigned long ec:6;    /* Exception Class */
+    } wfi_wfe;
+
+    /* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */
+    struct hsr_cp32 {
+        unsigned long read:1;  /* Direction */
+        unsigned long crm:4;   /* CRm */
+        unsigned long reg:5;   /* Rt */
+        unsigned long crn:4;   /* CRn */
+        unsigned long op1:3;   /* Op1 */
+        unsigned long op2:3;   /* Op2 */
+        unsigned long cc:4;    /* Condition Code */
+        unsigned long ccvalid:1;/* CC Valid */
+        unsigned long len:1;   /* Instruction length */
+        unsigned long ec:6;    /* Exception Class */
+    } cp32; /* HSR_EC_CP15_32, CP14_32, CP10 */
+
+    struct hsr_cp64 {
+        unsigned long read:1;   /* Direction */
+        unsigned long crm:4;    /* CRm */
+        unsigned long reg1:5;   /* Rt1 */
+        unsigned long reg2:5;   /* Rt2 */
+        unsigned long sbzp2:1;
+        unsigned long op1:4;    /* Op1 */
+        unsigned long cc:4;     /* Condition Code */
+        unsigned long ccvalid:1;/* CC Valid */
+        unsigned long len:1;    /* Instruction length */
+        unsigned long ec:6;     /* Exception Class */
+    } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */
+
+     struct hsr_cp {
+        unsigned long coproc:4; /* Number of coproc accessed */
+        unsigned long sbz0p:1;
+        unsigned long tas:1;    /* Trapped Advanced SIMD */
+        unsigned long res0:14;
+        unsigned long cc:4;     /* Condition Code */
+        unsigned long ccvalid:1;/* CC Valid */
+        unsigned long len:1;    /* Instruction length */
+        unsigned long ec:6;     /* Exception Class */
+    } cp; /* HSR_EC_CP */
+
+    /*
+     * This encoding is valid only for ARMv8 (ARM DDI 0487B.a, pages D7-2271 and
+     * G6-4957). On ARMv7, encoding ISS for EC=0x13 is defined as UNK/SBZP
+     * (ARM DDI 0406C.c page B3-1431). UNK/SBZP means that hardware implements
+     * this field as Read-As-Zero. ARMv8 is backwards compatible with ARMv7:
+     * reading CCKNOWNPASS on ARMv7 will return 0, which means that condition
+     * check was passed or instruction was unconditional.
+     */
+    struct hsr_smc32 {
+        unsigned long res0:19;  /* Reserved */
+        unsigned long ccknownpass:1; /* Instruction passed conditional check */
+        unsigned long cc:4;    /* Condition Code */
+        unsigned long ccvalid:1;/* CC Valid */
+        unsigned long len:1;   /* Instruction length */
+        unsigned long ec:6;    /* Exception Class */
+    } smc32; /* HSR_EC_SMC32 */
+
+#ifdef CONFIG_ARM_64
+    struct hsr_sysreg {
+        unsigned long read:1;   /* Direction */
+        unsigned long crm:4;    /* CRm */
+        unsigned long reg:5;    /* Rt */
+        unsigned long crn:4;    /* CRn */
+        unsigned long op1:3;    /* Op1 */
+        unsigned long op2:3;    /* Op2 */
+        unsigned long op0:2;    /* Op0 */
+        unsigned long res0:3;
+        unsigned long len:1;    /* Instruction length */
+        unsigned long ec:6;
+    } sysreg; /* HSR_EC_SYSREG */
+#endif
+
+    struct hsr_iabt {
+        unsigned long ifsc:6;  /* Instruction fault status code */
+        unsigned long res0:1;  /* RES0 */
+        unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
+        unsigned long res1:1;  /* RES0 */
+        unsigned long eat:1;   /* External abort type */
+        unsigned long fnv:1;   /* FAR not Valid */
+        unsigned long res2:14;
+        unsigned long len:1;   /* Instruction length */
+        unsigned long ec:6;    /* Exception Class */
+    } iabt; /* HSR_EC_INSTR_ABORT_* */
+
+    struct hsr_dabt {
+        unsigned long dfsc:6;  /* Data Fault Status Code */
+        unsigned long write:1; /* Write / not Read */
+        unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
+        unsigned long cache:1; /* Cache Maintenance */
+        unsigned long eat:1;   /* External Abort Type */
+        unsigned long fnv:1;   /* FAR not Valid */
+#ifdef CONFIG_ARM_32
+        unsigned long sbzp0:5;
+#else
+        unsigned long sbzp0:3;
+        unsigned long ar:1;    /* Acquire Release */
+        unsigned long sf:1;    /* Sixty Four bit register */
+#endif
+        unsigned long reg:5;   /* Register */
+        unsigned long sign:1;  /* Sign extend */
+        unsigned long size:2;  /* Access Size */
+        unsigned long valid:1; /* Syndrome Valid */
+        unsigned long len:1;   /* Instruction length */
+        unsigned long ec:6;    /* Exception Class */
+    } dabt; /* HSR_EC_DATA_ABORT_* */
+
+    /* Contain the common bits between DABT and IABT */
+    struct hsr_xabt {
+        unsigned long fsc:6;    /* Fault status code */
+        unsigned long pad1:1;   /* Not common */
+        unsigned long s1ptw:1;  /* Stage 2 fault during stage 1 translation */
+        unsigned long pad2:1;   /* Not common */
+        unsigned long eat:1;    /* External abort type */
+        unsigned long fnv:1;    /* FAR not Valid */
+        unsigned long pad3:14;  /* Not common */
+        unsigned long len:1;    /* Instruction length */
+        unsigned long ec:6;     /* Exception Class */
+    } xabt;
+
+#ifdef CONFIG_ARM_64
+    struct hsr_brk {
+        unsigned long comment:16;   /* Comment */
+        unsigned long res0:9;
+        unsigned long len:1;        /* Instruction length */
+        unsigned long ec:6;         /* Exception Class */
+    } brk;
+#endif
+};
+
+/* HSR.EC == HSR_CP{15,14,10}_32 */
+#define HSR_CP32_OP2_MASK (0x000e0000)
+#define HSR_CP32_OP2_SHIFT (17)
+#define HSR_CP32_OP1_MASK (0x0001c000)
+#define HSR_CP32_OP1_SHIFT (14)
+#define HSR_CP32_CRN_MASK (0x00003c00)
+#define HSR_CP32_CRN_SHIFT (10)
+#define HSR_CP32_CRM_MASK (0x0000001e)
+#define HSR_CP32_CRM_SHIFT (1)
+#define HSR_CP32_REGS_MASK (HSR_CP32_OP1_MASK|HSR_CP32_OP2_MASK|\
+                            HSR_CP32_CRN_MASK|HSR_CP32_CRM_MASK)
+
+/* HSR.EC == HSR_CP{15,14}_64 */
+#define HSR_CP64_OP1_MASK (0x000f0000)
+#define HSR_CP64_OP1_SHIFT (16)
+#define HSR_CP64_CRM_MASK (0x0000001e)
+#define HSR_CP64_CRM_SHIFT (1)
+#define HSR_CP64_REGS_MASK (HSR_CP64_OP1_MASK|HSR_CP64_CRM_MASK)
+
+/* HSR.EC == HSR_SYSREG */
+#define HSR_SYSREG_OP0_MASK (0x00300000)
+#define HSR_SYSREG_OP0_SHIFT (20)
+#define HSR_SYSREG_OP1_MASK (0x0001c000)
+#define HSR_SYSREG_OP1_SHIFT (14)
+#define HSR_SYSREG_CRN_MASK (0x00003c00)
+#define HSR_SYSREG_CRN_SHIFT (10)
+#define HSR_SYSREG_CRM_MASK (0x0000001e)
+#define HSR_SYSREG_CRM_SHIFT (1)
+#define HSR_SYSREG_OP2_MASK (0x000e0000)
+#define HSR_SYSREG_OP2_SHIFT (17)
+#define HSR_SYSREG_REGS_MASK (HSR_SYSREG_OP0_MASK|HSR_SYSREG_OP1_MASK|\
+                              HSR_SYSREG_CRN_MASK|HSR_SYSREG_CRM_MASK|\
+                              HSR_SYSREG_OP2_MASK)
+
+/* HSR.EC == HSR_{HVC32, HVC64, SMC64, SVC32, SVC64} */
+#define HSR_XXC_IMM_MASK     (0xffff)
+
+#endif /* __ASM_ARM_HSR_H */
+
+/*
+ * Local variables:
+ * mode: C
+ * c-file-style: "BSD"
+ * c-basic-offset: 4
+ * indent-tabs-mode: nil
+ * End:
+ */
diff --git a/xen/include/asm-arm/mmio.h b/xen/include/asm-arm/mmio.h
index c8dadb5006..3ed3f82bf7 100644
--- a/xen/include/asm-arm/mmio.h
+++ b/xen/include/asm-arm/mmio.h
@@ -21,6 +21,8 @@
 
 #include <xen/lib.h>
 #include <xen/rwlock.h>
+
+#include <asm/hsr.h>
 #include <asm/processor.h>
 #include <asm/regs.h>
 
diff --git a/xen/include/asm-arm/processor.h b/xen/include/asm-arm/processor.h
index 3f40468bfd..b64ea4e8e4 100644
--- a/xen/include/asm-arm/processor.h
+++ b/xen/include/asm-arm/processor.h
@@ -353,207 +353,8 @@
 extern register_t __cpu_logical_map[];
 #define cpu_logical_map(cpu) __cpu_logical_map[cpu]
 
-/* HSR data abort size definition */
-enum dabt_size {
-    DABT_BYTE        = 0,
-    DABT_HALF_WORD   = 1,
-    DABT_WORD        = 2,
-    DABT_DOUBLE_WORD = 3,
-};
-
-union hsr {
-    uint32_t bits;
-    struct {
-        unsigned long iss:25;  /* Instruction Specific Syndrome */
-        unsigned long len:1;   /* Instruction length */
-        unsigned long ec:6;    /* Exception Class */
-    };
-
-    /* Common to all conditional exception classes (0x0N, except 0x00). */
-    struct hsr_cond {
-        unsigned long iss:20;  /* Instruction Specific Syndrome */
-        unsigned long cc:4;    /* Condition Code */
-        unsigned long ccvalid:1;/* CC Valid */
-        unsigned long len:1;   /* Instruction length */
-        unsigned long ec:6;    /* Exception Class */
-    } cond;
-
-    struct hsr_wfi_wfe {
-        unsigned long ti:1;    /* Trapped instruction */
-        unsigned long sbzp:19;
-        unsigned long cc:4;    /* Condition Code */
-        unsigned long ccvalid:1;/* CC Valid */
-        unsigned long len:1;   /* Instruction length */
-        unsigned long ec:6;    /* Exception Class */
-    } wfi_wfe;
-
-    /* reg, reg0, reg1 are 4 bits on AArch32, the fifth bit is sbzp. */
-    struct hsr_cp32 {
-        unsigned long read:1;  /* Direction */
-        unsigned long crm:4;   /* CRm */
-        unsigned long reg:5;   /* Rt */
-        unsigned long crn:4;   /* CRn */
-        unsigned long op1:3;   /* Op1 */
-        unsigned long op2:3;   /* Op2 */
-        unsigned long cc:4;    /* Condition Code */
-        unsigned long ccvalid:1;/* CC Valid */
-        unsigned long len:1;   /* Instruction length */
-        unsigned long ec:6;    /* Exception Class */
-    } cp32; /* HSR_EC_CP15_32, CP14_32, CP10 */
-
-    struct hsr_cp64 {
-        unsigned long read:1;   /* Direction */
-        unsigned long crm:4;    /* CRm */
-        unsigned long reg1:5;   /* Rt1 */
-        unsigned long reg2:5;   /* Rt2 */
-        unsigned long sbzp2:1;
-        unsigned long op1:4;    /* Op1 */
-        unsigned long cc:4;     /* Condition Code */
-        unsigned long ccvalid:1;/* CC Valid */
-        unsigned long len:1;    /* Instruction length */
-        unsigned long ec:6;     /* Exception Class */
-    } cp64; /* HSR_EC_CP15_64, HSR_EC_CP14_64 */
-
-     struct hsr_cp {
-        unsigned long coproc:4; /* Number of coproc accessed */
-        unsigned long sbz0p:1;
-        unsigned long tas:1;    /* Trapped Advanced SIMD */
-        unsigned long res0:14;
-        unsigned long cc:4;     /* Condition Code */
-        unsigned long ccvalid:1;/* CC Valid */
-        unsigned long len:1;    /* Instruction length */
-        unsigned long ec:6;     /* Exception Class */
-    } cp; /* HSR_EC_CP */
-
-    /*
-     * This encoding is valid only for ARMv8 (ARM DDI 0487B.a, pages D7-2271 and
-     * G6-4957). On ARMv7, encoding ISS for EC=0x13 is defined as UNK/SBZP
-     * (ARM DDI 0406C.c page B3-1431). UNK/SBZP means that hardware implements
-     * this field as Read-As-Zero. ARMv8 is backwards compatible with ARMv7:
-     * reading CCKNOWNPASS on ARMv7 will return 0, which means that condition
-     * check was passed or instruction was unconditional.
-     */
-    struct hsr_smc32 {
-        unsigned long res0:19;  /* Reserved */
-        unsigned long ccknownpass:1; /* Instruction passed conditional check */
-        unsigned long cc:4;    /* Condition Code */
-        unsigned long ccvalid:1;/* CC Valid */
-        unsigned long len:1;   /* Instruction length */
-        unsigned long ec:6;    /* Exception Class */
-    } smc32; /* HSR_EC_SMC32 */
-
-#ifdef CONFIG_ARM_64
-    struct hsr_sysreg {
-        unsigned long read:1;   /* Direction */
-        unsigned long crm:4;    /* CRm */
-        unsigned long reg:5;    /* Rt */
-        unsigned long crn:4;    /* CRn */
-        unsigned long op1:3;    /* Op1 */
-        unsigned long op2:3;    /* Op2 */
-        unsigned long op0:2;    /* Op0 */
-        unsigned long res0:3;
-        unsigned long len:1;    /* Instruction length */
-        unsigned long ec:6;
-    } sysreg; /* HSR_EC_SYSREG */
-#endif
-
-    struct hsr_iabt {
-        unsigned long ifsc:6;  /* Instruction fault status code */
-        unsigned long res0:1;  /* RES0 */
-        unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
-        unsigned long res1:1;  /* RES0 */
-        unsigned long eat:1;   /* External abort type */
-        unsigned long fnv:1;   /* FAR not Valid */
-        unsigned long res2:14;
-        unsigned long len:1;   /* Instruction length */
-        unsigned long ec:6;    /* Exception Class */
-    } iabt; /* HSR_EC_INSTR_ABORT_* */
-
-    struct hsr_dabt {
-        unsigned long dfsc:6;  /* Data Fault Status Code */
-        unsigned long write:1; /* Write / not Read */
-        unsigned long s1ptw:1; /* Stage 2 fault during stage 1 translation */
-        unsigned long cache:1; /* Cache Maintenance */
-        unsigned long eat:1;   /* External Abort Type */
-        unsigned long fnv:1;   /* FAR not Valid */
-#ifdef CONFIG_ARM_32
-        unsigned long sbzp0:5;
-#else
-        unsigned long sbzp0:3;
-        unsigned long ar:1;    /* Acquire Release */
-        unsigned long sf:1;    /* Sixty Four bit register */
-#endif
-        unsigned long reg:5;   /* Register */
-        unsigned long sign:1;  /* Sign extend */
-        unsigned long size:2;  /* Access Size */
-        unsigned long valid:1; /* Syndrome Valid */
-        unsigned long len:1;   /* Instruction length */
-        unsigned long ec:6;    /* Exception Class */
-    } dabt; /* HSR_EC_DATA_ABORT_* */
-
-    /* Contain the common bits between DABT and IABT */
-    struct hsr_xabt {
-        unsigned long fsc:6;    /* Fault status code */
-        unsigned long pad1:1;   /* Not common */
-        unsigned long s1ptw:1;  /* Stage 2 fault during stage 1 translation */
-        unsigned long pad2:1;   /* Not common */
-        unsigned long eat:1;    /* External abort type */
-        unsigned long fnv:1;    /* FAR not Valid */
-        unsigned long pad3:14;  /* Not common */
-        unsigned long len:1;    /* Instruction length */
-        unsigned long ec:6;     /* Exception Class */
-    } xabt;
-
-#ifdef CONFIG_ARM_64
-    struct hsr_brk {
-        unsigned long comment:16;   /* Comment */
-        unsigned long res0:9;
-        unsigned long len:1;        /* Instruction length */
-        unsigned long ec:6;         /* Exception Class */
-    } brk;
-#endif
-
-
-};
 #endif
 
-/* HSR.EC == HSR_CP{15,14,10}_32 */
-#define HSR_CP32_OP2_MASK (0x000e0000)
-#define HSR_CP32_OP2_SHIFT (17)
-#define HSR_CP32_OP1_MASK (0x0001c000)
-#define HSR_CP32_OP1_SHIFT (14)
-#define HSR_CP32_CRN_MASK (0x00003c00)
-#define HSR_CP32_CRN_SHIFT (10)
-#define HSR_CP32_CRM_MASK (0x0000001e)
-#define HSR_CP32_CRM_SHIFT (1)
-#define HSR_CP32_REGS_MASK (HSR_CP32_OP1_MASK|HSR_CP32_OP2_MASK|\
-                            HSR_CP32_CRN_MASK|HSR_CP32_CRM_MASK)
-
-/* HSR.EC == HSR_CP{15,14}_64 */
-#define HSR_CP64_OP1_MASK (0x000f0000)
-#define HSR_CP64_OP1_SHIFT (16)
-#define HSR_CP64_CRM_MASK (0x0000001e)
-#define HSR_CP64_CRM_SHIFT (1)
-#define HSR_CP64_REGS_MASK (HSR_CP64_OP1_MASK|HSR_CP64_CRM_MASK)
-
-/* HSR.EC == HSR_SYSREG */
-#define HSR_SYSREG_OP0_MASK (0x00300000)
-#define HSR_SYSREG_OP0_SHIFT (20)
-#define HSR_SYSREG_OP1_MASK (0x0001c000)
-#define HSR_SYSREG_OP1_SHIFT (14)
-#define HSR_SYSREG_CRN_MASK (0x00003c00)
-#define HSR_SYSREG_CRN_SHIFT (10)
-#define HSR_SYSREG_CRM_MASK (0x0000001e)
-#define HSR_SYSREG_CRM_SHIFT (1)
-#define HSR_SYSREG_OP2_MASK (0x000e0000)
-#define HSR_SYSREG_OP2_SHIFT (17)
-#define HSR_SYSREG_REGS_MASK (HSR_SYSREG_OP0_MASK|HSR_SYSREG_OP1_MASK|\
-                              HSR_SYSREG_CRN_MASK|HSR_SYSREG_CRM_MASK|\
-                              HSR_SYSREG_OP2_MASK)
-
-/* HSR.EC == HSR_{HVC32, HVC64, SMC64, SVC32, SVC64} */
-#define HSR_XXC_IMM_MASK     (0xffff)
-
 /* Physical Address Register */
 #define PAR_F           (_AC(1,U)<<0)
 
diff --git a/xen/include/asm-arm/traps.h b/xen/include/asm-arm/traps.h
index a0406b5a3c..589fba9cd0 100644
--- a/xen/include/asm-arm/traps.h
+++ b/xen/include/asm-arm/traps.h
@@ -1,6 +1,7 @@
 #ifndef __ASM_ARM_TRAPS__
 #define __ASM_ARM_TRAPS__
 
+#include <asm/hsr.h>
 #include <asm/processor.h>
 
 #if defined(CONFIG_ARM_32)
