From patchwork Mon Sep 10 11:35:00 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 146296 Delivered-To: patch@linaro.org Received: by 2002:a2e:1648:0:0:0:0:0 with SMTP id 8-v6csp2383278ljw; Mon, 10 Sep 2018 04:35:10 -0700 (PDT) X-Google-Smtp-Source: ANB0VdaYv4KoYWE7lHyAzwUa3kd+dDfZLgMHHWItb5+H55BvT7WKDRttdgqbhmQ/UhFou/atHEvD X-Received: by 2002:a1c:9ac9:: with SMTP id c192-v6mr438185wme.47.1536579310388; Mon, 10 Sep 2018 04:35:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1536579310; cv=none; d=google.com; s=arc-20160816; b=sAt3T4U+venivdYY4tLdToq8+LakXM0PMKNnXaLACHsS+wDpdNFEcCNm4l6Qo4X6qT sx/fvLkVbTtq6OTlw6o2L7LlhyBquBR30QYdVjim8oBxaY43WU/b7fCfEfhWDcojnli7 NhWliWsbkRRyGXP20pBZv/jhZTEvHY50JF6Id88egiHSc7PCtCs/mEg1XQ0QEg1PGiYR qcxqsDtDYSkzbxbpDGE8rKaYFno4o6FjoTFCAO/XOqtAtEs6QVKxw+3999DVClgMyQ7u nD40oVVUMwQPuyB6F4dHmY9tZ8mbFvylpLJsIbyrZU+ZUtkuD3i/uIV3JMe3CA7cqC6x 3hjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:content-transfer-encoding:mime-version :list-subscribe:list-help:list-post:list-archive:list-unsubscribe :list-id:precedence:subject:cc:date:message-id:in-reply-to:to:from :dkim-signature:delivered-to; bh=Fu20bDseEAhB9TkorsUYKQJA/XWtX7Ng8yp3lh09ujs=; b=UD8ZCMb6Co4+5I13iX86RMusrmGftJwv5l6hiGF412a45Xzn2/b8XGycXJ+AT5aCYN tZEEEyiiXq/uZDniO6GyUC/DPQtXp60dpsk3AicJkdMFp9CSEl0smf0NdBrvZatMABxa kMwwvTTMc/gwmxpj97h/3tayePinpzF+IyOkvxYvWN/TccDKxJNbGzDNNHRGp92CT1zH SkNfW6EVd+IxfwESNWLyTGE5t4Ka9XNZp+5B0vu3K7NJ03MLJxtRwdJ0yQYcn5ZQFj2M 6NIS2uSQegB7zMhnZi6tMmMY9/9MJvpXKAmYV2w/LN0c3QBfei7ByJy+2KYYIpuw4y1+ 8wiA== ARC-Authentication-Results: i=1; mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=Lk3avSO8; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Return-Path: Received: from alsa0.perex.cz (alsa0.perex.cz. [77.48.224.243]) by mx.google.com with ESMTP id e17-v6si15448496wro.203.2018.09.10.04.35.10; Mon, 10 Sep 2018 04:35:10 -0700 (PDT) Received-SPF: pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) client-ip=77.48.224.243; Authentication-Results: mx.google.com; dkim=neutral (body hash did not verify) header.i=@sirena.org.uk header.s=20170815-heliosphere header.b=Lk3avSO8; spf=pass (google.com: domain of alsa-devel-bounces@alsa-project.org designates 77.48.224.243 as permitted sender) smtp.mailfrom=alsa-devel-bounces@alsa-project.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=kernel.org Received: from alsa0.perex.cz (localhost [127.0.0.1]) by alsa0.perex.cz (Postfix) with ESMTP id 66F142677FD; Mon, 10 Sep 2018 13:35:08 +0200 (CEST) X-Original-To: alsa-devel@alsa-project.org Delivered-To: alsa-devel@alsa-project.org Received: by alsa0.perex.cz (Postfix, from userid 1000) id A0988267801; Mon, 10 Sep 2018 13:35:06 +0200 (CEST) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on mail1.perex.cz X-Spam-Level: X-Spam-Status: No, score=0.2 required=5.0 tests=DKIM_SIGNED,DKIM_VALID, HEADER_FROM_DIFFERENT_DOMAINS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=disabled version=3.4.0 Received: from heliosphere.sirena.org.uk (heliosphere.sirena.org.uk [172.104.155.198]) by alsa0.perex.cz (Postfix) with ESMTP id A830C2676ED for ; Mon, 10 Sep 2018 13:35:02 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=sirena.org.uk; s=20170815-heliosphere; h=Date:Message-Id:In-Reply-To: Subject:Cc:To:From:Sender:Reply-To:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Id:List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner: List-Archive; bh=9X8qssQ+w3DjNW3Lp/6D0PkXwJH/g1BONAtbjTopSXY=; b=Lk3avSO8ltGM tShW4qRb6+M8nbg7DQHbIN3zvsbVQh0MOesTY3zpNHJXfD4iUt4c1gQ/UfgA78tJLqYceLeaqAU70 fvcUDVYq3JKBVtflpds6M+UOIQmqrzasgfZZ8J9Fm7RoPKQ21x4oJQiRkY87A3ZVz/B1M8b7tUbXL PpfZ4=; Received: from cpc102320-sgyl38-2-0-cust46.18-2.cable.virginm.net ([82.37.168.47] helo=debutante.sirena.org.uk) by heliosphere.sirena.org.uk with esmtpa (Exim 4.89) (envelope-from ) id 1fzKT6-0001vT-H5; Mon, 10 Sep 2018 11:35:00 +0000 Received: by debutante.sirena.org.uk (Postfix, from userid 1000) id 2C25F1122D51; Mon, 10 Sep 2018 12:35:00 +0100 (BST) From: Mark Brown To: Akshu Agrawal In-Reply-To: <1536566815-3271-2-git-send-email-akshu.agrawal@amd.com> Message-Id: <20180910113500.2C25F1122D51@debutante.sirena.org.uk> Date: Mon, 10 Sep 2018 12:35:00 +0100 (BST) Cc: , alsa-devel@alsa-project.org, Takashi Iwai , Liam Girdwood , djkurtz@chromium.org, open list , Mark Brown , "Mukunda, , Vijendar" , Alex Deucher , akshu.agrawal@amd.com Subject: [alsa-devel] Applied "ASoC: AMD: Ensure reset bit is cleared before configuring" to the asoc tree X-BeenThere: alsa-devel@alsa-project.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: "Alsa-devel mailing list for ALSA developers - http://www.alsa-project.org" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: alsa-devel-bounces@alsa-project.org Sender: alsa-devel-bounces@alsa-project.org The patch ASoC: AMD: Ensure reset bit is cleared before configuring has been applied to the asoc tree at https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted. You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed. If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced. Please add any relevant lists and maintainers to the CCs when replying to this mail. Thanks, Mark >From 2a665dba016d5493c7d826fec82b0cb643b30d42 Mon Sep 17 00:00:00 2001 From: Akshu Agrawal Date: Mon, 10 Sep 2018 13:36:30 +0530 Subject: [PATCH] ASoC: AMD: Ensure reset bit is cleared before configuring HW register descriptions says: "DMA Channel Reset...Software must confirm that this bit is cleared before reprogramming any of the channel configuration registers." There could be cases where dma stop errored out leaving dma channel in reset state. We need to ensure that before the start of another dma, channel is out of the reset state. Signed-off-by: Akshu Agrawal Signed-off-by: Mark Brown --- sound/soc/amd/acp-pcm-dma.c | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) -- 2.19.0.rc1 _______________________________________________ Alsa-devel mailing list Alsa-devel@alsa-project.org http://mailman.alsa-project.org/mailman/listinfo/alsa-devel diff --git a/sound/soc/amd/acp-pcm-dma.c b/sound/soc/amd/acp-pcm-dma.c index e359938e3d7e..77b265bd0505 100644 --- a/sound/soc/amd/acp-pcm-dma.c +++ b/sound/soc/amd/acp-pcm-dma.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include @@ -184,6 +185,24 @@ static void config_dma_descriptor_in_sram(void __iomem *acp_mmio, acp_reg_write(descr_info->xfer_val, acp_mmio, mmACP_SRBM_Targ_Idx_Data); } +static void pre_config_reset(void __iomem *acp_mmio, u16 ch_num) +{ + u32 dma_ctrl; + int ret; + + /* clear the reset bit */ + dma_ctrl = acp_reg_read(acp_mmio, mmACP_DMA_CNTL_0 + ch_num); + dma_ctrl &= ~ACP_DMA_CNTL_0__DMAChRst_MASK; + acp_reg_write(dma_ctrl, acp_mmio, mmACP_DMA_CNTL_0 + ch_num); + /* check the reset bit before programming configuration registers */ + ret = readl_poll_timeout(acp_mmio + ((mmACP_DMA_CNTL_0 + ch_num) * 4), + dma_ctrl, + !(dma_ctrl & ACP_DMA_CNTL_0__DMAChRst_MASK), + 100, ACP_DMA_RESET_TIME); + if (ret < 0) + pr_err("Failed to clear reset of channel : %d\n", ch_num); +} + /* * Initialize the DMA descriptor information for transfer between * system memory <-> ACP SRAM @@ -236,6 +255,7 @@ static void set_acp_sysmem_dma_descriptors(void __iomem *acp_mmio, config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, &dmadscr[i]); } + pre_config_reset(acp_mmio, ch); config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, NUM_DSCRS_PER_CHANNEL, @@ -275,6 +295,7 @@ static void set_acp_to_i2s_dma_descriptors(void __iomem *acp_mmio, u32 size, config_dma_descriptor_in_sram(acp_mmio, dma_dscr_idx, &dmadscr[i]); } + pre_config_reset(acp_mmio, ch); /* Configure the DMA channel with the above descriptore */ config_acp_dma_channel(acp_mmio, ch, dma_dscr_idx - 1, NUM_DSCRS_PER_CHANNEL,