From patchwork Mon Feb 3 10:08:37 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Christophe Lyon X-Patchwork-Id: 183042 Delivered-To: patch@linaro.org Received: by 2002:a92:1f12:0:0:0:0:0 with SMTP id i18csp3795200ile; Mon, 3 Feb 2020 02:09:32 -0800 (PST) X-Google-Smtp-Source: APXvYqyFX/gWVm4+K5eTSpmGujRIlx3cN3zGA51PHqWN0bGKolUBeuK2QugIqtzN6pfq1dpl+4x0 X-Received: by 2002:a05:6830:114c:: with SMTP id x12mr17251838otq.324.1580724571875; Mon, 03 Feb 2020 02:09:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1580724571; cv=none; d=google.com; s=arc-20160816; b=fj2IgXjuNLygVMbOTS1GHztQ+kMFdiZV2A3oYS+MC23sHGPcRiYW+kDzpgck6OYcU2 /zq6ILbhgUG7qptlkQJ8cVV7M69HFVQGCa/wW6xVihgyWHal930idJgEdbo4yllhlF1E wKBYqFhlPj+gDskagHYkdX8/zrNt0xNShbliilutG5JTwDtQIDfWhYUYqpba3n0eYOB/ tHrX4RECRLQe2t/unRlBwpmHZL9cJguQhji2F3GCOnyxyQCTQcqd3LrTY8EGB6fKcrB0 rsbGTbV82XwafMbc6anRfzooDcwGQ5gfhVC5fTP9q/ZVfDlgWMnBtJnPZh7J8hquynMS tZcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=to:subject:message-id:date:from:mime-version:dkim-signature :delivered-to:sender:list-help:list-post:list-archive:list-subscribe :list-unsubscribe:list-id:precedence:mailing-list:dkim-signature :domainkey-signature; bh=s/Mqg0dvZe3Ez9oCu8yI2ECs9V+pem1JzrdE13jrba0=; b=wGclpKCIjdjxprGSFcB4kmsAZRJUF2DYbFKILmBQlA/VH9KjuCw92Ow/7AMGMrAiKs R5qggsqe/9sc89LP4nzV2d5Fcd+Pc+j/iIpV7115rTgSfMsClms8b/Db6nPUfsu+xyiv wC8BRRYTtOpZQ+QdZ8kdZdiYiLaJZyeRcVSgYyHO/Tn4t3s7OLHneIpwpxSXoKy0wJta AC2SKgrY/GvtM54bJlKDP76sjSTeWI9MGhYBK8ASfybemNKNy+XWsJosMzWr7PBLiBj2 9F/BvM5HMmRyX/d5afNKN6Bh9cdy8ylHRBzR9Ii4ku5KF00IhuT/mG7q3f4QDZk2nE2E GrgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=O1vVZs17; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ep6+gQWo; spf=pass (google.com: domain of binutils-return-108658-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="binutils-return-108658-patch=linaro.org@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id h18si8172000otr.265.2020.02.03.02.09.31 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 03 Feb 2020 02:09:31 -0800 (PST) Received-SPF: pass (google.com: domain of binutils-return-108658-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@sourceware.org header.s=default header.b=O1vVZs17; dkim=neutral (body hash did not verify) header.i=@linaro.org header.s=google header.b=Ep6+gQWo; spf=pass (google.com: domain of binutils-return-108658-patch=linaro.org@sourceware.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="binutils-return-108658-patch=linaro.org@sourceware.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :content-type; q=dns; s=default; b=Q1Exoe/gtBsmm9Ij1ZehCpAvSuunh +CHNlFTrMzpEzZyS4X+UHbgtDu6pXlFTFQGrj8efrwJnwue5YpwU53iZ0re4H4hk GmkqEQjB92HoQSTMe/Iiyz9a5V5kNWQtk0KCj63s8iPvwTzdfbaT1xjtcEsTLeKa Fbbz69kgZqh21o= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:mime-version:from:date:message-id:subject:to :content-type; s=default; bh=cEj2qhrmhKXFWNGMUcntZkSuq2Y=; b=O1v VZs17oacLW1lTMdHBQ3PxJPt/yUD6O6lw+dfucauoBeb5d8xih+IFqcJgHx1MHrY BjUArhE6z07vWGHEx9MJ72XKQiafP4TuoZNoADJU4HX0iA4PbsMquBp+U/RDMQhU 2Re8TKVOy8d8uzQMFzljr3xUM1ReWNBkqUNR/2+c= Received: (qmail 16301 invoked by alias); 3 Feb 2020 10:08:59 -0000 Mailing-List: contact binutils-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: binutils-owner@sourceware.org Delivered-To: mailing list binutils@sourceware.org Received: (qmail 16191 invoked by uid 89); 3 Feb 2020 10:08:58 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-16.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=06000000, 05000000, HX-Envelope-From:sk:christo, sk:christo X-HELO: mail-vk1-f194.google.com Received: from mail-vk1-f194.google.com (HELO mail-vk1-f194.google.com) (209.85.221.194) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 03 Feb 2020 10:08:51 +0000 Received: by mail-vk1-f194.google.com with SMTP id o200so3947738vke.4 for ; Mon, 03 Feb 2020 02:08:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=mime-version:from:date:message-id:subject:to; bh=tvezHK163iVN0DrpeD1rAnIlrPLn3rF1PYAKv39ajXk=; b=Ep6+gQWoYiwjf3fJYQAinfzL/lihTQ5kYIVEUm9NP3agPemNATEI2yffvWHZJeHAAd 2umkyzlkU37kT+KzSm4OBcmgRF7OmcOB+WCaGfDSjQkCgLlffuCnIzQqhKktJw2DiHNN 02v73c9aWOXfm2B8GJjUMWtWmC+jsAawPYsj00nAI9WjLSb1BFIOFR3PsT0/zox1hqw9 nRHlM9NNbZvVTja00OWzHKnQxj+hiY8KFgDmFmdkEvqqL7k33xXAMiJ7y1Stm9ULqALx U3HCVfLciktBH9H7jxlH0Hz+vdQr3QXDQhS1FEmjAwe4OkjwrkxtoqGeZhIZ7P59VwKo Ivtw== MIME-Version: 1.0 From: Christophe Lyon Date: Mon, 3 Feb 2020 11:08:37 +0100 Message-ID: Subject: [PATCH RFC v3] Add support for non-contiguous memory regions To: binutils X-IsSubscribed: yes Hi, This is a follow-up to https://sourceware.org/ml/binutils/2019-11/msg00402.html and https://sourceware.org/ml/binutils/2020-01/msg00064.html The changes between v2 and v3: * added some doc/NEWS * fixed bugs detected when running the testsuite with the option activated by default. In particular, I've noticed and documented the incompatibility with INSERT (or rather, it's likely to cause problems, but depends on the actual linker scripts contents), because my new option breaks the assumption of the parsing & processing order assumed by INSERT. * added new option --enable-non-contiguous-regions-warnings which activates some warnings to help understand why the behaviour changes in some cases We'd still have to do modify target that has XXX_build_one_stub(), in a way similar to what I did in elf32-arm.c. What is the recommended way of early-exiting the linker when a problem is detected? I'm using abort(), but that's not very nice and implies that there's a bug in the linker code. I'm more willing to report unsupported cases in a friendly way. There are 4 patches, to hopefully make review/comments easier; I can squash them at commit time if this is preferable. * patch1: is the main (code) patch * patch2: generic test * patch3: arm tests * patch4: powerpc test Thoughts? Thanks, Christophe >From ad381e5cb59f17da928af23d420ce33d466348f1 Mon Sep 17 00:00:00 2001 From: Christophe Lyon Date: Mon, 6 Jan 2020 14:58:24 +0000 Subject: [PATCH 3/4] Add arm tests for non-contiguous memory regions 2020-01-06 Christophe Lyon ld/ * testsuite/ld-arm/arm-elf.exp: Run the new tests. * testsuite/ld-arm/arm-elf/non-contiguous-arm.s: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm2.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm3.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm4.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm4.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm5.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm5.ld: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm6.d: New. * testsuite/ld-arm/arm-elf/non-contiguous-arm6.ld: New. Change-Id: Ib9e82b1eedd84aee936e01f9aeee7fdd4aa331bb --- ld/testsuite/ld-arm/arm-elf.exp | 7 +++ ld/testsuite/ld-arm/non-contiguous-arm.d | 4 ++ ld/testsuite/ld-arm/non-contiguous-arm.ld | 34 +++++++++++++ ld/testsuite/ld-arm/non-contiguous-arm.s | 35 +++++++++++++ ld/testsuite/ld-arm/non-contiguous-arm2.d | 77 ++++++++++++++++++++++++++++ ld/testsuite/ld-arm/non-contiguous-arm2.ld | 33 ++++++++++++ ld/testsuite/ld-arm/non-contiguous-arm3.d | 82 ++++++++++++++++++++++++++++++ ld/testsuite/ld-arm/non-contiguous-arm3.ld | 33 ++++++++++++ ld/testsuite/ld-arm/non-contiguous-arm4.d | 4 ++ ld/testsuite/ld-arm/non-contiguous-arm4.ld | 34 +++++++++++++ ld/testsuite/ld-arm/non-contiguous-arm5.d | 77 ++++++++++++++++++++++++++++ ld/testsuite/ld-arm/non-contiguous-arm5.ld | 34 +++++++++++++ ld/testsuite/ld-arm/non-contiguous-arm6.d | 76 +++++++++++++++++++++++++++ ld/testsuite/ld-arm/non-contiguous-arm6.ld | 33 ++++++++++++ 14 files changed, 563 insertions(+) create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm.ld create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm.s create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm2.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm2.ld create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm3.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm3.ld create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm4.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm4.ld create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm5.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm5.ld create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm6.d create mode 100644 ld/testsuite/ld-arm/non-contiguous-arm6.ld diff --git a/ld/testsuite/ld-arm/arm-elf.exp b/ld/testsuite/ld-arm/arm-elf.exp index 44e599f..18177d1 100644 --- a/ld/testsuite/ld-arm/arm-elf.exp +++ b/ld/testsuite/ld-arm/arm-elf.exp @@ -1261,3 +1261,10 @@ set arm_unwind_tests { "unwind-mix"} } run_ld_link_tests $arm_unwind_tests + +run_dump_test "non-contiguous-arm" +run_dump_test "non-contiguous-arm2" +run_dump_test "non-contiguous-arm3" +run_dump_test "non-contiguous-arm4" +run_dump_test "non-contiguous-arm5" +run_dump_test "non-contiguous-arm6" diff --git a/ld/testsuite/ld-arm/non-contiguous-arm.d b/ld/testsuite/ld-arm/non-contiguous-arm.d new file mode 100644 index 0000000..c62a453 --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm.d @@ -0,0 +1,4 @@ +#name: non-contiguous-arm +#source: non-contiguous-arm.s +#ld: --enable-non-contiguous-regions -T non-contiguous-arm.ld +# error: \A.*Could not assign .code.4 to an output section. Retry without --enable-non-contiguous-regions.*\Z diff --git a/ld/testsuite/ld-arm/non-contiguous-arm.ld b/ld/testsuite/ld-arm/non-contiguous-arm.ld new file mode 100644 index 0000000..a50621b --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm.ld @@ -0,0 +1,34 @@ +/* + sections .code.1 and .code.2 fit in .raml + section .code.3 fits in .ramu + section .code.4 too large to fit + expect an error about .code.4 +*/ +MEMORY +{ + RAML (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x0001c + RAMU (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040 + RAMZ (rwx) : ORIGIN = 0x20040000, LENGTH = 0x00040 +} + +SECTIONS +{ + .raml : + { _raml_start = . ; + *(.boot) ; + *(.code) *(.code.*) ; + _raml_end = . ; + } > RAML + + .ramu : AT ( ADDR (.raml) + SIZEOF (.raml) ) + { _ramu_start = . ; + *(.code) *(.code.*) ; + _ramu_end = . ; + } > RAMU + + .ramz : AT ( ADDR (.ramu) + SIZEOF (.ramu) ) + { _ramz_start = . ; + *(.code) *(.code.*) ; + _ramz_end = . ; + } > RAMZ +} diff --git a/ld/testsuite/ld-arm/non-contiguous-arm.s b/ld/testsuite/ld-arm/non-contiguous-arm.s new file mode 100644 index 0000000..cdc8b00 --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm.s @@ -0,0 +1,35 @@ + .syntax unified + .section .code.1, "ax", %progbits + .arm + # Fit in RAML + .global code1 + .type code1, %function +code1: + nop + nop + bl code2 + + .section .code.2, "ax", %progbits + # Fit in RAML + .global code2 + .type code2, %function +code2: + nop + nop + bl code3 + + .section .code.3, "ax", %progbits + # Fit in RAMU + .global code3 + .type code3, %function +code3: + nop + bl code4 + + .section .code.4, "ax", %progbits + # Fit in RAMZ + .global code4 + .type code4, %function +code4: +$a: + .fill 20, 4, 0xe1a00000 diff --git a/ld/testsuite/ld-arm/non-contiguous-arm2.d b/ld/testsuite/ld-arm/non-contiguous-arm2.d new file mode 100644 index 0000000..ed2ba69 --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm2.d @@ -0,0 +1,77 @@ +#name: non-contiguous-arm2 +#source: non-contiguous-arm.s +#ld: --enable-non-contiguous-regions -T non-contiguous-arm2.ld +#objdump: -rdth +#xfail: [is_generic] + +.*: file format elf32-(little|big)arm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.raml 00000018 1fff0000 1fff0000 00010000 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.ramu 00000008 20000000 1fff0018 00020000 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 \.ramz 00000050 20040000 20000008 00030000 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .ARM.attributes 00000012 00000000 00000000 00030050 2\*\*0 + CONTENTS, READONLY +SYMBOL TABLE: +1fff0000 l d .raml 00000000 .raml +20000000 l d .ramu 00000000 .ramu +20040000 l d .ramz 00000000 .ramz +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l df \*ABS\* 00000000 .*/non-contiguous-arm.o +1fff0018 g .raml 00000000 _raml_end +20000000 g .ramu 00000000 _ramu_start +1fff000c g F .raml 00000000 code2 +20040000 g .ramz 00000000 _ramz_start +1fff0000 g .raml 00000000 _raml_start +20000000 g F .ramu 00000000 code3 +1fff0000 g F .raml 00000000 code1 +20040050 g .ramz 00000000 _ramz_end +20040000 g F .ramz 00000000 code4 +20000008 g .ramu 00000000 _ramu_end + + +Disassembly of section .raml: + +1fff0000 \: +1fff0000: e1a00000 nop ; \(mov r0, r0\) +1fff0004: e1a00000 nop ; \(mov r0, r0\) +1fff0008: ebffffff bl 1fff000c \ + +1fff000c \: +1fff000c: e1a00000 nop ; \(mov r0, r0\) +1fff0010: e1a00000 nop ; \(mov r0, r0\) +1fff0014: eb003ff9 bl 20000000 \ + +Disassembly of section .ramu: + +20000000 \: +20000000: e1a00000 nop ; \(mov r0, r0\) +20000004: eb00fffd bl 20040000 \ + +Disassembly of section .ramz: + +20040000 \: +20040000: e1a00000 .word 0xe1a00000 +20040004: e1a00000 .word 0xe1a00000 +20040008: e1a00000 .word 0xe1a00000 +2004000c: e1a00000 .word 0xe1a00000 +20040010: e1a00000 .word 0xe1a00000 +20040014: e1a00000 .word 0xe1a00000 +20040018: e1a00000 .word 0xe1a00000 +2004001c: e1a00000 .word 0xe1a00000 +20040020: e1a00000 .word 0xe1a00000 +20040024: e1a00000 .word 0xe1a00000 +20040028: e1a00000 .word 0xe1a00000 +2004002c: e1a00000 .word 0xe1a00000 +20040030: e1a00000 .word 0xe1a00000 +20040034: e1a00000 .word 0xe1a00000 +20040038: e1a00000 .word 0xe1a00000 +2004003c: e1a00000 .word 0xe1a00000 +20040040: e1a00000 .word 0xe1a00000 +20040044: e1a00000 .word 0xe1a00000 +20040048: e1a00000 .word 0xe1a00000 +2004004c: e1a00000 .word 0xe1a00000 diff --git a/ld/testsuite/ld-arm/non-contiguous-arm2.ld b/ld/testsuite/ld-arm/non-contiguous-arm2.ld new file mode 100644 index 0000000..f13567e --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm2.ld @@ -0,0 +1,33 @@ +/* + sections .code.1 and .code.2 fit in .raml + section .code.3 fits in .ramu and does not need a farcall stub to jump to code4 + section .code.4 fits in .ramz +*/ +MEMORY +{ + RAML (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x0001c + RAMU (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008 + RAMZ (rwx) : ORIGIN = 0x20040000, LENGTH = 0x00400 +} + +SECTIONS +{ + .raml : + { _raml_start = . ; + *(.boot) ; + *(.code) *(.code.*) ; + _raml_end = . ; + } > RAML + + .ramu : AT ( ADDR (.raml) + SIZEOF (.raml) ) + { _ramu_start = . ; + *(.code) *(.code.*) ; + _ramu_end = . ; + } > RAMU + + .ramz : AT ( ADDR (.ramu) + SIZEOF (.ramu) ) + { _ramz_start = . ; + *(.code) *(.code.*) ; + _ramz_end = . ; + } > RAMZ +} diff --git a/ld/testsuite/ld-arm/non-contiguous-arm3.d b/ld/testsuite/ld-arm/non-contiguous-arm3.d new file mode 100644 index 0000000..f8bbf98 --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm3.d @@ -0,0 +1,82 @@ +#name: non-contiguous-arm3 +#source: non-contiguous-arm.s +#ld: --enable-non-contiguous-regions -T non-contiguous-arm3.ld +#objdump: -rdth +#xfail: [is_generic] + +.*: file format elf32-(little|big)arm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.raml 00000018 1fff0000 1fff0000 00010000 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.ramu 00000010 20000000 1fff0018 00020000 2\*\*3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 \.ramz 00000050 30040000 20000010 00030000 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .ARM.attributes 00000012 00000000 00000000 00030050 2\*\*0 + CONTENTS, READONLY +SYMBOL TABLE: +1fff0000 l d .raml 00000000 .raml +20000000 l d .ramu 00000000 .ramu +30040000 l d .ramz 00000000 .ramz +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l df \*ABS\* 00000000 .*/non-contiguous-arm.o +20000008 l F .ramu 00000008 __code4_veneer +1fff0018 g .raml 00000000 _raml_end +20000000 g .ramu 00000000 _ramu_start +1fff000c g F .raml 00000000 code2 +30040000 g .ramz 00000000 _ramz_start +1fff0000 g .raml 00000000 _raml_start +20000000 g F .ramu 00000000 code3 +1fff0000 g F .raml 00000000 code1 +30040050 g .ramz 00000000 _ramz_end +30040000 g F .ramz 00000000 code4 +20000010 g .ramu 00000000 _ramu_end + + +Disassembly of section .raml: + +1fff0000 \: +1fff0000: e1a00000 nop ; \(mov r0, r0\) +1fff0004: e1a00000 nop ; \(mov r0, r0\) +1fff0008: ebffffff bl 1fff000c \ + +1fff000c \: +1fff000c: e1a00000 nop ; \(mov r0, r0\) +1fff0010: e1a00000 nop ; \(mov r0, r0\) +1fff0014: eb003ff9 bl 20000000 \ + +Disassembly of section .ramu: + +20000000 \: +20000000: e1a00000 nop ; \(mov r0, r0\) +20000004: ebffffff bl 20000008 \<__code4_veneer\> + +20000008 \<__code4_veneer\>: +20000008: e51ff004 ldr pc, \[pc, #-4\] ; 2000000c \<__code4_veneer\+0x4\> +2000000c: 30040000 .word 0x30040000 + +Disassembly of section .ramz: + +30040000 \: +30040000: e1a00000 .word 0xe1a00000 +30040004: e1a00000 .word 0xe1a00000 +30040008: e1a00000 .word 0xe1a00000 +3004000c: e1a00000 .word 0xe1a00000 +30040010: e1a00000 .word 0xe1a00000 +30040014: e1a00000 .word 0xe1a00000 +30040018: e1a00000 .word 0xe1a00000 +3004001c: e1a00000 .word 0xe1a00000 +30040020: e1a00000 .word 0xe1a00000 +30040024: e1a00000 .word 0xe1a00000 +30040028: e1a00000 .word 0xe1a00000 +3004002c: e1a00000 .word 0xe1a00000 +30040030: e1a00000 .word 0xe1a00000 +30040034: e1a00000 .word 0xe1a00000 +30040038: e1a00000 .word 0xe1a00000 +3004003c: e1a00000 .word 0xe1a00000 +30040040: e1a00000 .word 0xe1a00000 +30040044: e1a00000 .word 0xe1a00000 +30040048: e1a00000 .word 0xe1a00000 +3004004c: e1a00000 .word 0xe1a00000 diff --git a/ld/testsuite/ld-arm/non-contiguous-arm3.ld b/ld/testsuite/ld-arm/non-contiguous-arm3.ld new file mode 100644 index 0000000..81bb695 --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm3.ld @@ -0,0 +1,33 @@ +/* + sections .code.1 and .code.2 fit in .raml + section .code.3 fits in .ramu even with a farcall stub to jump to code4 + section .code.4 fits in .ramz +*/ +MEMORY +{ + RAML (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x0001c + RAMU (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010 + RAMZ (rwx) : ORIGIN = 0x30040000, LENGTH = 0x00400 +} + +SECTIONS +{ + .raml : + { _raml_start = . ; + *(.boot) ; + *(.code) *(.code.*) ; + _raml_end = . ; + } > RAML + + .ramu : AT ( ADDR (.raml) + SIZEOF (.raml) ) + { _ramu_start = . ; + *(.code) *(.code.*) ; + _ramu_end = . ; + } > RAMU + + .ramz : AT ( ADDR (.ramu) + SIZEOF (.ramu) ) + { _ramz_start = . ; + *(.code) *(.code.*) ; + _ramz_end = . ; + } > RAMZ +} diff --git a/ld/testsuite/ld-arm/non-contiguous-arm4.d b/ld/testsuite/ld-arm/non-contiguous-arm4.d new file mode 100644 index 0000000..6b99544 --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm4.d @@ -0,0 +1,4 @@ +#name: non-contiguous-arm4 +#source: non-contiguous-arm.s +#ld: --enable-non-contiguous-regions -T non-contiguous-arm4.ld +# error: \AOutput section .ramu not large enough for the linker-created stubs section .code.3.__stub.*\Z diff --git a/ld/testsuite/ld-arm/non-contiguous-arm4.ld b/ld/testsuite/ld-arm/non-contiguous-arm4.ld new file mode 100644 index 0000000..1e0c376 --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm4.ld @@ -0,0 +1,34 @@ +/* + sections .code.1 and .code.2 fit in .raml + section .code.3 fits in .ramu but not its farcall stub to jump to code4 + section .code.4 fits in .ramz + expect an error about .code.3 +*/ +MEMORY +{ + RAML (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x0001c + RAMU (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008 + RAMZ (rwx) : ORIGIN = 0x30040000, LENGTH = 0x00400 +} + +SECTIONS +{ + .raml : + { _raml_start = . ; + *(.boot) ; + *(.code) *(.code.*) ; + _raml_end = . ; + } > RAML + + .ramu : AT ( ADDR (.raml) + SIZEOF (.raml) ) + { _ramu_start = . ; + *(.code) *(.code.*) ; + _ramu_end = . ; + } > RAMU + + .ramz : AT ( ADDR (.ramu) + SIZEOF (.ramu) ) + { _ramz_start = . ; + *(.code) *(.code.*) ; + _ramz_end = . ; + } > RAMZ +} diff --git a/ld/testsuite/ld-arm/non-contiguous-arm5.d b/ld/testsuite/ld-arm/non-contiguous-arm5.d new file mode 100644 index 0000000..30f6118 --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm5.d @@ -0,0 +1,77 @@ +#name: non-contiguous-arm5 +#source: non-contiguous-arm.s +#ld: --enable-non-contiguous-regions -T non-contiguous-arm5.ld +#objdump: -rdth +#xfail: [is_generic] + +.*: file format elf32-(little|big)arm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.raml 0000000c 1fff0000 1fff0000 00010000 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.ramu 00000014 20000000 1fff000c 00020000 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 \.ramz 00000050 20040000 20000014 00030000 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 3 .ARM.attributes 00000012 00000000 00000000 00030050 2\*\*0 + CONTENTS, READONLY +SYMBOL TABLE: +1fff0000 l d .raml 00000000 .raml +20000000 l d .ramu 00000000 .ramu +20040000 l d .ramz 00000000 .ramz +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l df \*ABS\* 00000000 .*/non-contiguous-arm.o +1fff000c g .raml 00000000 _raml_end +20000000 g .ramu 00000000 _ramu_start +20000000 g F .ramu 00000000 code2 +20040000 g .ramz 00000000 _ramz_start +1fff0000 g .raml 00000000 _raml_start +2000000c g F .ramu 00000000 code3 +1fff0000 g F .raml 00000000 code1 +20040050 g .ramz 00000000 _ramz_end +20040000 g F .ramz 00000000 code4 +20000014 g .ramu 00000000 _ramu_end + + +Disassembly of section .raml: + +1fff0000 \: +1fff0000: e1a00000 nop ; \(mov r0, r0\) +1fff0004: e1a00000 nop ; \(mov r0, r0\) +1fff0008: eb003ffc bl 20000000 \ + +Disassembly of section .ramu: + +20000000 \: +20000000: e1a00000 nop ; \(mov r0, r0\) +20000004: e1a00000 nop ; \(mov r0, r0\) +20000008: ebffffff bl 2000000c \ + +2000000c \: +2000000c: e1a00000 nop ; \(mov r0, r0\) +20000010: eb00fffa bl 20040000 \ + +Disassembly of section .ramz: + +20040000 \: +20040000: e1a00000 .word 0xe1a00000 +20040004: e1a00000 .word 0xe1a00000 +20040008: e1a00000 .word 0xe1a00000 +2004000c: e1a00000 .word 0xe1a00000 +20040010: e1a00000 .word 0xe1a00000 +20040014: e1a00000 .word 0xe1a00000 +20040018: e1a00000 .word 0xe1a00000 +2004001c: e1a00000 .word 0xe1a00000 +20040020: e1a00000 .word 0xe1a00000 +20040024: e1a00000 .word 0xe1a00000 +20040028: e1a00000 .word 0xe1a00000 +2004002c: e1a00000 .word 0xe1a00000 +20040030: e1a00000 .word 0xe1a00000 +20040034: e1a00000 .word 0xe1a00000 +20040038: e1a00000 .word 0xe1a00000 +2004003c: e1a00000 .word 0xe1a00000 +20040040: e1a00000 .word 0xe1a00000 +20040044: e1a00000 .word 0xe1a00000 +20040048: e1a00000 .word 0xe1a00000 +2004004c: e1a00000 .word 0xe1a00000 diff --git a/ld/testsuite/ld-arm/non-contiguous-arm5.ld b/ld/testsuite/ld-arm/non-contiguous-arm5.ld new file mode 100644 index 0000000..99c0234 --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm5.ld @@ -0,0 +1,34 @@ +/* + section .code.1 fits in .raml + section .code.2 does not fit in .raml and goes to .ramu + section .code.3 would fit in .raml, but goes to .ramu: Check that .code.2 and .code.3 are not swapped + section .code.4 fits in .ramz +*/ +MEMORY +{ + RAML (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00014 + RAMU (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00020 + RAMZ (rwx) : ORIGIN = 0x20040000, LENGTH = 0x00400 +} + +SECTIONS +{ + .raml : + { _raml_start = . ; + *(.boot) ; + *(.code) *(.code.*) ; + _raml_end = . ; + } > RAML + + .ramu : AT ( ADDR (.raml) + SIZEOF (.raml) ) + { _ramu_start = . ; + *(.code) *(.code.*) ; + _ramu_end = . ; + } > RAMU + + .ramz : AT ( ADDR (.ramu) + SIZEOF (.ramu) ) + { _ramz_start = . ; + *(.code) *(.code.*) ; + _ramz_end = . ; + } > RAMZ +} diff --git a/ld/testsuite/ld-arm/non-contiguous-arm6.d b/ld/testsuite/ld-arm/non-contiguous-arm6.d new file mode 100644 index 0000000..5c1c938 --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm6.d @@ -0,0 +1,76 @@ +#name: non-contiguous-arm6 +#source: non-contiguous-arm.s +#ld: --enable-non-contiguous-regions -T non-contiguous-arm6.ld +#objdump: -rdth +#xfail: [is_generic] + +.*: file format elf32-(little|big)arm + +Sections: +Idx Name Size VMA LMA File off Algn + 0 \.raml 00000028 1fff0000 1fff0000 00010000 2\*\*3 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 1 \.ramz 00000050 40040000 30000000 00020000 2\*\*2 + CONTENTS, ALLOC, LOAD, READONLY, CODE + 2 .ARM.attributes 00000012 00000000 00000000 00020050 2\*\*0 + CONTENTS, READONLY +SYMBOL TABLE: +1fff0000 l d .raml 00000000 .raml +40040000 l d .ramz 00000000 .ramz +00000000 l d .ARM.attributes 00000000 .ARM.attributes +00000000 l df \*ABS\* 00000000 .*/non-contiguous-arm.o +1fff0020 l F .raml 00000008 __code4_veneer +1fff0028 g .raml 00000000 _raml_end +30000000 g .raml 00000000 _ramu_start +1fff000c g F .raml 00000000 code2 +40040000 g .ramz 00000000 _ramz_start +1fff0000 g .raml 00000000 _raml_start +1fff0018 g F .raml 00000000 code3 +1fff0000 g F .raml 00000000 code1 +40040050 g .ramz 00000000 _ramz_end +40040000 g F .ramz 00000000 code4 +30000000 g .raml 00000000 _ramu_end + +Disassembly of section .raml: + +1fff0000 \: +1fff0000: e1a00000 nop ; \(mov r0, r0\) +1fff0004: e1a00000 nop ; \(mov r0, r0\) +1fff0008: ebffffff bl 1fff000c \ + +1fff000c \: +1fff000c: e1a00000 nop ; \(mov r0, r0\) +1fff0010: e1a00000 nop ; \(mov r0, r0\) +1fff0014: ebffffff bl 1fff0018 \ + +1fff0018 \: +1fff0018: e1a00000 nop ; \(mov r0, r0\) +1fff001c: ebffffff bl 1fff0020 \<__code4_veneer\> + +1fff0020 \<__code4_veneer\>: +1fff0020: e51ff004 ldr pc, \[pc, #-4\] ; 1fff0024 \<__code4_veneer\+0x4\> +1fff0024: 40040000 .word 0x40040000 + +Disassembly of section .ramz: + +40040000 \: +40040000: e1a00000 .word 0xe1a00000 +40040004: e1a00000 .word 0xe1a00000 +40040008: e1a00000 .word 0xe1a00000 +4004000c: e1a00000 .word 0xe1a00000 +40040010: e1a00000 .word 0xe1a00000 +40040014: e1a00000 .word 0xe1a00000 +40040018: e1a00000 .word 0xe1a00000 +4004001c: e1a00000 .word 0xe1a00000 +40040020: e1a00000 .word 0xe1a00000 +40040024: e1a00000 .word 0xe1a00000 +40040028: e1a00000 .word 0xe1a00000 +4004002c: e1a00000 .word 0xe1a00000 +40040030: e1a00000 .word 0xe1a00000 +40040034: e1a00000 .word 0xe1a00000 +40040038: e1a00000 .word 0xe1a00000 +4004003c: e1a00000 .word 0xe1a00000 +40040040: e1a00000 .word 0xe1a00000 +40040044: e1a00000 .word 0xe1a00000 +40040048: e1a00000 .word 0xe1a00000 +4004004c: e1a00000 .word 0xe1a00000 diff --git a/ld/testsuite/ld-arm/non-contiguous-arm6.ld b/ld/testsuite/ld-arm/non-contiguous-arm6.ld new file mode 100644 index 0000000..6d6d6fe --- /dev/null +++ b/ld/testsuite/ld-arm/non-contiguous-arm6.ld @@ -0,0 +1,33 @@ +/* + sections .code.1, .code.2 and .code.3 (+ farcall stub) fit in .raml + section .code.4 fits in .ramz + nothing fits in .ramu +*/ +MEMORY +{ + RAML (rwx) : ORIGIN = 0x1FFF0000, LENGTH = 0x00030 + RAMU (rwx) : ORIGIN = 0x30000000, LENGTH = 0x00010 + RAMZ (rwx) : ORIGIN = 0x40040000, LENGTH = 0x00400 +} + +SECTIONS +{ + .raml : + { _raml_start = . ; + *(.boot) ; + *(.code) *(.code.*) ; + _raml_end = . ; + } > RAML + + .ramu : AT ( ADDR (.raml) + SIZEOF (.raml) ) + { _ramu_start = . ; + *(.code) *(.code.*) ; + _ramu_end = . ; + } > RAMU + + .ramz : AT ( ADDR (.ramu) + SIZEOF (.ramu) ) + { _ramz_start = . ; + *(.code) *(.code.*) ; + _ramz_end = . ; + } > RAMZ +} -- 2.7.4