From patchwork Mon Sep 30 14:40:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil Goyal X-Patchwork-Id: 174762 Delivered-To: patch@linaro.org Received: by 2002:a92:7e96:0:0:0:0:0 with SMTP id q22csp7239613ill; Mon, 30 Sep 2019 07:57:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqwygPK4fjkvG8ZatkSj/YC15M5WtQ51jR84vBTifVN1PaI/xjua/xEgIXPCVAVEEe2CZP+M X-Received: by 2002:a50:b6a8:: with SMTP id d37mr20173518ede.63.1569855442473; Mon, 30 Sep 2019 07:57:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1569855442; cv=none; d=google.com; s=arc-20160816; b=N4s01Yq4g56FPx9CppaviOFHINGOZJ0uBZF9XEqRPBZp7Lv1KCCaqBlDVHQJAk3kB7 4qZsa5hhGy5AGZAW0Ss09DBdsn0Uvcj0A69HkRgzQNWfqpChDh693omafqq9oDRWIC3y FsEYuS+fLtB/D8dlFt0wEM1283XzgAAXXuLLhhNLHt70unyk0vvyQDy5UmM2I4WbO2Kf f3N64l9g3rapKcyr46CeJ6Huty6UBwZ2hOX1PDZPXZg08kFb0DczONbKWTQ4XGqlSRWd zgCJB49vAz6J7ZGFId8021NTBWcLQ2xrAxS3sMnlBFcZrxXLQvo4VsZx6KDGFE1ZA9if 32EQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:cc:to:from; bh=LPWMSCF2aq+6NsEB8lFtH/77Rmrs+TCau9cdC6TMWpw=; b=MQ2E6QNACHQgrV6TX/SnYW2koIEROMz6+rZxhCFbTZXYEJudVix5BRlMPCODV9Hnqm s8lv+FJ6byK3snCK99UJXnmXb9lktENyzPXSp0P1TS3UrOOjAdMI9r7AFTB1gvdVnxf4 OH3uKfq0g6wMuCwGuOs5rZxghtm7LFGm56enicV3+RHzUCfpibOkRbUUgMVccpS1vGfW yzokJHC3MAILPDAjF9rjjE/QydH8UB+2JSSaD4rdXfRUXkzZw35N+vViUDfpvKou30Qu C1B18uw5IjRTaSxF6mGOBnZGQY0ujbbTKeq3gu73oU9oZFvDn4qFtocf68g9j4FMYFdV yXDA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id ot41si7281022ejb.215.2019.09.30.07.57.22; Mon, 30 Sep 2019 07:57:22 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=nxp.com Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id E49A71BEC0; Mon, 30 Sep 2019 16:56:38 +0200 (CEST) Received: from inva021.nxp.com (inva021.nxp.com [92.121.34.21]) by dpdk.org (Postfix) with ESMTP id E975F1BE8F for ; Mon, 30 Sep 2019 16:56:23 +0200 (CEST) Received: from inva021.nxp.com (localhost [127.0.0.1]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id C303320049E; Mon, 30 Sep 2019 16:56:23 +0200 (CEST) Received: from invc005.ap-rdc01.nxp.com (invc005.ap-rdc01.nxp.com [165.114.16.14]) by inva021.eu-rdc02.nxp.com (Postfix) with ESMTP id 6565C2000A7; Mon, 30 Sep 2019 16:56:21 +0200 (CEST) Received: from GDB1.ap.freescale.net (GDB1.ap.freescale.net [10.232.132.179]) by invc005.ap-rdc01.nxp.com (Postfix) with ESMTP id 5FB9040318; Mon, 30 Sep 2019 22:56:18 +0800 (SGT) From: Akhil Goyal To: dev@dpdk.org Cc: aconole@redhat.com, anoobj@marvell.com, Hemant Agrawal Date: Mon, 30 Sep 2019 20:10:46 +0530 Message-Id: <20190930144104.12742-7-akhil.goyal@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190930144104.12742-1-akhil.goyal@nxp.com> References: <20190930115237.5073-1-akhil.goyal@nxp.com> <20190930144104.12742-1-akhil.goyal@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [dpdk-dev] [PATCH v3 06/24] crypto/dpaa2_sec: support CAAM HW era 10 X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" From: Hemant Agrawal Adding minimal support for CAAM HW era 10 (used in LX2) Primary changes are: 1. increased shard desc length form 6 bit to 7 bits 2. support for several PDCP operations as PROTOCOL offload. Signed-off-by: Hemant Agrawal Acked-by: Akhil Goyal --- drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c | 5 ++++ drivers/crypto/dpaa2_sec/hw/desc.h | 5 ++++ drivers/crypto/dpaa2_sec/hw/desc/pdcp.h | 21 ++++++++++----- .../dpaa2_sec/hw/rta/fifo_load_store_cmd.h | 9 ++++--- drivers/crypto/dpaa2_sec/hw/rta/header_cmd.h | 21 ++++++++++++--- drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h | 3 +-- drivers/crypto/dpaa2_sec/hw/rta/key_cmd.h | 5 ++-- drivers/crypto/dpaa2_sec/hw/rta/load_cmd.h | 10 ++++--- drivers/crypto/dpaa2_sec/hw/rta/math_cmd.h | 12 +++++---- drivers/crypto/dpaa2_sec/hw/rta/move_cmd.h | 8 +++--- drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h | 10 +++---- .../crypto/dpaa2_sec/hw/rta/operation_cmd.h | 6 ++--- .../crypto/dpaa2_sec/hw/rta/protocol_cmd.h | 9 +++++-- .../dpaa2_sec/hw/rta/sec_run_time_asm.h | 27 +++++++++++++------ .../dpaa2_sec/hw/rta/seq_in_out_ptr_cmd.h | 7 +++-- drivers/crypto/dpaa2_sec/hw/rta/store_cmd.h | 6 ++--- 16 files changed, 110 insertions(+), 54 deletions(-) -- 2.17.1 diff --git a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c index 7946abf40..9108b3c43 100644 --- a/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c +++ b/drivers/crypto/dpaa2_sec/dpaa2_sec_dpseci.c @@ -3450,6 +3450,11 @@ cryptodev_dpaa2_sec_probe(struct rte_dpaa2_driver *dpaa2_drv __rte_unused, /* init user callbacks */ TAILQ_INIT(&(cryptodev->link_intr_cbs)); + if (dpaa2_svr_family == SVR_LX2160A) + rta_set_sec_era(RTA_SEC_ERA_10); + + DPAA2_SEC_INFO("2-SEC ERA is %d", rta_get_sec_era()); + /* Invoke PMD device initialization function */ retval = dpaa2_sec_dev_init(cryptodev); if (retval == 0) diff --git a/drivers/crypto/dpaa2_sec/hw/desc.h b/drivers/crypto/dpaa2_sec/hw/desc.h index e12c3db2f..667da971b 100644 --- a/drivers/crypto/dpaa2_sec/hw/desc.h +++ b/drivers/crypto/dpaa2_sec/hw/desc.h @@ -18,6 +18,8 @@ #include "hw/compat.h" #endif +extern enum rta_sec_era rta_sec_era; + /* Max size of any SEC descriptor in 32-bit words, inclusive of header */ #define MAX_CAAM_DESCSIZE 64 @@ -113,9 +115,12 @@ /* Start Index or SharedDesc Length */ #define HDR_START_IDX_SHIFT 16 #define HDR_START_IDX_MASK (0x3f << HDR_START_IDX_SHIFT) +#define HDR_START_IDX_MASK_ERA10 (0x7f << HDR_START_IDX_SHIFT) /* If shared descriptor header, 6-bit length */ #define HDR_DESCLEN_SHR_MASK 0x3f +/* If shared descriptor header, 7-bit length era10 onwards*/ +#define HDR_DESCLEN_SHR_MASK_ERA10 0x7f /* If non-shared header, 7-bit length */ #define HDR_DESCLEN_MASK 0x7f diff --git a/drivers/crypto/dpaa2_sec/hw/desc/pdcp.h b/drivers/crypto/dpaa2_sec/hw/desc/pdcp.h index 9a73105ac..4bf1d69f9 100644 --- a/drivers/crypto/dpaa2_sec/hw/desc/pdcp.h +++ b/drivers/crypto/dpaa2_sec/hw/desc/pdcp.h @@ -776,7 +776,8 @@ pdcp_insert_cplane_enc_only_op(struct program *p, KEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key, cipherdata->keylen, INLINE_KEY(cipherdata)); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { if (sn_size == PDCP_SN_SIZE_5) PROTOCOL(p, dir, OP_PCLID_LTE_PDCP_CTRL_MIXED, (uint16_t)cipherdata->algtype << 8); @@ -962,7 +963,8 @@ pdcp_insert_cplane_snow_aes_op(struct program *p, REFERENCE(jump_back_to_sd_cmd); REFERENCE(move_mac_i_to_desc_buf); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { KEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key, cipherdata->keylen, INLINE_KEY(cipherdata)); KEY(p, KEY2, authdata->key_enc_flags, authdata->key, @@ -1286,7 +1288,8 @@ pdcp_insert_cplane_aes_snow_op(struct program *p, KEY(p, KEY2, authdata->key_enc_flags, authdata->key, authdata->keylen, INLINE_KEY(authdata)); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { int pclid; if (sn_size == PDCP_SN_SIZE_5) @@ -1430,7 +1433,8 @@ pdcp_insert_cplane_snow_zuc_op(struct program *p, SET_LABEL(p, keyjump); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { int pclid; if (sn_size == PDCP_SN_SIZE_5) @@ -1548,7 +1552,8 @@ pdcp_insert_cplane_aes_zuc_op(struct program *p, KEY(p, KEY2, authdata->key_enc_flags, authdata->key, authdata->keylen, INLINE_KEY(authdata)); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { int pclid; if (sn_size == PDCP_SN_SIZE_5) @@ -1671,7 +1676,8 @@ pdcp_insert_cplane_zuc_snow_op(struct program *p, KEY(p, KEY2, authdata->key_enc_flags, authdata->key, authdata->keylen, INLINE_KEY(authdata)); - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { int pclid; if (sn_size == PDCP_SN_SIZE_5) @@ -1806,7 +1812,8 @@ pdcp_insert_cplane_zuc_aes_op(struct program *p, return -ENOTSUP; } - if (rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) { + if ((rta_sec_era >= RTA_SEC_ERA_8 && sn_size != PDCP_SN_SIZE_18) || + (rta_sec_era == RTA_SEC_ERA_10)) { int pclid; KEY(p, KEY1, cipherdata->key_enc_flags, cipherdata->key, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/fifo_load_store_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/fifo_load_store_cmd.h index 8c807aaa2..287e09cd7 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/fifo_load_store_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/fifo_load_store_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_FIFO_LOAD_STORE_CMD_H__ @@ -42,7 +41,8 @@ static const uint32_t fifo_load_table[][2] = { * supported. */ static const unsigned int fifo_load_table_sz[] = {22, 22, 23, 23, - 23, 23, 23, 23}; + 23, 23, 23, 23, + 23, 23}; static inline int rta_fifo_load(struct program *program, uint32_t src, @@ -201,7 +201,8 @@ static const uint32_t fifo_store_table[][2] = { * supported. */ static const unsigned int fifo_store_table_sz[] = {21, 21, 21, 21, - 22, 22, 22, 23}; + 22, 22, 22, 23, + 23, 23}; static inline int rta_fifo_store(struct program *program, uint32_t src, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/header_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/header_cmd.h index 0c7ea9387..45aefa04c 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/header_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/header_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_HEADER_CMD_H__ @@ -19,6 +18,8 @@ static const uint32_t job_header_flags[] = { DNR | TD | MTD | SHR | REO | RSMS | EXT, DNR | TD | MTD | SHR | REO | RSMS | EXT, DNR | TD | MTD | SHR | REO | RSMS | EXT, + DNR | TD | MTD | SHR | REO | EXT, + DNR | TD | MTD | SHR | REO | EXT, DNR | TD | MTD | SHR | REO | EXT }; @@ -31,6 +32,8 @@ static const uint32_t shr_header_flags[] = { DNR | SC | PD | CIF | RIF, DNR | SC | PD | CIF | RIF, DNR | SC | PD | CIF | RIF, + DNR | SC | PD | CIF | RIF, + DNR | SC | PD | CIF | RIF, DNR | SC | PD | CIF | RIF }; @@ -72,7 +75,12 @@ rta_shr_header(struct program *program, } opcode |= HDR_ONE; - opcode |= (start_idx << HDR_START_IDX_SHIFT) & HDR_START_IDX_MASK; + if (rta_sec_era >= RTA_SEC_ERA_10) + opcode |= (start_idx << HDR_START_IDX_SHIFT) & + HDR_START_IDX_MASK_ERA10; + else + opcode |= (start_idx << HDR_START_IDX_SHIFT) & + HDR_START_IDX_MASK; if (flags & DNR) opcode |= HDR_DNR; @@ -160,7 +168,12 @@ rta_job_header(struct program *program, } opcode |= HDR_ONE; - opcode |= ((start_idx << HDR_START_IDX_SHIFT) & HDR_START_IDX_MASK); + if (rta_sec_era >= RTA_SEC_ERA_10) + opcode |= (start_idx << HDR_START_IDX_SHIFT) & + HDR_START_IDX_MASK_ERA10; + else + opcode |= (start_idx << HDR_START_IDX_SHIFT) & + HDR_START_IDX_MASK; if (flags & EXT) { opcode |= HDR_EXT; diff --git a/drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h index 546d22e98..18f781e37 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/jump_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_JUMP_CMD_H__ diff --git a/drivers/crypto/dpaa2_sec/hw/rta/key_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/key_cmd.h index 1ec21234a..ec3fbcaf6 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/key_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/key_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_KEY_CMD_H__ @@ -19,6 +18,8 @@ static const uint32_t key_enc_flags[] = { ENC | NWB | EKT | TK, ENC | NWB | EKT | TK, ENC | NWB | EKT | TK | PTS, + ENC | NWB | EKT | TK | PTS, + ENC | NWB | EKT | TK | PTS, ENC | NWB | EKT | TK | PTS }; diff --git a/drivers/crypto/dpaa2_sec/hw/rta/load_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/load_cmd.h index f3b0dcfcb..38e253c22 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/load_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/load_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_LOAD_CMD_H__ @@ -19,6 +18,8 @@ static const uint32_t load_len_mask_allowed[] = { 0x000000fe, 0x000000fe, 0x000000fe, + 0x000000fe, + 0x000000fe, 0x000000fe }; @@ -30,6 +31,8 @@ static const uint32_t load_off_mask_allowed[] = { 0x000000ff, 0x000000ff, 0x000000ff, + 0x000000ff, + 0x000000ff, 0x000000ff }; @@ -137,7 +140,8 @@ static const struct load_map load_dst[] = { * Allowed LOAD destinations for each SEC Era. * Values represent the number of entries from load_dst[] that are supported. */ -static const unsigned int load_dst_sz[] = { 31, 34, 34, 40, 40, 40, 40, 40 }; +static const unsigned int load_dst_sz[] = { 31, 34, 34, 40, 40, + 40, 40, 40, 40, 40}; static inline int load_check_len_offset(int pos, uint32_t length, uint32_t offset) diff --git a/drivers/crypto/dpaa2_sec/hw/rta/math_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/math_cmd.h index 5b28cbabb..cca70f7e0 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/math_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/math_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_MATH_CMD_H__ @@ -29,7 +28,8 @@ static const uint32_t math_op1[][2] = { * Allowed MATH op1 sources for each SEC Era. * Values represent the number of entries from math_op1[] that are supported. */ -static const unsigned int math_op1_sz[] = {10, 10, 12, 12, 12, 12, 12, 12}; +static const unsigned int math_op1_sz[] = {10, 10, 12, 12, 12, 12, + 12, 12, 12, 12}; static const uint32_t math_op2[][2] = { /*1*/ { MATH0, MATH_SRC1_REG0 }, @@ -51,7 +51,8 @@ static const uint32_t math_op2[][2] = { * Allowed MATH op2 sources for each SEC Era. * Values represent the number of entries from math_op2[] that are supported. */ -static const unsigned int math_op2_sz[] = {8, 9, 13, 13, 13, 13, 13, 13}; +static const unsigned int math_op2_sz[] = {8, 9, 13, 13, 13, 13, 13, 13, + 13, 13}; static const uint32_t math_result[][2] = { /*1*/ { MATH0, MATH_DEST_REG0 }, @@ -71,7 +72,8 @@ static const uint32_t math_result[][2] = { * Values represent the number of entries from math_result[] that are * supported. */ -static const unsigned int math_result_sz[] = {9, 9, 10, 10, 10, 10, 10, 10}; +static const unsigned int math_result_sz[] = {9, 9, 10, 10, 10, 10, 10, 10, + 10, 10}; static inline int rta_math(struct program *program, uint64_t operand1, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/move_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/move_cmd.h index a7ff7c675..d2151c6dd 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/move_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/move_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_MOVE_CMD_H__ @@ -47,7 +46,8 @@ static const uint32_t move_src_table[][2] = { * Values represent the number of entries from move_src_table[] that are * supported. */ -static const unsigned int move_src_table_sz[] = {9, 11, 14, 14, 14, 14, 14, 14}; +static const unsigned int move_src_table_sz[] = {9, 11, 14, 14, 14, 14, 14, 14, + 14, 14}; static const uint32_t move_dst_table[][2] = { /*1*/ { CONTEXT1, MOVE_DEST_CLASS1CTX }, @@ -72,7 +72,7 @@ static const uint32_t move_dst_table[][2] = { * supported. */ static const -unsigned int move_dst_table_sz[] = {13, 14, 14, 15, 15, 15, 15, 15}; +unsigned int move_dst_table_sz[] = {13, 14, 14, 15, 15, 15, 15, 15, 15, 15}; static inline int set_move_offset(struct program *program __maybe_unused, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h index 94f775e2e..85092d961 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/nfifo_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_NFIFO_CMD_H__ @@ -24,7 +23,7 @@ static const uint32_t nfifo_src[][2] = { * Allowed NFIFO LOAD sources for each SEC Era. * Values represent the number of entries from nfifo_src[] that are supported. */ -static const unsigned int nfifo_src_sz[] = {4, 5, 5, 5, 5, 5, 5, 7}; +static const unsigned int nfifo_src_sz[] = {4, 5, 5, 5, 5, 5, 5, 7, 7, 7}; static const uint32_t nfifo_data[][2] = { { MSG, NFIFOENTRY_DTYPE_MSG }, @@ -77,7 +76,8 @@ static const uint32_t nfifo_flags[][2] = { * Allowed NFIFO LOAD flags for each SEC Era. * Values represent the number of entries from nfifo_flags[] that are supported. */ -static const unsigned int nfifo_flags_sz[] = {12, 14, 14, 14, 14, 14, 14, 14}; +static const unsigned int nfifo_flags_sz[] = {12, 14, 14, 14, 14, 14, + 14, 14, 14, 14}; static const uint32_t nfifo_pad_flags[][2] = { { BM, NFIFOENTRY_BM }, @@ -90,7 +90,7 @@ static const uint32_t nfifo_pad_flags[][2] = { * Values represent the number of entries from nfifo_pad_flags[] that are * supported. */ -static const unsigned int nfifo_pad_flags_sz[] = {2, 2, 2, 2, 3, 3, 3, 3}; +static const unsigned int nfifo_pad_flags_sz[] = {2, 2, 2, 2, 3, 3, 3, 3, 3, 3}; static inline int rta_nfifo_load(struct program *program, uint32_t src, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/operation_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/operation_cmd.h index b85760e5b..9a1788c0f 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/operation_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/operation_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_OPERATION_CMD_H__ @@ -229,7 +228,8 @@ static const struct alg_aai_map alg_table[] = { * Allowed OPERATION algorithms for each SEC Era. * Values represent the number of entries from alg_table[] that are supported. */ -static const unsigned int alg_table_sz[] = {14, 15, 15, 15, 17, 17, 11, 17}; +static const unsigned int alg_table_sz[] = {14, 15, 15, 15, 17, 17, + 11, 17, 17, 17}; static inline int rta_operation(struct program *program, uint32_t cipher_algo, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/protocol_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/protocol_cmd.h index 82581edf5..e9f20703f 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/protocol_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/protocol_cmd.h @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016, 2019 NXP + * Copyright 2016,2019 NXP * */ @@ -326,6 +326,10 @@ static const uint32_t proto_blob_flags[] = { OP_PCL_BLOB_EKT | OP_PCL_BLOB_REG_MASK | OP_PCL_BLOB_SEC_MEM, OP_PCL_BLOB_FORMAT_MASK | OP_PCL_BLOB_BLACK | OP_PCL_BLOB_TKEK | OP_PCL_BLOB_EKT | OP_PCL_BLOB_REG_MASK | OP_PCL_BLOB_SEC_MEM, + OP_PCL_BLOB_FORMAT_MASK | OP_PCL_BLOB_BLACK | OP_PCL_BLOB_TKEK | + OP_PCL_BLOB_EKT | OP_PCL_BLOB_REG_MASK | OP_PCL_BLOB_SEC_MEM, + OP_PCL_BLOB_FORMAT_MASK | OP_PCL_BLOB_BLACK | OP_PCL_BLOB_TKEK | + OP_PCL_BLOB_EKT | OP_PCL_BLOB_REG_MASK | OP_PCL_BLOB_SEC_MEM, OP_PCL_BLOB_FORMAT_MASK | OP_PCL_BLOB_BLACK | OP_PCL_BLOB_TKEK | OP_PCL_BLOB_EKT | OP_PCL_BLOB_REG_MASK | OP_PCL_BLOB_SEC_MEM }; @@ -604,7 +608,8 @@ static const struct proto_map proto_table[] = { * Allowed OPERATION protocols for each SEC Era. * Values represent the number of entries from proto_table[] that are supported. */ -static const unsigned int proto_table_sz[] = {21, 29, 29, 29, 29, 35, 37, 40}; +static const unsigned int proto_table_sz[] = {21, 29, 29, 29, 29, 35, 37, + 40, 40, 40}; static inline int rta_proto_operation(struct program *program, uint32_t optype, diff --git a/drivers/crypto/dpaa2_sec/hw/rta/sec_run_time_asm.h b/drivers/crypto/dpaa2_sec/hw/rta/sec_run_time_asm.h index 5357187f8..d8cdebd20 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/sec_run_time_asm.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/sec_run_time_asm.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_SEC_RUN_TIME_ASM_H__ @@ -36,7 +35,9 @@ enum rta_sec_era { RTA_SEC_ERA_6, RTA_SEC_ERA_7, RTA_SEC_ERA_8, - MAX_SEC_ERA = RTA_SEC_ERA_8 + RTA_SEC_ERA_9, + RTA_SEC_ERA_10, + MAX_SEC_ERA = RTA_SEC_ERA_10 }; /** @@ -605,10 +606,14 @@ __rta_inline_data(struct program *program, uint64_t data, static inline unsigned int rta_desc_len(uint32_t *buffer) { - if ((*buffer & CMD_MASK) == CMD_DESC_HDR) + if ((*buffer & CMD_MASK) == CMD_DESC_HDR) { return *buffer & HDR_DESCLEN_MASK; - else - return *buffer & HDR_DESCLEN_SHR_MASK; + } else { + if (rta_sec_era >= RTA_SEC_ERA_10) + return *buffer & HDR_DESCLEN_SHR_MASK_ERA10; + else + return *buffer & HDR_DESCLEN_SHR_MASK; + } } static inline unsigned int @@ -701,9 +706,15 @@ rta_patch_header(struct program *program, int line, unsigned int new_ref) return -EINVAL; opcode = bswap ? swab32(program->buffer[line]) : program->buffer[line]; + if (rta_sec_era >= RTA_SEC_ERA_10) { + opcode &= (uint32_t)~HDR_START_IDX_MASK_ERA10; + opcode |= (new_ref << HDR_START_IDX_SHIFT) & + HDR_START_IDX_MASK_ERA10; + } else { + opcode &= (uint32_t)~HDR_START_IDX_MASK; + opcode |= (new_ref << HDR_START_IDX_SHIFT) & HDR_START_IDX_MASK; + } - opcode &= (uint32_t)~HDR_START_IDX_MASK; - opcode |= (new_ref << HDR_START_IDX_SHIFT) & HDR_START_IDX_MASK; program->buffer[line] = bswap ? swab32(opcode) : opcode; return 0; diff --git a/drivers/crypto/dpaa2_sec/hw/rta/seq_in_out_ptr_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/seq_in_out_ptr_cmd.h index ceb6a8719..5e6af0c83 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/seq_in_out_ptr_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/seq_in_out_ptr_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_SEQ_IN_OUT_PTR_CMD_H__ @@ -19,6 +18,8 @@ static const uint32_t seq_in_ptr_flags[] = { RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP, RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP, RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP, + RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP, + RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP, RBS | INL | SGF | PRE | EXT | RTO | RJD | SOP }; @@ -31,6 +32,8 @@ static const uint32_t seq_out_ptr_flags[] = { SGF | PRE | EXT | RTO | RST | EWS, SGF | PRE | EXT | RTO | RST | EWS, SGF | PRE | EXT | RTO | RST | EWS, + SGF | PRE | EXT | RTO | RST | EWS, + SGF | PRE | EXT | RTO | RST | EWS, SGF | PRE | EXT | RTO | RST | EWS }; diff --git a/drivers/crypto/dpaa2_sec/hw/rta/store_cmd.h b/drivers/crypto/dpaa2_sec/hw/rta/store_cmd.h index 8b58e544d..5de47d053 100644 --- a/drivers/crypto/dpaa2_sec/hw/rta/store_cmd.h +++ b/drivers/crypto/dpaa2_sec/hw/rta/store_cmd.h @@ -1,8 +1,7 @@ /* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0) * * Copyright 2008-2016 Freescale Semiconductor Inc. - * Copyright 2016 NXP - * + * Copyright 2016,2019 NXP */ #ifndef __RTA_STORE_CMD_H__ @@ -56,7 +55,8 @@ static const uint32_t store_src_table[][2] = { * supported. */ static const unsigned int store_src_table_sz[] = {29, 31, 33, 33, - 33, 33, 35, 35}; + 33, 33, 35, 35, + 35, 35}; static inline int rta_store(struct program *program, uint64_t src,