From patchwork Mon Jun 8 21:34:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Honnappa Nagarahalli X-Patchwork-Id: 187623 Delivered-To: patch@linaro.org Received: by 2002:a92:cf06:0:0:0:0:0 with SMTP id c6csp5214690ilo; Mon, 8 Jun 2020 14:34:37 -0700 (PDT) X-Google-Smtp-Source: ABdhPJwaQoR5YV6lONq+LC+DlvZkuN+3LdZjMt3pcv6KlVaWz1z+dbQqDovz5WXC1OzQZFXhCZKP X-Received: by 2002:a05:6402:1285:: with SMTP id w5mr24391515edv.73.1591652077838; Mon, 08 Jun 2020 14:34:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1591652077; cv=none; d=google.com; s=arc-20160816; b=uCYd+7G3TiALS7SIb2UDtd9LczkBNmx1jELUpB/uwpzm0Zrq43YnqaQR/p+sZZYuoZ 9Y/ygDcjnV4PftV6WQI/rJYkD/RiMHL16BNcbL7zuFdoJtL51IWKHfYOv8ZKHLCdnFVE aXVj/CJ4gLhaw6lY1VCI7fKe0ULbJBzEX7TezYoXcBL9EWNiyuk71/NXNYD2+wKc8zuT K/NDZ2oLlFQos8/wD16jyxMtr0j4qbdnn7pGFEd6x6O5iRYf8YG9i4Kqiei0q/ubgHBM rqaLAyvGbASDKtx6Zf+8RKwMfzGtlvGOQ/Hb9xl/K3BqobwSUFZFM9xqM4D00xHckK+W j5mw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:message-id:date:cc:to :from; bh=SQBfQ/NMJ7ZML3oz0Ho8zi2Em8T1kNsuv5QOPio5sBE=; b=rHjbSwnmHIeskMrgHRRyA9r2DAoAaqShcYtmoW5ziPaokkYWNiajXHcbAnwNkKgJF+ q5YqlGkiT1qu1vUbczRrxG6p/SlJHsFyVg/1eRBPcP02o6HfHvYo6NL9sGS/yQD/wWdJ mVNke4v1jPZN0gu1/vxxuZMfSbPrJPEnFM9JkZHeia7RueOAJYGRiIq+6h3g0ZtD3k+g IbADcbjiQu/JvCh6zkqq2bbbaDho3yfIRj0RNlgSF1+xsSU6y8i6ebg3wpasC+O5xt1N WUUFTa0mL4riJSUwcBLvl3nZ3wVDdKZoRHK0JS1lk5skZQKKxvwVFXeNo7eVxbJ5Lii5 65hA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org Return-Path: Received: from dpdk.org (dpdk.org. [92.243.14.124]) by mx.google.com with ESMTP id rn4si9336437ejb.124.2020.06.08.14.34.37; Mon, 08 Jun 2020 14:34:37 -0700 (PDT) Received-SPF: pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) client-ip=92.243.14.124; Authentication-Results: mx.google.com; spf=pass (google.com: domain of dev-bounces@dpdk.org designates 92.243.14.124 as permitted sender) smtp.mailfrom=dev-bounces@dpdk.org Received: from [92.243.14.124] (localhost [127.0.0.1]) by dpdk.org (Postfix) with ESMTP id 893922BA2; Mon, 8 Jun 2020 23:34:36 +0200 (CEST) Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by dpdk.org (Postfix) with ESMTP id 6AA9B2B9E; Mon, 8 Jun 2020 23:34:35 +0200 (CEST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C1A9A1FB; Mon, 8 Jun 2020 14:34:34 -0700 (PDT) Received: from qc2400f-1.austin.arm.com (qc2400f-1.austin.arm.com [10.118.12.27]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id B5C613F66F; Mon, 8 Jun 2020 14:34:34 -0700 (PDT) From: Honnappa Nagarahalli To: dev@dpdk.org, honnappa.nagarahalli@arm.com, jerinj@marvell.com, hemant.agrawal@nxp.com, akhil.goyal@nxp.com, ogerlitz@mellanox.com, ajit.khaparde@broadcom.com Cc: ruigeng.wang@arm.com, dharmik.thakkar@arm.com, phil.yang@arm.com, stable@dpdk.org Date: Mon, 8 Jun 2020 16:34:17 -0500 Message-Id: <20200608213417.9764-1-honnappa.nagarahalli@arm.com> X-Mailer: git-send-email 2.17.1 Subject: [dpdk-dev] [PATCH] eal: generic counter based loop for CPU freq calculation X-BeenThere: dev@dpdk.org X-Mailman-Version: 2.1.15 Precedence: list List-Id: DPDK patches and discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dev-bounces@dpdk.org Sender: "dev" get_tsc_freq uses 'nanosleep' system call to calculate the CPU frequency. However, 'nanosleep' results in the process getting un-scheduled. The kernel saves and restores the PMU state. This ensures that the PMU cycles are not counted towards a sleeping process. When RTE_ARM_EAL_RDTSC_USE_PMU is defined, this results in incorrect CPU frequency calculation. This logic is replaced with generic counter based loop. Bugzilla ID: 450 Fixes: af75078fece3 ("first public release") Cc: stable@dpdk.org Signed-off-by: Honnappa Nagarahalli Reviewed-by: Ruifeng Wang Reviewed-by: Dharmik Thakkar Reviewed-by: Phil Yang --- lib/librte_eal/arm/include/rte_cycles_64.h | 45 +++++++++++++++++++--- lib/librte_eal/arm/rte_cycles.c | 24 ++++++++++-- 2 files changed, 61 insertions(+), 8 deletions(-) -- 2.17.1 Acked-by: Jerin Jacob diff --git a/lib/librte_eal/arm/include/rte_cycles_64.h b/lib/librte_eal/arm/include/rte_cycles_64.h index da557b6a1..6fc352036 100644 --- a/lib/librte_eal/arm/include/rte_cycles_64.h +++ b/lib/librte_eal/arm/include/rte_cycles_64.h @@ -11,6 +11,36 @@ extern "C" { #include "generic/rte_cycles.h" +/** Read generic counter frequency */ +static inline uint64_t +__rte_rd_generic_cntr_freq(void) +{ + uint64_t freq; + + asm volatile("mrs %0, cntfrq_el0" : "=r" (freq)); + return freq; +} + +/** Read generic counter */ +static inline uint64_t +__rte_rd_generic_cntr(void) +{ + uint64_t tsc; + + asm volatile("mrs %0, cntvct_el0" : "=r" (tsc)); + return tsc; +} + +static inline uint64_t +__rte_rd_generic_cntr_precise(void) +{ + uint64_t tsc; + + asm volatile("isb" : : : "memory"); + asm volatile("mrs %0, cntvct_el0" : "=r" (tsc)); + return tsc; +} + /** * Read the time base register. * @@ -25,10 +55,7 @@ extern "C" { static inline uint64_t rte_rdtsc(void) { - uint64_t tsc; - - asm volatile("mrs %0, cntvct_el0" : "=r" (tsc)); - return tsc; + return __rte_rd_generic_cntr(); } #else /** @@ -49,14 +76,22 @@ rte_rdtsc(void) * asm volatile("msr pmcr_el0, %0" : : "r" (val)); * */ + +/** Read PMU cycle counter */ static inline uint64_t -rte_rdtsc(void) +__rte_rd_pmu_cycle_cntr(void) { uint64_t tsc; asm volatile("mrs %0, pmccntr_el0" : "=r"(tsc)); return tsc; } + +static inline uint64_t +rte_rdtsc(void) +{ + return __rte_rd_pmu_cycle_cntr(); +} #endif static inline uint64_t diff --git a/lib/librte_eal/arm/rte_cycles.c b/lib/librte_eal/arm/rte_cycles.c index 3500d523e..92c87a8a4 100644 --- a/lib/librte_eal/arm/rte_cycles.c +++ b/lib/librte_eal/arm/rte_cycles.c @@ -3,14 +3,32 @@ */ #include "eal_private.h" +#include "rte_cycles.h" uint64_t get_tsc_freq_arch(void) { #if defined RTE_ARCH_ARM64 && !defined RTE_ARM_EAL_RDTSC_USE_PMU - uint64_t freq; - asm volatile("mrs %0, cntfrq_el0" : "=r" (freq)); - return freq; + return __rte_rd_generic_cntr_freq(); +#elif defined RTE_ARCH_ARM64 && defined RTE_ARM_EAL_RDTSC_USE_PMU + /* Use the generic counter ticks to calculate the PMU + * cycle frequency. + */ + uint64_t gcnt_ticks; + uint64_t start_ticks, cur_ticks; + uint64_t start_pmu_cycles, end_pmu_cycles; + + /* Number of ticks for 1/10 second */ + gcnt_ticks = __rte_rd_generic_cntr_freq() / 10; + + start_ticks = __rte_rd_generic_cntr_precise(); + start_pmu_cycles = rte_rdtsc_precise(); + do { + cur_ticks = __rte_rd_generic_cntr(); + } while ((cur_ticks - start_ticks) < gcnt_ticks); + end_pmu_cycles = rte_rdtsc_precise(); + + return ((end_pmu_cycles - start_pmu_cycles) * 10); #else return 0; #endif