From patchwork Thu Mar 17 06:53:12 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marek Szyprowski X-Patchwork-Id: 63944 Delivered-To: patch@linaro.org Received: by 10.112.199.169 with SMTP id jl9csp290094lbc; Wed, 16 Mar 2016 23:53:27 -0700 (PDT) X-Received: by 10.66.140.70 with SMTP id re6mr12526161pab.100.1458197607726; Wed, 16 Mar 2016 23:53:27 -0700 (PDT) Return-Path: Received: from gabe.freedesktop.org (gabe.freedesktop.org. [131.252.210.177]) by mx.google.com with ESMTP id q90si10451460pfa.198.2016.03.16.23.53.27; Wed, 16 Mar 2016 23:53:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) client-ip=131.252.210.177; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 131.252.210.177 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6A6256EA56; Thu, 17 Mar 2016 06:53:23 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 89ADA6EA56 for ; Thu, 17 Mar 2016 06:53:21 +0000 (UTC) Received: from eucpsbgm2.samsung.com (unknown [203.254.199.245]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0O4600DGM8GTZF20@mailout2.w1.samsung.com> for dri-devel@lists.freedesktop.org; Thu, 17 Mar 2016 06:53:17 +0000 (GMT) X-AuditID: cbfec7f5-f79b16d000005389-45-56ea545ddbdd Received: from eusync4.samsung.com ( [203.254.199.214]) by eucpsbgm2.samsung.com (EUCPMTA) with SMTP id C2.13.21385.D545AE65; Thu, 17 Mar 2016 06:53:17 +0000 (GMT) Received: from amdc1339.digital.local ([106.116.147.30]) by eusync4.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0O46000AE8GPT830@eusync4.samsung.com>; Thu, 17 Mar 2016 06:53:17 +0000 (GMT) From: Marek Szyprowski To: dri-devel@lists.freedesktop.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH] drm/exynos: fimd: fix broken dp_clock control Date: Thu, 17 Mar 2016 07:53:12 +0100 Message-id: <1458197592-5050-1-git-send-email-m.szyprowski@samsung.com> X-Mailer: git-send-email 1.9.2 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupkluLIzCtJLcpLzFFi42I5/e/4Nd3YkFdhBhPO8FncWneO1WLjjPWs Fpf3a1tc+fqezWLS/QksFm/ermGyeHHvIovF6xeGFjPO72OyWHvkLrvFjMkv2Ry4Pe53H2fy 2NJ/l92jb8sqRo/Pm+QCWKK4bFJSczLLUov07RK4MlYv/MRY0MtZMan5NHsD4x32LkZODgkB E4nFT1YyQ9hiEhfurWfrYuTiEBJYyihxp+U3lNPEJPF12mo2kCo2AUOJrrddYLaIgJtE0+GZ rCBFzAJTmCW2r/7HApIQFrCT+L5rA9hYFgFViSvn1gDZHBy8Au4SX1eaQ2yTk/j/cgXTBEbu BYwMqxhFU0uTC4qT0nON9IoTc4tL89L1kvNzNzFCAujrDsalx6wOMQpwMCrx8DKcexkmxJpY VlyZe4hRgoNZSYS3RPhVmBBvSmJlVWpRfnxRaU5q8SFGaQ4WJXHembvehwgJpCeWpGanphak FsFkmTg4pRoY+Z8wms/Vv9bInJuT/PbgjIYbP86vsQk5kryjKby/LubmfKdNzWuuHVFcOPu3 zocGxeKLC5+rLD27TC6y7/zrnIk50qYJis1iR50bn68UWuCy+d2+22ph9fofHi5r3j7XI3ua zu0Z0yUnTqm6eTz5wr958uv0Pe7/vtX88NfmxSWzuF8riYicnqbEUpyRaKjFXFScCACEQrMU HAIAAA== Cc: Krzysztof Kozlowski , Javier Martinez Canillas , Bartlomiej Zolnierkiewicz , Seung-Woo Kim , Andrzej Hajda , Chanho Park , Marek Szyprowski X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Commit 1feafd3afd294b03dbbedb8e8f94e0c4db526f10 ("drm/exynos: add exynos5420 support for fimd") add support for Exynos 5420 SoC, but it broke enabling display clock feature because of incorrect condition check. This patch fixes it, so display is working again on platforms requiring display clock control (i.e. Exynos5250-based SNOW platform). Signed-off-by: Marek Szyprowski --- drivers/gpu/drm/exynos/exynos_drm_fimd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/exynos/exynos_drm_fimd.c b/drivers/gpu/drm/exynos/exynos_drm_fimd.c index 0a44511..c65fe79 100644 --- a/drivers/gpu/drm/exynos/exynos_drm_fimd.c +++ b/drivers/gpu/drm/exynos/exynos_drm_fimd.c @@ -889,7 +889,7 @@ static void fimd_dp_clock_enable(struct exynos_drm_crtc *crtc, bool enable) * clock. On these SoCs the bootloader may enable it but any * power domain off/on will reset it to disable state. */ - if (ctx->driver_data != &exynos5_fimd_driver_data || + if (ctx->driver_data != &exynos5_fimd_driver_data && ctx->driver_data != &exynos5420_fimd_driver_data) return;