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[2610:10:20:722:a800:ff:fe36:1795]) by mx.google.com with ESMTPS id r4si15125073pgp.581.2019.03.26.03.32.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 26 Mar 2019 03:32:39 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) client-ip=2610:10:20:722:a800:ff:fe36:1795; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of dri-devel-bounces@lists.freedesktop.org designates 2610:10:20:722:a800:ff:fe36:1795 as permitted sender) smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org; dmarc=fail (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 747C86E7E0; Tue, 26 Mar 2019 10:32:38 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5E7B06E7E0 for ; Tue, 26 Mar 2019 10:32:37 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id x2QAWYCN043758; Tue, 26 Mar 2019 05:32:34 -0500 Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x2QAWYf4002670 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 26 Mar 2019 05:32:34 -0500 Received: from DFLE112.ent.ti.com (10.64.6.33) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 26 Mar 2019 05:32:33 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 26 Mar 2019 05:32:33 -0500 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x2QAWN25071249; Tue, 26 Mar 2019 05:32:31 -0500 From: Tomi Valkeinen To: Andrzej Hajda , Laurent Pinchart , , Lucas Stach , Andrey Gusakov , Philipp Zabel , Andrey Smirnov , Jyri Sarha , Peter Ujfalusi , Benoit Parrot Subject: [PATCHv2 03/22] drm/bridge: tc358767: fix ansi 8b10b use Date: Tue, 26 Mar 2019 12:31:27 +0200 Message-ID: <20190326103146.24795-4-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190326103146.24795-1-tomi.valkeinen@ti.com> References: <20190326103146.24795-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1553596354; bh=GR+iFK9fpwKw0iLA2Q86EAhBm/eN6981/+g3Kvvk7rM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Y/8qpj6PEhnxADLiT0kaSiO12jTKW92vZEWNovmWK8JdSAvxf3BbvZQpk5Zz2XVep s7FLFMgFLmzBw/ViQimHojgr6LGTuUtM4NDDhijyrCHk/BAjiNgGv956GJJ6m/ZVxz Xry9dBKeK4Jc8vMC2XIexgzWyZUSJ1ptR72MCpEE= X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomi Valkeinen Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" DP always uses ANSI 8B10B encoding. Some monitors (old?) may not have the ANSI 8B10B bit set in DPCD, even if it should always be set. The tc358767 driver currently respects that flag, and turns the encoding off if the monitor does not have the bit set, which then results in the monitor not working. This patch makes the driver to always use ANSI 8B10B encoding, and drops the 'coding8b10b' field which is no longer used. Signed-off-by: Tomi Valkeinen Reviewed-by: Andrzej Hajda Reviewed-by: Laurent Pinchart --- drivers/gpu/drm/bridge/tc358767.c | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/bridge/tc358767.c b/drivers/gpu/drm/bridge/tc358767.c index 11a50f7bb4be..163c594fa6ac 100644 --- a/drivers/gpu/drm/bridge/tc358767.c +++ b/drivers/gpu/drm/bridge/tc358767.c @@ -188,7 +188,6 @@ struct tc_edp_link { u8 assr; int scrambler_dis; int spread; - int coding8b10b; u8 swing; u8 preemp; }; @@ -390,13 +389,10 @@ static u32 tc_srcctrl(struct tc_data *tc) * No training pattern, skew lane 1 data by two LSCLK cycles with * respect to lane 0 data, AutoCorrect Mode = 0 */ - u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW; + u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B; if (tc->link.scrambler_dis) reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ - if (tc->link.coding8b10b) - /* Enable 8/10B Encoder (TxData[19:16] not used) */ - reg |= DP0_SRCCTRL_EN810B; if (tc->link.spread) reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ if (tc->link.base.num_lanes == 2) @@ -635,7 +631,7 @@ static int tc_get_display_props(struct tc_data *tc) ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, tmp); if (ret < 0) goto err_dpcd_read; - tc->link.coding8b10b = tmp[0] & BIT(0); + tc->link.scrambler_dis = 0; /* read assr */ ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, tmp); @@ -649,7 +645,6 @@ static int tc_get_display_props(struct tc_data *tc) tc->link.base.num_lanes, (tc->link.base.capabilities & DP_LINK_CAP_ENHANCED_FRAMING) ? "enhanced" : "non-enhanced"); - dev_dbg(tc->dev, "ANSI 8B/10B: %d\n", tc->link.coding8b10b); dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", tc->link.assr, tc->assr); @@ -951,7 +946,7 @@ static int tc_main_link_setup(struct tc_data *tc) /* DOWNSPREAD_CTRL */ tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; /* MAIN_LINK_CHANNEL_CODING_SET */ - tmp[1] = tc->link.coding8b10b ? DP_SET_ANSI_8B10B : 0x00; + tmp[1] = DP_SET_ANSI_8B10B; ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); if (ret < 0) goto err_dpcd_write;