| Message ID | 20220215141643.3444941-5-dmitry.baryshkov@linaro.org |
|---|---|
| State | Superseded |
| Headers | show |
| Series | drm/msm/dpu: cleanup dpu encoder code | expand |
On Tue 15 Feb 08:16 CST 2022, Dmitry Baryshkov wrote: > We do not use MSM bus client, so drop bus_scaling_client field from > dpu_encoder_virt. > > Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 2 -- > 1 file changed, 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index 401e37f50d54..480d02ccff8c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -127,7 +127,6 @@ enum dpu_enc_rc_states { > * Virtual encoder registers itself with the DRM Framework as the encoder. > * @base: drm_encoder base class for registration with DRM > * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes > - * @bus_scaling_client: Client handle to the bus scaling interface > * @enabled: True if the encoder is active, protected by enc_lock > * @num_phys_encs: Actual number of physical encoders contained. > * @phys_encs: Container of physical encoders managed. > @@ -172,7 +171,6 @@ enum dpu_enc_rc_states { > struct dpu_encoder_virt { > struct drm_encoder base; > spinlock_t enc_spinlock; > - uint32_t bus_scaling_client; > > bool enabled; > > -- > 2.34.1 >
Quoting Dmitry Baryshkov (2022-02-15 06:16:39) > We do not use MSM bus client, so drop bus_scaling_client field from > dpu_encoder_virt. > > Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com> > Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> > --- Reviewed-by: Stephen Boyd <swboyd@chromium.org>
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 401e37f50d54..480d02ccff8c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -127,7 +127,6 @@ enum dpu_enc_rc_states { * Virtual encoder registers itself with the DRM Framework as the encoder. * @base: drm_encoder base class for registration with DRM * @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes - * @bus_scaling_client: Client handle to the bus scaling interface * @enabled: True if the encoder is active, protected by enc_lock * @num_phys_encs: Actual number of physical encoders contained. * @phys_encs: Container of physical encoders managed. @@ -172,7 +171,6 @@ enum dpu_enc_rc_states { struct dpu_encoder_virt { struct drm_encoder base; spinlock_t enc_spinlock; - uint32_t bus_scaling_client; bool enabled;