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[209.132.180.131]) by mx.google.com with ESMTPS id 31-v6si16394824plg.296.2018.10.02.09.19.36 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 02 Oct 2018 09:19:37 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-486815-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=Udwq5CuN; dkim=pass header.i=@linaro.org header.s=google header.b=Rn+23t0L; spf=pass (google.com: domain of gcc-patches-return-486815-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom="gcc-patches-return-486815-patch=linaro.org@gcc.gnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=K4HiLodp1amq ySNDqxau3ReQUGdn0HgjOaQuOnBLeZ6XzLEsopKGW8MIpSdl5JN5dQZdoBKmTwqj INJFq7pewNyTumEsyawvcP1wgduCrx3283B6sJ/8/Z7Bx/Q7oTZPA1c55XIYqBA+ Fq2KeH7Ja7025VY1YQFxqIp+1oa3s6A= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=0796RnUJbY/QUiz+/z J1iLqNFM8=; b=Udwq5CuNR/ClheIJe3KSwD+xGfVoYTgNMERGUq1zgcT7P9iyYh Dh9C1O4jh8nYOEK9xMWh4O2Pibsl6VqojHAgQQinGheI+LrcMznEpBxcieD0Ef8m F26j8lpaBa5PcPY7ehwHTQrq0BC/3O7tzLd6hVACt3dIQQZIgazQY1LKk= Received: (qmail 65999 invoked by alias); 2 Oct 2018 16:19:24 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 65988 invoked by uid 89); 2 Oct 2018 16:19:23 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-11.9 required=5.0 tests=BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=HX-Received:sk:26-v6mr, Implement, CAS, cas X-HELO: mail-oi1-f169.google.com Received: from mail-oi1-f169.google.com (HELO mail-oi1-f169.google.com) (209.85.167.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 02 Oct 2018 16:19:22 +0000 Received: by mail-oi1-f169.google.com with SMTP id 22-v6so1014352oiz.2 for ; Tue, 02 Oct 2018 09:19:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id; bh=rLnjcqpCfrrGkJSgMoVd8f9D/kFaXg371v3dBAsGKIc=; b=Rn+23t0LpAk+4Hyd2mxFfZVuA8/0wKMcFaictBZ207eXBMtMk3M8/WFlM7NAy6e6+Z TZsd/Kma0BJn1eAb2GC+bBNjjxbJWwkESKsgjZITupZ/nw2qZWyAxyYURLv8/9mOLaDI PweDGwb7HCdPaSpPG/HxyBZh4USfHeji133lI= Return-Path: Received: from cloudburst.twiddle.net ([187.217.227.243]) by smtp.gmail.com with ESMTPSA id j15-v6sm145987oth.27.2018.10.02.09.19.16 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 02 Oct 2018 09:19:17 -0700 (PDT) From: Richard Henderson To: gcc-patches@gcc.gnu.org Cc: ramana.radhakrishnan@arm.com, agraf@suse.de, marcus.shawcroft@arm.com, james.greenhalgh@arm.com, richard.earnshaw@arm.com Subject: [PATCH, AArch64 v2 00/11] LSE atomics out-of-line Date: Tue, 2 Oct 2018 11:19:04 -0500 Message-Id: <20181002161915.18843-1-richard.henderson@linaro.org> Changes since v1: * Use config/t-slibgcc-libgcc instead of gcc.c changes. * Some style fixes. * Ifdefs to work with old glibc. * Force TImode registers into even regnos. Required by CASP, allowed by the ABI, and is seen as the simplier solution than adding two new register classes. * Use match_dup instead of matching constraints for CAS{P}. Matching constraints result in lots of extraneous moves for TImode, and keeping the expander interface the same for non-TImode simplifies the code. r~ Richard Henderson (11): aarch64: Simplify LSE cas generation aarch64: Improve cas generation aarch64: Improve swp generation aarch64: Improve atomic-op lse generation aarch64: Emit LSE st instructions Add visibility to libfunc constructors aarch64: Add out-of-line functions for LSE atomics aarch64: Implement -matomic-ool aarch64: Force TImode values into even registers aarch64: Implement TImode compare-and-swap Enable -matomic-ool by default gcc/config/aarch64/aarch64-protos.h | 20 +- gcc/optabs-libfuncs.h | 2 + gcc/common/config/aarch64/aarch64-common.c | 6 +- gcc/config/aarch64/aarch64.c | 494 +++++++------- gcc/optabs-libfuncs.c | 26 +- .../atomic-comp-swap-release-acquire.c | 2 +- .../gcc.target/aarch64/atomic-inst-ldadd.c | 18 +- .../gcc.target/aarch64/atomic-inst-ldlogic.c | 54 +- .../gcc.target/aarch64/atomic-op-acq_rel.c | 2 +- .../gcc.target/aarch64/atomic-op-acquire.c | 2 +- .../gcc.target/aarch64/atomic-op-char.c | 2 +- .../gcc.target/aarch64/atomic-op-consume.c | 2 +- .../gcc.target/aarch64/atomic-op-imm.c | 2 +- .../gcc.target/aarch64/atomic-op-int.c | 2 +- .../gcc.target/aarch64/atomic-op-long.c | 2 +- .../gcc.target/aarch64/atomic-op-relaxed.c | 2 +- .../gcc.target/aarch64/atomic-op-release.c | 2 +- .../gcc.target/aarch64/atomic-op-seq_cst.c | 2 +- .../gcc.target/aarch64/atomic-op-short.c | 2 +- .../aarch64/atomic_cmp_exchange_zero_reg_1.c | 2 +- .../atomic_cmp_exchange_zero_strong_1.c | 2 +- .../gcc.target/aarch64/sync-comp-swap.c | 2 +- .../gcc.target/aarch64/sync-op-acquire.c | 2 +- .../gcc.target/aarch64/sync-op-full.c | 2 +- libgcc/config/aarch64/lse.c | 282 ++++++++ gcc/config/aarch64/aarch64.opt | 4 + gcc/config/aarch64/atomics.md | 608 ++++++++++-------- gcc/config/aarch64/iterators.md | 8 +- gcc/config/aarch64/predicates.md | 12 + gcc/doc/invoke.texi | 14 +- libgcc/config.host | 4 + libgcc/config/aarch64/t-lse | 48 ++ 32 files changed, 1058 insertions(+), 576 deletions(-) create mode 100644 libgcc/config/aarch64/lse.c create mode 100644 libgcc/config/aarch64/t-lse -- 2.17.1