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[209.132.180.131]) by mx.google.com with ESMTPS id w27si7069839pgc.170.2017.06.09.05.58.03 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Jun 2017 05:58:03 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-455531-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-455531-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-455531-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; q=dns; s= default; b=xXytk4Ohqi8xqW2u044stutdHKNjf4o7NNNwVnjXy6j96/tHQ/sU+ wPeY1ZaqEiZWXtKNlmzn0n32AIpl72q07CcGZIQF0DDPEjpc7YAtZ3U/kpjv0Nhx d75vqHypFw1Rv/Y3LDp9V9oqL5XQMaED89JqwnMTkkCY9+7eADkFXs= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references:mime-version:content-type; s=default; bh=xJ8VdnVa+8XP2I6YJGco+4S+aNU=; b=KbX7P3XKygkp6EJ9mHC31OIDIvyy ZYghbKXEQlYzizlQUxSQeg8N5LfMJkFQKWEPR+iQcas5U661UivYuCS+FaIXESBm Oz2DUWX1vzq+vgZfY4ODyOUbNonhdrAmL8l3bcW6A9h9nJuOh3jxjc+jh3C/pTHW 3c8ZIO4casCKPzE= Received: (qmail 85337 invoked by alias); 9 Jun 2017 12:54:35 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 84082 invoked by uid 89); 9 Jun 2017 12:54:32 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.2 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, SPF_SOFTFAIL autolearn=ham version=3.3.2 spammy=sensible X-HELO: eggs.gnu.org Received: from eggs.gnu.org (HELO eggs.gnu.org) (208.118.235.92) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 09 Jun 2017 12:54:28 +0000 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1dJJQo-0007gK-Je for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:31 -0400 Received: from foss.arm.com ([217.140.101.70]:47128) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1dJJQo-0007Te-9E for gcc-patches@gcc.gnu.org; Fri, 09 Jun 2017 08:54:26 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F385A1650; Fri, 9 Jun 2017 05:54:25 -0700 (PDT) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1AA5A3F3E1; Fri, 9 Jun 2017 05:54:24 -0700 (PDT) From: Richard Earnshaw To: gcc-patches@gcc.gnu.org Cc: Richard Earnshaw , Joel Sherrill , Ralf Corsepius , Sebastian Huber Subject: [PATCH 23/30] [arm][rtems] Update t-rtems for new option framework Date: Fri, 9 Jun 2017 13:53:52 +0100 Message-Id: <0c71bd43a66e3cffceae8adbca9fd5f3c199e438.1497004220.git.Richard.Earnshaw@arm.com> In-Reply-To: References: In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 217.140.101.70 [This patch has only been fairly lightly tested (I've built a compiler with all the relevant multilibs and smoke-tested a few combinations to check that the tools still produce a sensible object file).] This patch updates the RTEMS build to use the new option framework. It tries as far as possible to keep the existing supported options, but there are two necessary changes and one cleanup. I've also restructed the file slightly to make it slightly easier (IMO) to understand. Necessary changes: 1: ARMv4t does not support a hard-float ABI, the earliest supported architecture with floating-point support is ARMv5te, so I've rebased the original fpu/hard libraries to that revision of the architecture. 2: Similarly, the earliest version of the -m profile to support hardware floating-point is armv7e-m (not armv7-m), so the base architecture for m-profile with FP has been correspondingly updated. Clean-up: 1: For greater consistency I've changed the -mcpu=cortex-m7/-mfpu=fpv5-d16/-mhard-float to -march=armv7e-m+fp.dp/-mhard-float. The built-in -mcpu rewrite rules take care of mapping the existing option sets onto the architecture string to ensure compatibility. Since the existing rule set does not contain any MULTILIB_REUSE rules, I have not added any here this time around, but it would be worth the maintainers of this file considering whether adding some rules would make their toolchain more friendly to users. Finally, I've added lines to reset all the multilib variables at the head of the file. I found during testing that some definitions from t-arm-elf were leaking through and causing unexpected behviour. * config/arm/t-rtems: Rewrite for new option framework. --- gcc/config/arm/t-rtems | 49 ++++++++++++++++++++++++++++++++----------------- 1 file changed, 32 insertions(+), 17 deletions(-) diff --git a/gcc/config/arm/t-rtems b/gcc/config/arm/t-rtems index 026a589..c073786 100644 --- a/gcc/config/arm/t-rtems +++ b/gcc/config/arm/t-rtems @@ -1,22 +1,37 @@ # Custom RTEMS multilibs for ARM -MULTILIB_OPTIONS = mbig-endian mthumb march=armv6-m/march=armv7-a/march=armv7-r/march=armv7-m/mcpu=cortex-m7 mfpu=neon/mfpu=vfp/mfpu=vfpv3-d16/mfpu=fpv4-sp-d16/mfpu=fpv5-d16 mfloat-abi=hard -MULTILIB_DIRNAMES = eb thumb armv6-m armv7-a armv7-r armv7-m cortex-m7 neon vfp vfpv3-d16 fpv4-sp-d16 fpv5-d16 hard +# Reset all MULTILIB variables + +MULTILIB_OPTIONS = +MULTILIB_DIRNAMES = +MULTILIB_EXCEPTIONS = +MULTILIB_REUSE = +MULTILIB_MATCHES = +MULTILIB_REQUIRED = # Enumeration of multilibs -MULTILIB_EXCEPTIONS = - -MULTILIB_REQUIRED = -MULTILIB_REQUIRED += mbig-endian/mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mbig-endian/mthumb/march=armv7-r -MULTILIB_REQUIRED += mfpu=vfp/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv6-m -MULTILIB_REQUIRED += mthumb/march=armv7-a/mfpu=neon/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7-a -MULTILIB_REQUIRED += mthumb/march=armv7-r/mfpu=vfpv3-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7-r -MULTILIB_REQUIRED += mthumb/march=armv7-m/mfpu=fpv4-sp-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/mcpu=cortex-m7/mfpu=fpv5-d16/mfloat-abi=hard -MULTILIB_REQUIRED += mthumb/march=armv7-m -MULTILIB_REQUIRED += mthumb +MULTILIB_OPTIONS += mbig-endian +MULTILIB_DIRNAMES += eb + +MULTILIB_OPTIONS += mthumb +MULTILIB_DIRNAMES += thumb + +MULTILIB_OPTIONS += march=armv5te+fp/march=armv6-m/march=armv7-a/march=armv7-a+simd/march=armv7-r/march=armv7-r+fp/march=armv7-m/march=armv7e-m+fp/march=armv7e-m+fp.dp +MULTILIB_DIRNAMES += armv5te+fp armv6-m armv7-a armv7-a+simd armv7-r armv7-r+fp armv7-m armv7e-m+fp armv7e-m+fp.dp + +MULTILIB_OPTIONS += mfloat-abi=hard +MULTILIB_DIRNAMES += hard + +MULTILIB_REQUIRED += mbig-endian/mthumb/march=armv7-r+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mbig-endian/mthumb/march=armv7-r +MULTILIB_REQUIRED += march=armv5te+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv6-m +MULTILIB_REQUIRED += mthumb/march=armv7-a+simd/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7-a +MULTILIB_REQUIRED += mthumb/march=armv7-r+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7-r +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7e-m+fp.dp/mfloat-abi=hard +MULTILIB_REQUIRED += mthumb/march=armv7-m +MULTILIB_REQUIRED += mthumb