From patchwork Thu Dec 15 16:06:28 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 88181 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp880579qgi; Thu, 15 Dec 2016 08:07:58 -0800 (PST) X-Received: by 10.99.63.135 with SMTP id m129mr3418241pga.16.1481818078072; Thu, 15 Dec 2016 08:07:58 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id o5si3130201plh.162.2016.12.15.08.07.57 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Dec 2016 08:07:58 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-444523-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-444523-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-444523-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; q=dns; s=default; b=MVXAL4Whb4tWnvdzssWjr/Q35Vhh5 jTlS9wLbmAx748KyseJuf9elyvuBmV3zc1u67GRD4HJSUZ+XrO0SSH7a880WygiC DCML4hkfvehTdjL7Ync19SnfXd05yBEVIm/eWwQa1/UJKMq1vCJHa75Jc8319gLj 4IkXg38RB1nYxY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; s=default; bh=9xgRLrUmZ3JPL1TLeUTk8kWFbV0=; b=OWi dhSW1kLVaB7eFJ8+W07ET3PQTeumD8PHenLw8NPwh1Mvq6ENDSTJrReZ5txMFTwA OVjVYOVyCPc+iNHATEzEEaZUetfCOLSKeJIJ9gtxj4MeTYM10AX1kt5Lp8D0fL6r 3ULrUdtuWZ22UqxcKsGg1oCViEUX+I6rawaBYVcQ= Received: (qmail 35144 invoked by alias); 15 Dec 2016 16:06:34 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 35085 invoked by uid 89); 15 Dec 2016 16:06:33 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.0 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=interest X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Dec 2016 16:06:31 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 634AF1570; Thu, 15 Dec 2016 08:06:30 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 13D9D3F445 for ; Thu, 15 Dec 2016 08:06:29 -0800 (PST) From: "Richard Earnshaw (lists)" Subject: [PATCH 09/21] [arm] Rework arm-common to use new feature bits. To: gcc-patches@gcc.gnu.org References: Message-ID: <0c996fea-b97a-74a5-6e74-438bee7a76c5@arm.com> Date: Thu, 15 Dec 2016 16:06:28 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: This converts the recently added implicit -mthumb support code to use the new data structures. Since we have a very simple query and no initialized copies of the sbitmaps, for now we simply scan the list of features to look for the one of interest. * arm-opts.h (struct arm_arch_core_flag): Add new field ISA. Initialize it. (arm_arch_core_flag): Delete flags field. (arm_arch_core_flags): Don't initialize flags field. * common/config/arm/arm-common.c (check_isa_bits_for): New function. (arm_target_thumb_only): Use new isa bits arrays. --- gcc/common/config/arm/arm-common.c | 23 +++++++++++++++++++---- gcc/config/arm/arm-opts.h | 1 + 2 files changed, 20 insertions(+), 4 deletions(-) diff --git a/gcc/common/config/arm/arm-common.c b/gcc/common/config/arm/arm-common.c index 79e3f1f..dca3682 100644 --- a/gcc/common/config/arm/arm-common.c +++ b/gcc/common/config/arm/arm-common.c @@ -101,23 +101,37 @@ arm_rewrite_mcpu (int argc, const char **argv) struct arm_arch_core_flag { const char *const name; - const arm_feature_set flags; + const enum isa_feature isa_bits[isa_num_bits]; }; static const struct arm_arch_core_flag arm_arch_core_flags[] = { #undef ARM_CORE #define ARM_CORE(NAME, X, IDENT, TUNE_FLAGS, ARCH, ISA, FLAGS, COSTS) \ - {NAME, FLAGS}, + {NAME, {ISA isa_nobit}}, #include "config/arm/arm-cores.def" #undef ARM_CORE #undef ARM_ARCH #define ARM_ARCH(NAME, CORE, TUNE_FLAGS, ARCH, ISA, FLAGS) \ - {NAME, FLAGS}, + {NAME, {ISA isa_nobit}}, #include "config/arm/arm-arches.def" #undef ARM_ARCH }; +/* Scan over a raw feature array BITS checking for BIT being present. + This is slower than the normal bitmask checks, but we would spend longer + initializing that than doing the check this way. Returns true iff + BIT is found. */ +static bool +check_isa_bits_for (const enum isa_feature* bits, enum isa_feature bit) +{ + while (*bits != isa_nobit) + if (*bits++ == bit) + return true; + + return false; +} + /* Called by the driver to check whether the target denoted by current command line options is a Thumb-only target. ARGV is an array of -march and -mcpu values (ie. it contains the rhs after the equal @@ -132,7 +146,8 @@ arm_target_thumb_only (int argc, const char **argv) { for (opt = 0; opt < (ARRAY_SIZE (arm_arch_core_flags)); opt++) if ((strcmp (argv[argc - 1], arm_arch_core_flags[opt].name) == 0) - && !ARM_FSET_HAS_CPU1(arm_arch_core_flags[opt].flags, FL_NOTM)) + && !check_isa_bits_for (arm_arch_core_flags[opt].isa_bits, + isa_bit_notm)) return "-mthumb"; return NULL; diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h index a62ac46..52c69e9 100644 --- a/gcc/config/arm/arm-opts.h +++ b/gcc/config/arm/arm-opts.h @@ -26,6 +26,7 @@ #define ARM_OPTS_H #include "arm-flags.h" +#include "arm-isa.h" /* The various ARM cores. */ enum processor_type