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[209.132.180.131]) by mx.google.com with ESMTPS id t32si7768157ioi.154.2015.10.02.01.12.59 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 02 Oct 2015 01:12:59 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-408946-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 104875 invoked by alias); 2 Oct 2015 08:12:48 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 104866 invoked by uid 89); 2 Oct 2015 08:12:47 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 02 Oct 2015 08:12:46 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-24-PNaypRbKQVeZhV08xHcWiA-1; Fri, 02 Oct 2015 09:12:40 +0100 Received: from e107456-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 2 Oct 2015 09:12:40 +0100 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus.shawcroft@arm.com, richard.earnshaw@arm.com Subject: [Patch AArch64] Improve SIMD concatenation with zeroes Date: Fri, 2 Oct 2015 09:12:36 +0100 Message-Id: <1443773556-11626-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: PNaypRbKQVeZhV08xHcWiA-1 X-IsSubscribed: yes X-Original-Sender: james.greenhalgh@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::22a as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, In AArch64, SIMD instructions which only touch the bottom 64-bits of a vector register write zeroes to the upper 64-bits. In other words, we have a cheap way to implement a "zero extend" of a SIMD operation, and can generate efficient code for: [(set (match_operand 0) (vec_concat:128-bit mode (other vector operations in a 64-bit mode) (match_operand 2 [zeroes])))] And for the big-endian equivalent of this. This small patch catches two important cases of this, namely loading a 64-bit vector and moving a 64-bit vector from general purpose registers to vector registers. Bootstrapped on aarch64-none-linux-gnu with no issues, and aarch64.exp run for aarch64_be-none-elf. Ok for trunk? Thanks, James --- gcc/ 2015-10-01 James Greenhalgh * config/aarch64/aarch64-simd.md (*aarch64_combinez): Add alternatives for reads from memory and moves from general-purpose registers. (*aarch64_combinez_be): Likewise. 2015-10-01 James Greenhalgh * gcc.target/aarch64/vect_combine_zeroes_1.c: New. diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 541faf9..6a2ab61 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -2530,23 +2530,33 @@ ;; dest vector. (define_insn "*aarch64_combinez" - [(set (match_operand: 0 "register_operand" "=&w") + [(set (match_operand: 0 "register_operand" "=w,w,w") (vec_concat: - (match_operand:VD_BHSI 1 "register_operand" "w") - (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz")))] + (match_operand:VD_BHSI 1 "general_operand" "w,r,m") + (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz")))] "TARGET_SIMD && !BYTES_BIG_ENDIAN" - "mov\\t%0.8b, %1.8b" - [(set_attr "type" "neon_move")] + "@ + mov\\t%0.8b, %1.8b + fmov\t%d0, %1 + ldr\\t%d0, %1" + [(set_attr "type" "neon_move, neon_from_gp, neon_load1_1reg") + (set_attr "simd" "yes,*,yes") + (set_attr "fp" "*,yes,*")] ) (define_insn "*aarch64_combinez_be" - [(set (match_operand: 0 "register_operand" "=&w") + [(set (match_operand: 0 "register_operand" "=w,w,w") (vec_concat: - (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz") - (match_operand:VD_BHSI 1 "register_operand" "w")))] + (match_operand:VD_BHSI 2 "aarch64_simd_imm_zero" "Dz,Dz,Dz") + (match_operand:VD_BHSI 1 "general_operand" "w,r,m")))] "TARGET_SIMD && BYTES_BIG_ENDIAN" - "mov\\t%0.8b, %1.8b" - [(set_attr "type" "neon_move")] + "@ + mov\\t%0.8b, %1.8b + fmov\t%d0, %1 + ldr\\t%d0, %1" + [(set_attr "type" "neon_move, neon_from_gp, neon_load1_1reg") + (set_attr "simd" "yes,*,yes") + (set_attr "fp" "*,yes,*")] ) (define_expand "aarch64_combine" diff --git a/gcc/testsuite/gcc.target/aarch64/vect_combine_zeroes_1.c b/gcc/testsuite/gcc.target/aarch64/vect_combine_zeroes_1.c new file mode 100644 index 0000000..6257fa9 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/vect_combine_zeroes_1.c @@ -0,0 +1,24 @@ +/* { dg-options "-O2 --save-temps" } */ + +#include "arm_neon.h" + +int32x4_t +foo (int32x2_t *x) +{ + int32x2_t i = *x; + int32x2_t zeroes = vcreate_s32 (0l); + int32x4_t ret = vcombine_s32 (i, zeroes); + return ret; +} + +int32x4_t +bar (int64_t x) +{ + int32x2_t i = vcreate_s32 (x); + int32x2_t zeroes = vcreate_s32 (0l); + int32x4_t ret = vcombine_s32 (i, zeroes); + return ret; +} + +/* { dg-final { scan-assembler-not "mov\tv\[0-9\]+.8b, v\[0-9\]+.8b" } } */ +