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[209.132.180.131]) by mx.google.com with ESMTPS id yp1si51013594pbc.152.2015.11.16.06.37.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 16 Nov 2015 06:37:23 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-414241-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-return-414241-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-414241-patch=linaro.org@gcc.gnu.org; dkim=pass header.i=@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=tugICQM0Oht0jrHNEPLiXkWEJj8EqeDhc4LZfoBGidZCqNENKq +Pz4kEopM2YdV+aiOhJpUSXyVdh98vH0YsPVXE4i7Xj4dMS4kitGbVOn/MTSftd6 zYx3NtY0U8oJq3H9AcctELgBK0PEPGBmFtCW7xBafU2KhmOEcj8m4q2/I= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=yX0T7wa1WcnvZUQwZE4+U6PyYL4=; b=S69b5XbazVVDakG/6Vka hdndo/WHxsO2std5lg4ePRexGeKcVyaUcU5Wuvs6dmvhnQfztrv89+zlQfTzD/tO juwf87J5wyIQNpcu8TStlEJkDzh3o/6ArgI7qg3o4MMrIaG4Gf1uwGP8fMZXmLs/ JBMG75mXnRwB9a9FraNfC8A= Received: (qmail 68659 invoked by alias); 16 Nov 2015 14:37:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 68646 invoked by uid 89); 16 Nov 2015 14:37:10 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 16 Nov 2015 14:37:09 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-22-mb_kjM2SRXm0AsGpfrp0iA-1; Mon, 16 Nov 2015 14:37:03 +0000 Received: from e107456-lin.cambridge.arm.com ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 16 Nov 2015 14:37:02 +0000 From: James Greenhalgh To: gcc-patches@gcc.gnu.org Cc: marcus.shawcroft@arm.com, richard.earnshaw@arm.com Subject: [Patch AArch64] Add support for Cortex-A35 Date: Mon, 16 Nov 2015 14:36:58 +0000 Message-Id: <1447684618-37158-1-git-send-email-james.greenhalgh@arm.com> MIME-Version: 1.0 X-MC-Unique: mb_kjM2SRXm0AsGpfrp0iA-1 X-IsSubscribed: yes Hi, This patch adds support to the AArch64 back-end for the Cortex-A35 processor, as recently announced by ARM. The ARM Cortex-A35 provides full support for the ARMv8-A architecture, including the CRC extension, with optional Advanced-SIMD and Floating-Point support. We therefore set feature flags for this CPU to AARCH64_FL_FOR_ARCH8 and AARCH64_FL_CRC, in the same fashion as Cortex-A53 and Cortex-A57. While the Cortex-A35 supports dual-issue, we model it as single issue with the expectation that this will give better schedules when sharing the Cortex-A53 pipeline model. Bootstrapped with --with-cpu=cortex-a35 with no issues. I'm sorry to have got this upstream a little late for the end of Stage 1, but if it is OK with the AArch64 maintainers I'd like to get it in for GCC 6. OK? Thanks, James --- 2015-11-16 James Greenhalgh * config/aarch64/aarch64-cores.def (cortex-a35): New. * config/aarch64/aarch64.c (cortexa35_tunings): New. * config/aarch64/aarch64-tune.md: Regenerate. * doc/invoke.texi (-mcpu): Add Cortex-A35 diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 4af70ca..f8fab28 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -40,6 +40,7 @@ /* V8 Architecture Processors. */ +AARCH64_CORE("cortex-a35", cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, "0x41", "0xd04") AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, "0x41", "0xd03") AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, "0x41", "0xd07") AARCH64_CORE("cortex-a72", cortexa72, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa72, "0x41", "0xd08") diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index c65a124..cbc6f48 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53" + "cortexa35,cortexa53,cortexa57,cortexa72,exynosm1,qdf24xx,thunderx,xgene1,cortexa57cortexa53,cortexa72cortexa53" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 5ec7f08..8569385 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -362,6 +362,31 @@ static const struct tune_params generic_tunings = (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ }; +static const struct tune_params cortexa35_tunings = +{ + &cortexa53_extra_costs, + &generic_addrcost_table, + &cortexa53_regmove_cost, + &generic_vector_cost, + &generic_branch_cost, + 4, /* memmov_cost */ + 1, /* issue_rate */ + (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD + | AARCH64_FUSE_MOVK_MOVK | AARCH64_FUSE_ADRP_LDR), /* fusible_ops */ + 8, /* function_align. */ + 8, /* jump_align. */ + 4, /* loop_align. */ + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + 0, /* cache_line_size. */ + tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ + (AARCH64_EXTRA_TUNE_NONE) /* tune_flags. */ +}; + static const struct tune_params cortexa53_tunings = { &cortexa53_extra_costs, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index c18df98..d782ab2 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12576,8 +12576,9 @@ processors implementing the target architecture. @opindex mtune Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: -@samp{generic}, @samp{cortex-a53}, @samp{cortex-a57}, @samp{cortex-a72}, -@samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx}, @samp{xgene1}. +@samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a57}, +@samp{cortex-a72}, @samp{exynos-m1}, @samp{qdf24xx}, @samp{thunderx}, +@samp{xgene1}. Additionally, this option can specify that GCC should tune the performance of the code for a big.LITTLE system. Permissible values for this