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[209.132.180.131]) by mx.google.com with ESMTPS id d8si4800313plj.419.2017.06.29.13.54.22 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 29 Jun 2017 13:54:22 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-457234-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.b=YE/kfYck; spf=pass (google.com: domain of gcc-patches-return-457234-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-457234-patch=linaro.org@gcc.gnu.org; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=iiKgo2WUDssu vOneUGDXtlnHyqalAiXsYedDMbrWlIT+JbJfz4lE3ifjuZPAtH8sv4GLb7pJucug rM1aA1BmKlzWh9uB2EfHZ6q8xWTQHw7GL5F5WcbueAFIt8NcgXNafSVZKB0FInH3 b+uWXUVeN/OXt05cd5fNetDeXVuiP64= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=o4zJd6YGSwEfI+dHFs EK6Bq/4Mw=; b=YE/kfYckWKGB4NExJskZl3LvcLo6zATujx1HrA+A6uSPNZ02tj ydbrJKTIXIk4qIVJUuHwdhTa9WNty083o5NNyMO4HMYaeARULSgt9BdRPbAQGZxA HEU+0ea3HG0dh5UrbvjKr71Zsu/8ahWsZ34kKA+tBUWgzuXvrce8BQdcA= Received: (qmail 56218 invoked by alias); 29 Jun 2017 20:54:04 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 56203 invoked by uid 89); 29 Jun 2017 20:54:04 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.4 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, RCVD_IN_SORBS_SPAM, SPF_PASS autolearn=ham version=3.3.2 spammy= X-HELO: mail-oi0-f54.google.com Received: from mail-oi0-f54.google.com (HELO mail-oi0-f54.google.com) (209.85.218.54) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 29 Jun 2017 20:54:01 +0000 Received: by mail-oi0-f54.google.com with SMTP id p188so21016368oia.0 for ; Thu, 29 Jun 2017 13:54:01 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=BtjdNNoCQrGf1s5CakLxiWnQ4EiWtyDCsI8Vjll4l2U=; b=VNFF95v6Dw7Ki3e8Viz1JgaQXJPguFh8aMpiPDy5aJuH9tlH37/qUrlTn2BuOeQCDP S7N31fgeTjbqj9fefXf75yttXWkRLjHy8wjST8hAeGUoMxGJbNe+9njTgSEghhGbYgGu JK9tkJjWUuXqas7hwrgOB+lZc/gLPjx57085HKk/aPjUd+xx4Tl4Qt1VhhtX2bG/vLlT 7a4tLZby4SmEtqZ4kig1HF4eOIVICM0crpBEqIqg+G8dR+Hsj30ZEP5kID31PjP+fNXa uLGLtsZQguiDGffN8WEj8P5y4t+TqZ/bZsWr36P3nbbpPoNrCGbZWHVjW0V5Du/NpCAz khqw== X-Gm-Message-State: AKS2vOx9tPF4RaZnNM/ul712oesrtGX6FUXNQLejWroGlszZxlZSGSff Qfo+Et9/kPM6JBZlKrQ/0g== X-Received: by 10.202.82.74 with SMTP id g71mr5429145oib.177.1498769639350; Thu, 29 Jun 2017 13:53:59 -0700 (PDT) Received: from r3-a15.aus-colo ([64.28.108.36]) by smtp.gmail.com with ESMTPSA id t130sm10938151oig.3.2017.06.29.13.53.57 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 29 Jun 2017 13:53:58 -0700 (PDT) From: Jim Wilson To: gcc-patches@gcc.gnu.org Cc: Jim Wilson Subject: [PATCH] Add RDMA support to Falkor. Date: Thu, 29 Jun 2017 15:53:52 -0500 Message-Id: <1498769632-43280-1-git-send-email-jim.wilson@linaro.org> Falkor is an ARMV8-A part, but also includes the RDMA extension from ARMV8.1-A. I'd like to enable support for the RDMA instructions when -mcpu=falkor is used, and also make the RDMA intrisics available. To do that, I need to add rdma as an architecture extension, and modify a few things to use it. Binutils already supports rdma as an architecture extension. I only did the aarch64 port, and not the arm port. There are no supported targets that have the RDMA instructions and also aarch32 support. There are also no aarch32 RDMA testcases. So there is no way to test it. It wasn't clear whether it was better to add something untested or leave it out. I chose to leave it out for now. I also needed a few testcase changes. There were redundant options being added for the RDMA tests that I had to remove as they are now wrong. Also the fact that I only did aarch64 means we need to check both armv8-a+rdma and armv8.1-a for the rdma support. This was tested with an aarch64 bootstrap and make check. There were no regressions. OK? Jim gcc/ * config/aarch64/aarch64-cores.def (falkor): Add AARCH64_FL_RDMA. (qdf24xx): Likewise. * config/aarch64/aarch64-options-extensions.def (rdma); New. * config/aarch64/aarch64.h (AARCH64_FL_RDMA): New. (AARCH64_FL_V8_1): Renumber. (AARCH64_FL_FOR_ARCH8_1): Add AARCH64_FL_RDMA. (AARCH64_ISA_RDMA): Use AARCH64_FL_RDMA. * config/aarch64/arm_neon.h: Use +rdma instead of arch=armv8.1-a. * doc/invoke.texi (AArch64 Options): Mention +rmda in -march docs. Add rdma to feature modifiers list. gcc/testsuite/ * lib/target-supports.exp (add_options_for_arm_v8_1a_neon): Delete redundant -march option. (check_effective_target_arm_v8_1a_neon_ok_nocache): Try armv8-a+rdma in addition to armv8.1-a. --- gcc/config/aarch64/aarch64-cores.def | 4 ++-- gcc/config/aarch64/aarch64-option-extensions.def | 4 ++++ gcc/config/aarch64/aarch64.h | 8 +++++--- gcc/config/aarch64/arm_neon.h | 2 +- gcc/doc/invoke.texi | 5 ++++- gcc/testsuite/lib/target-supports.exp | 18 ++++++++++-------- 6 files changed, 26 insertions(+), 15 deletions(-) -- 2.7.4 diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index f8342ca..b8d0ba6 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -65,8 +65,8 @@ AARCH64_CORE("thunderxt83", thunderxt83, thunderx, 8A, AARCH64_FL_FOR_ARCH AARCH64_CORE("xgene1", xgene1, xgene1, 8A, AARCH64_FL_FOR_ARCH8, xgene1, 0x50, 0x000, -1) /* Qualcomm ('Q') cores. */ -AARCH64_CORE("falkor", falkor, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00, -1) -AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, qdf24xx, 0x51, 0xC00, -1) +AARCH64_CORE("falkor", falkor, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx, 0x51, 0xC00, -1) +AARCH64_CORE("qdf24xx", qdf24xx, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO | AARCH64_FL_RDMA, qdf24xx, 0x51, 0xC00, -1) /* Samsung ('S') cores. */ AARCH64_CORE("exynos-m1", exynosm1, exynosm1, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC | AARCH64_FL_CRYPTO, exynosm1, 0x53, 0x001, -1) diff --git a/gcc/config/aarch64/aarch64-option-extensions.def b/gcc/config/aarch64/aarch64-option-extensions.def index c0752ce..c4f059a 100644 --- a/gcc/config/aarch64/aarch64-option-extensions.def +++ b/gcc/config/aarch64/aarch64-option-extensions.def @@ -63,4 +63,8 @@ AARCH64_OPT_EXTENSION("fp16", AARCH64_FL_F16, AARCH64_FL_FP, 0, "fphp asimdhp") /* Enabling or disabling "rcpc" only changes "rcpc". */ AARCH64_OPT_EXTENSION("rcpc", AARCH64_FL_RCPC, 0, 0, "lrcpc") +/* Enabling "rdma" also enables "fp", "simd". + Disabling "rdma" just disables "rdma". */ +AARCH64_OPT_EXTENSION("rdma", AARCH64_FL_RDMA, AARCH64_FL_FP | AARCH64_FL_SIMD, 0, "rdma") + #undef AARCH64_OPT_EXTENSION diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 106cf3a..7f91edb 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -144,7 +144,8 @@ extern unsigned aarch64_architecture_version; #define AARCH64_FL_CRC (1 << 3) /* Has CRC. */ /* ARMv8.1-A architecture extensions. */ #define AARCH64_FL_LSE (1 << 4) /* Has Large System Extensions. */ -#define AARCH64_FL_V8_1 (1 << 5) /* Has ARMv8.1-A extensions. */ +#define AARCH64_FL_RDMA (1 << 5) /* Has Round Double Multiply Add. */ +#define AARCH64_FL_V8_1 (1 << 6) /* Has ARMv8.1-A extensions. */ /* ARMv8.2-A architecture extensions. */ #define AARCH64_FL_V8_2 (1 << 8) /* Has ARMv8.2-A features. */ #define AARCH64_FL_F16 (1 << 9) /* Has ARMv8.2-A FP16 extensions. */ @@ -161,7 +162,8 @@ extern unsigned aarch64_architecture_version; /* Architecture flags that effect instruction selection. */ #define AARCH64_FL_FOR_ARCH8 (AARCH64_FL_FPSIMD) #define AARCH64_FL_FOR_ARCH8_1 \ - (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC | AARCH64_FL_V8_1) + (AARCH64_FL_FOR_ARCH8 | AARCH64_FL_LSE | AARCH64_FL_CRC \ + | AARCH64_FL_RDMA | AARCH64_FL_V8_1) #define AARCH64_FL_FOR_ARCH8_2 \ (AARCH64_FL_FOR_ARCH8_1 | AARCH64_FL_V8_2) #define AARCH64_FL_FOR_ARCH8_3 \ @@ -174,7 +176,7 @@ extern unsigned aarch64_architecture_version; #define AARCH64_ISA_FP (aarch64_isa_flags & AARCH64_FL_FP) #define AARCH64_ISA_SIMD (aarch64_isa_flags & AARCH64_FL_SIMD) #define AARCH64_ISA_LSE (aarch64_isa_flags & AARCH64_FL_LSE) -#define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_V8_1) +#define AARCH64_ISA_RDMA (aarch64_isa_flags & AARCH64_FL_RDMA) #define AARCH64_ISA_V8_2 (aarch64_isa_flags & AARCH64_FL_V8_2) #define AARCH64_ISA_F16 (aarch64_isa_flags & AARCH64_FL_F16) #define AARCH64_ISA_V8_3 (aarch64_isa_flags & AARCH64_FL_V8_3) diff --git a/gcc/config/aarch64/arm_neon.h b/gcc/config/aarch64/arm_neon.h index 0753da3..d7b30b0 100644 --- a/gcc/config/aarch64/arm_neon.h +++ b/gcc/config/aarch64/arm_neon.h @@ -12162,7 +12162,7 @@ vbslq_u64 (uint64x2_t __a, uint64x2_t __b, uint64x2_t __c) /* ARMv8.1-A instrinsics. */ #pragma GCC push_options -#pragma GCC target ("arch=armv8.1-a") +#pragma GCC target ("+nothing+rdma") __extension__ extern __inline int16x4_t __attribute__ ((__always_inline__, __gnu_inline__, __artificial__)) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index d1e097b..2bd10c6 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14082,7 +14082,7 @@ support for the ARMv8.2-A architecture extensions. The value @samp{armv8.1-a} implies @samp{armv8-a} and enables compiler support for the ARMv8.1-A architecture extension. In particular, it -enables the @samp{+crc} and @samp{+lse} features. +enables the @samp{+crc}, @samp{+lse}, and @samp{+rdma} features. The value @samp{native} is available on native AArch64 GNU/Linux and causes the compiler to pick the architecture of the host system. This @@ -14198,6 +14198,9 @@ instructions. This is on by default for all possible values for options @item lse Enable Large System Extension instructions. This is on by default for @option{-march=armv8.1-a}. +@item rdma +Enable Round Double Multiply Accumulate instructions. This is on by default +for @option{-march=armv8.1-a}. @item fp16 Enable FP16 extension. This also enables floating-point instructions. diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index fe5e777..a245eed 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3425,7 +3425,7 @@ proc add_options_for_arm_v8_1a_neon { flags } { return "$flags" } global et_arm_v8_1a_neon_flags - return "$flags $et_arm_v8_1a_neon_flags -march=armv8.1-a" + return "$flags $et_arm_v8_1a_neon_flags" } # Add the options needed for ARMv8.2 with the scalar FP16 extension. @@ -4115,13 +4115,15 @@ proc check_effective_target_arm_v8_1a_neon_ok_nocache { } { # since AArch64 only needs the -march setting. foreach flags {"" "-mfpu=neon-fp-armv8" "-mfloat-abi=softfp" \ "-mfpu=neon-fp-armv8 -mfloat-abi=softfp"} { - if { [check_no_compiler_messages_nocache arm_v8_1a_neon_ok object { - #if !defined (__ARM_FEATURE_QRDMX) - #error "__ARM_FEATURE_QRDMX not defined" - #endif - } "$flags -march=armv8.1-a"] } { - set et_arm_v8_1a_neon_flags "$flags -march=armv8.1-a" - return 1 + foreach arches { "-march=armv8-a+rdma" "-march=armv8.1-a" } { + if { [check_no_compiler_messages_nocache arm_v8_1a_neon_ok object { + #if !defined (__ARM_FEATURE_QRDMX) + #error "__ARM_FEATURE_QRDMX not defined" + #endif + } "$flags $arches"] } { + set et_arm_v8_1a_neon_flags "$flags $arches" + return 1 + } } }