From patchwork Fri Oct 27 12:43:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siddhesh Poyarekar X-Patchwork-Id: 117315 Delivered-To: patch@linaro.org Received: by 10.140.22.164 with SMTP id 33csp727570qgn; Fri, 27 Oct 2017 05:45:07 -0700 (PDT) X-Google-Smtp-Source: ABhQp+RUilEfOKLl05B4NCgB0f05+eDMFXQ6BSI/0qA+yh5pUTQd+823tdlXbFnnAp+vccodNUZF X-Received: by 10.84.242.74 with SMTP id c10mr302295pll.141.1509108307684; Fri, 27 Oct 2017 05:45:07 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1509108307; cv=none; d=google.com; s=arc-20160816; b=L4RY/EdFqbVVzUZq6Buj35wzNyvpt81Zp9GzvrH3kEQa+H0XeWwBZTSfmPQDsgiQN+ rInFQDuvO7sqxAmVfFFfrCx4nvg7NA+miafCbkAN8/oveUbdg/g5cv6whUXGySlnvH18 ShM2k1CAQ+F0rg35eYFNKUflPF69CisaOBviKS4DepkaSUAg0+nUOqMP7PCRuaOsm7d9 Zs5ztX6EEdh45k9pAVyXkBMzSyW3w6i2fODEhEGq+2QTmsDHTULIGgrfEeaq2b034sf+ 0C/PNJPR+qeEzFswjit+yGZSPJHYOZ2lupVu+hLmMKxgM33yk7aOZodEDqQXTuc/z16A WIGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=message-id:date:subject:cc:to:from:delivered-to:sender:list-help :list-post:list-archive:list-unsubscribe:list-id:precedence :mailing-list:dkim-signature:domainkey-signature :arc-authentication-results; bh=ykQZG3R4CBw7EZFP51WQ7f4PgrW30bk2RzakX7IrmJU=; b=FF61xQPCxNcP0pWVJ9GwSCTwhvNkb9svjMFlD2wMKc6yFlTCQgSxgIwLwiLlylGT/Q kM1EqHhb7JTHnepTSvC6V6gcHwp/305eiToSl4gD5hZOWVWv+EUl/Y35RJa4LFbtrk9F B3HfgT+5K/NtwnQMHYw559BfDdGlKkj/8Zh+upn4qFg8F0JFV8Tl6p86sESRj5wM8gei bJr0rVdSqy6GXrt68y37XV36cchaEUxpa39zAy+R/CLABcdhIWvNP/5wxLmmA3j1VjNX PGpJ8lotYnl+laKgkjnWV10WWPJZsJ6GZv6v8uXoI3IneY7nXv0usaWidRXI2piCEbB8 u3Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=jtf1GJiT; spf=pass (google.com: domain of gcc-patches-return-465331-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-465331-patch=linaro.org@gcc.gnu.org Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id y74si5351560pff.496.2017.10.27.05.45.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 27 Oct 2017 05:45:07 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-465331-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org header.s=default header.b=jtf1GJiT; spf=pass (google.com: domain of gcc-patches-return-465331-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-465331-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=bP5KnNhLHEMf bu1g+pT4//a+97WX6A6W90B9LjjGVV94GjR7cxaiS6qdxJcbuuXc8KrddlWMsWqi l0mTGh8d2o5RYd/Cv3sCWGXI56NQi5BfmBkGfgl1aD894USxrx2xSjJ1CHHJmHH0 vvqb8Z18JErU5JQmEX9ZfJjgT8qsWoc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=80ksCPK8jYwpNzXpXI /4usOAqYM=; b=jtf1GJiT2M+0lMASDSkBBMO2kk27Kw29vRUvUbFMG+YDRQywyA 6t49Y+Z79Q5nivT8/koIwmnNL5UoQpxlkUjOgrd7rkVigwhqo0YHDYhjQKxJT7lb sl0uPZu6K2kdFYTpgeei8iXhV8Yheic8DTc2PZyzBRyAdEF07eAWXHPzI= Received: (qmail 63767 invoked by alias); 27 Oct 2017 12:44:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 63666 invoked by uid 89); 27 Oct 2017 12:44:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE autolearn=ham version=3.3.2 spammy=vulcan, sk:siddhes, sk:thunder, siddhesh X-HELO: homiemail-a52.g.dreamhost.com Received: from sub5.mail.dreamhost.com (HELO homiemail-a52.g.dreamhost.com) (208.113.200.129) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Oct 2017 12:44:09 +0000 Received: from homiemail-a52.g.dreamhost.com (localhost [127.0.0.1]) by homiemail-a52.g.dreamhost.com (Postfix) with ESMTP id 012CF600315F; Fri, 27 Oct 2017 05:44:06 -0700 (PDT) Received: from devel.in.reserved-bit.com (unknown [202.189.238.75]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) (Authenticated sender: siddhesh@gotplt.org) by homiemail-a52.g.dreamhost.com (Postfix) with ESMTPSA id A7CCB600315C; Fri, 27 Oct 2017 05:44:04 -0700 (PDT) From: Siddhesh Poyarekar To: gcc-patches@gcc.gnu.org Cc: Richard.Earnshaw@foss.arm.com, Siddhesh Poyarekar Subject: [PATCH] New option saphira for Qualcomm server part Date: Fri, 27 Oct 2017 18:13:50 +0530 Message-Id: <1509108230-16347-1-git-send-email-siddhesh@gotplt.org> From: Siddhesh Poyarekar This patch adds an mcpu option for the Qualcomm saphira server part. Tested on aarch64 and did not find any regressions resulting from this patch. Siddhesh 2017-10-27 Siddhesh Poyarekar Jim Wilson gcc/ * config/aarch64/aarch64-cores.def (saphira): New. * config/aarch64/aarch64-tune.md: Regenerated. * doc/invoke.texi (AArch64 Options/-mtune): Add "saphira". * gcc/config/aarch64/aarch64.c (saphira_tunings): New. Change-Id: I23c4a1ab74e4376c3800cb1481c508bc27418508 --- gcc/config/aarch64/aarch64-cores.def | 5 +++++ gcc/config/aarch64/aarch64-tune.md | 2 +- gcc/config/aarch64/aarch64.c | 28 ++++++++++++++++++++++++++++ gcc/doc/invoke.texi | 2 +- 4 files changed, 35 insertions(+), 2 deletions(-) -- 2.7.4 diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 16e4485..cdf047c 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -86,6 +86,11 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1) AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1) +/* ARMv8.3-A Architecture Processors. */ + +/* Qualcomm ('Q') cores. */ +AARCH64_CORE("saphira", saphira, falkor, 8_3A, AARCH64_FL_FOR_ARCH8_3 | AARCH64_FL_CRYPTO | AARCH64_FL_RCPC, saphira, 0x51, 0xC01, -1) + /* ARMv8-A big.LITTLE implementations. */ AARCH64_CORE("cortex-a57.cortex-a53", cortexa57cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, AARCH64_BIG_LITTLE (0xd07, 0xd03), -1) diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index 7fcd6cb..7b3a746 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" + "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,thunderxt81,thunderxt83,xgene1,falkor,qdf24xx,exynosm1,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d1aaf19..f554ffb 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -822,6 +822,34 @@ static const struct tune_params qdf24xx_tunings = &qdf24xx_prefetch_tune }; +/* Tuning structure for the Qualcomm Saphira core. Default to falkor values + for now. */ +static const struct tune_params saphira_tunings = +{ + &generic_extra_costs, + &generic_addrcost_table, + &generic_regmove_cost, + &generic_vector_cost, + &generic_branch_cost, + &generic_approx_modes, + 4, /* memmov_cost */ + 4, /* issue_rate */ + (AARCH64_FUSE_MOV_MOVK | AARCH64_FUSE_ADRP_ADD + | AARCH64_FUSE_MOVK_MOVK), /* fuseable_ops */ + 16, /* function_align. */ + 8, /* jump_align. */ + 16, /* loop_align. */ + 2, /* int_reassoc_width. */ + 4, /* fp_reassoc_width. */ + 1, /* vec_reassoc_width. */ + 2, /* min_div_recip_mul_sf. */ + 2, /* min_div_recip_mul_df. */ + 0, /* max_case_values. */ + tune_params::AUTOPREFETCHER_WEAK, /* autoprefetcher_model. */ + (AARCH64_EXTRA_TUNE_NONE), /* tune_flags. */ + &generic_prefetch_tune +}; + static const struct tune_params thunderx2t99_tunings = { &thunderx2t99_extra_costs, diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 71b2445..bc480ad 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -14326,7 +14326,7 @@ Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, -@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, +@samp{exynos-m1}, @samp{falkor}, @samp{qdf24xx}, @samp{saphira}, @samp{xgene1}, @samp{vulcan}, @samp{thunderx}, @samp{thunderxt88}, @samp{thunderxt88p1}, @samp{thunderxt81}, @samp{thunderxt83}, @samp{thunderx2t99}, @samp{cortex-a57.cortex-a53},