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[209.132.180.131]) by mx.google.com with ESMTPS id b59si5270197plc.205.2016.11.23.05.35.09 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 23 Nov 2016 05:35:09 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-442370-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-442370-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-442370-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=Agbgh4/oTW8PSDbd jsHnOAH4N16pJvF2ajNY/xneelb5MloaFBqr9XFGsqgRTUhAhEolOsOzxMgL9DmL 1FlQIPNFx+W/VjaUvOKpEziBgXdV5hfttBGOto2n8sBNME4eAAMsbRXX6fGF4FR9 rP1WwIWkJEn8zQnqagYoo3bRv0s= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=7v2Q6JaDGmbpz9TedrnJh1 xRpl0=; b=mQkTkQYQ4jn3WO9HDC81+ynG3jgqs5tffYicW5QRVb1GNIBcJQXGEl yQ0JcHl8JzgX4JS4b27NEl8WYNOQfpdq7u0ZeqHWI2o/Ffj54jWuEH/JpJ5IvFb/ ryWlsKuSkCoQ+hpfwqti/Oyq741k2THmxHSExzKP4XuO3rko99k/s= Received: (qmail 110383 invoked by alias); 23 Nov 2016 13:34:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 110372 invoked by uid 89); 23 Nov 2016 13:34:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.2 spammy=242632, sk:ebotcaz, U*ebotcazou, D*adacore.com X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 23 Nov 2016 13:34:45 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id E337F81358 for ; Wed, 23 Nov 2016 14:34:42 +0100 (CET) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id Ge9qL8R93YeN for ; Wed, 23 Nov 2016 14:34:42 +0100 (CET) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id BA58781357 for ; Wed, 23 Nov 2016 14:34:42 +0100 (CET) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Small tweaks to 32-bit shift patterns in 64-bit mode Date: Wed, 23 Nov 2016 14:34:42 +0100 Message-ID: <2237864.ktGgssC3JR@polaris> User-Agent: KMail/4.14.10 (Linux/3.16.7-48-desktop; KDE/4.14.9; x86_64; ; ) MIME-Version: 1.0 For example, a couple of them were rejecting constant integers, leading to suboptimal code before function returns in some cases. Tested on SPARC/Solaris, applied on the mainline. 2016-11-23 Eric Botcazou * config/sparc/sparc.md (*ashrsi3_extend): Rename to... (*ashrsi3_extend0): ...this. Accept constant integers. (*ashrsi3_extend2): Rename to... (*ashrsi3_extend1): ...this. (*ashrsi3_extend2): New pattern. (*lshrsi3_extend1): Accept constant integers. (*lshrsi3_extend2): Fix condition on operand 2. -- Eric Botcazou Index: config/sparc/sparc.md =================================================================== --- config/sparc/sparc.md (revision 242632) +++ config/sparc/sparc.md (working copy) @@ -6508,17 +6508,22 @@ (define_insn "ashrsi3" } [(set_attr "type" "shift")]) -(define_insn "*ashrsi3_extend" +(define_insn "*ashrsi3_extend0" [(set (match_operand:DI 0 "register_operand" "=r") (sign_extend:DI (ashiftrt:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith_operand" "r"))))] + (match_operand:SI 2 "arith_operand" "rI"))))] "TARGET_ARCH64" - "sra\t%1, %2, %0" +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + return "sra\t%1, %2, %0"; +} [(set_attr "type" "shift")]) -;; This handles the case as above, but with constant shift instead of -;; register. Combiner "simplifies" it for us a little bit though. -(define_insn "*ashrsi3_extend2" +;; This handles the case where +;; (sign_extend:DI (ashiftrt:SI (match_operand:SI) (match_operand:SI))) +;; but combiner "simplifies" it for us. +(define_insn "*ashrsi3_extend1" [(set (match_operand:DI 0 "register_operand" "=r") (ashiftrt:DI (ashift:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0) (const_int 32)) @@ -6530,6 +6535,21 @@ (define_insn "*ashrsi3_extend2" } [(set_attr "type" "shift")]) +;; This handles the case where +;; (ashiftrt:DI (sign_extend:DI (match_operand:SI)) (const_int)) +;; but combiner "simplifies" it for us. +(define_insn "*ashrsi3_extend2" + [(set (match_operand:DI 0 "register_operand" "=r") + (sign_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0) + (match_operand 2 "small_int_operand" "I") + (const_int 32)))] + "TARGET_ARCH64 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 32" +{ + operands[2] = GEN_INT (32 - INTVAL (operands[2])); + return "sra\t%1, %2, %0"; +} + [(set_attr "type" "shift")]) + (define_expand "ashrdi3" [(set (match_operand:DI 0 "register_operand" "=r") (ashiftrt:DI (match_operand:DI 1 "register_operand" "r") @@ -6595,26 +6615,30 @@ (define_insn "*lshrsi3_extend0" [(set_attr "type" "shift")]) ;; This handles the case where -;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))), +;; (zero_extend:DI (lshiftrt:SI (match_operand:SI) (match_operand:SI))) ;; but combiner "simplifies" it for us. (define_insn "*lshrsi3_extend1" [(set (match_operand:DI 0 "register_operand" "=r") (and:DI (subreg:DI (lshiftrt:SI (match_operand:SI 1 "register_operand" "r") - (match_operand:SI 2 "arith_operand" "r")) 0) + (match_operand:SI 2 "arith_operand" "rI")) 0) (match_operand 3 "const_int_operand" "")))] "TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[3]) == 0xffffffff" - "srl\t%1, %2, %0" +{ + if (GET_CODE (operands[2]) == CONST_INT) + operands[2] = GEN_INT (INTVAL (operands[2]) & 0x1f); + return "srl\t%1, %2, %0"; +} [(set_attr "type" "shift")]) ;; This handles the case where -;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int >=0 < 32)) +;; (lshiftrt:DI (zero_extend:DI (match_operand:SI)) (const_int)) ;; but combiner "simplifies" it for us. (define_insn "*lshrsi3_extend2" [(set (match_operand:DI 0 "register_operand" "=r") (zero_extract:DI (subreg:DI (match_operand:SI 1 "register_operand" "r") 0) (match_operand 2 "small_int_operand" "I") (const_int 32)))] - "TARGET_ARCH64 && (unsigned HOST_WIDE_INT) INTVAL (operands[2]) < 32" + "TARGET_ARCH64 && INTVAL (operands[2]) > 0 && INTVAL (operands[2]) <= 32" { operands[2] = GEN_INT (32 - INTVAL (operands[2])); return "srl\t%1, %2, %0";