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[209.132.180.131]) by mx.google.com with ESMTPS id 36si42558161plc.213.2016.12.11.23.57.59 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sun, 11 Dec 2016 23:57:59 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-444122-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-444122-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-444122-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=UwLg07C6Xii94uUL Ljr/l+x5//Hxa2tfhysD1ECtG2V1i+dNcbRzyejc+lf5PLDOsIU3j0Vimt0I4Vn7 lT21uk0RPuMa5ztC38WwoMiGGWTOw/DiKpcP8wOvZg2+Y8UZUQZxj042YpoX7d/x s8E5dju8RpQbstu1VycQlWoF/ZY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type :content-transfer-encoding; s=default; bh=sq2xxJvZV5OH1PHq0zW3Rl xerH4=; b=mSjSkkLzEc1eEY0SlKXHYxmiSDQ8UwKYzOMRMZTjqawRwJS6X2N4vJ xObQ1F8Iy/KQQWNGncooZeFQknEcstfnQpGwrADlWpIJz4dHOgqel0uzbKeMOHZI 8JDgOJBBDE5FRLHAQPG2BgVRoF/NDiG0p6djGdRfMNZDqLdn+mYUM= Received: (qmail 6134 invoked by alias); 12 Dec 2016 07:57:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 6112 invoked by uid 89); 12 Dec 2016 07:57:39 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, KAM_ASCII_DIVIDERS, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=no version=3.3.2 spammy=SPARC, U*ebotcazou, sk:ebotcaz, 12811 X-HELO: smtp.eu.adacore.com Received: from mel.act-europe.fr (HELO smtp.eu.adacore.com) (194.98.77.210) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 12 Dec 2016 07:57:29 +0000 Received: from localhost (localhost [127.0.0.1]) by filtered-smtp.eu.adacore.com (Postfix) with ESMTP id 30B04814D1 for ; Mon, 12 Dec 2016 08:57:27 +0100 (CET) Received: from smtp.eu.adacore.com ([127.0.0.1]) by localhost (smtp.eu.adacore.com [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id ZnBwDRBiQ7q3 for ; Mon, 12 Dec 2016 08:57:27 +0100 (CET) Received: from polaris.localnet (bon31-6-88-161-99-133.fbx.proxad.net [88.161.99.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.eu.adacore.com (Postfix) with ESMTPSA id 071A4812EE for ; Mon, 12 Dec 2016 08:57:26 +0100 (CET) From: Eric Botcazou To: gcc-patches@gcc.gnu.org Subject: [SPARC] Adjust T constraint Date: Mon, 12 Dec 2016 08:57:26 +0100 Message-ID: <2395674.fsfTfpvWjH@polaris> User-Agent: KMail/4.14.10 (Linux/3.16.7-53-desktop; KDE/4.14.9; x86_64; ; ) MIME-Version: 1.0 The main purpose of the T constraint is to make sure that a memory reference is aligned on a 64-bit boundary in 32-bit mode. But define_memory_constraint is not appropriate for such a constraint, because reload may think that it can satisfy it by reloading the address, which is of course wrong; this apparently never happens with old reload, but does with LRA and is responsible for the last couple of regressions in the testsuite in 32-bit mode. Tested on SPARC/Solaris w/ and w/o -mlra, applied on the mainline. 2016-12-12 Eric Botcazou * config/sparc/constraints.md (T): Use special memory constraint. (U): Minor tweak. (W): Add TARGET_ARCH64 test. * config/sparc/sparc.md (*movdi_insn_sp32): Replace 'W' with 'T'. (*movdf_insn_sp32): Likewise. (*mov_insn_sp32): Likewise. Replace 'e' with 'f' in conjunction with offsettable memory references. -- Eric Botcazou Index: config/sparc/constraints.md =================================================================== --- config/sparc/constraints.md (revision 243513) +++ config/sparc/constraints.md (working copy) @@ -128,11 +128,11 @@ (define_constraint "S" (and (match_code "const_double") (match_test "fp_high_losum_p (op)"))) -;; Not needed in 64-bit mode -(define_memory_constraint "T" +;; We need a special memory constraint because of the alignment requirement +(define_special_memory_constraint "T" "Memory reference whose address is aligned to 8-byte boundary" - (and (match_test "TARGET_ARCH32") - (match_code "mem") + (and (match_code "mem") + (match_test "TARGET_ARCH32") (match_test "memory_ok_for_ldd (op)"))) ;; This awkward register constraint is necessary because it is not @@ -174,16 +174,17 @@ (define_memory_constraint "T" ;; reg_class_for_constraint, and checks it against NO_REGS. (define_constraint "U" "Pseudo-register or hard even-numbered integer register" - (and (match_test "TARGET_ARCH32") - (match_code "reg") + (and (match_code "reg") (ior (match_test "REGNO (op) < FIRST_PSEUDO_REGISTER") (not (match_test "reload_in_progress && reg_renumber [REGNO (op)] < 0"))) + (match_test "TARGET_ARCH32") (match_test "register_ok_for_ldd (op)"))) -;; Equivalent to 'T' but available in 64-bit mode +;; Equivalent to 'T' but in 64-bit mode without alignment requirement (define_memory_constraint "W" "Memory reference for 'e' constraint floating-point register" (and (match_code "mem") + (match_test "TARGET_ARCH64") (match_test "memory_ok_for_ldd (op)"))) (define_memory_constraint "w" Index: config/sparc/sparc.md =================================================================== --- config/sparc/sparc.md (revision 243513) +++ config/sparc/sparc.md (working copy) @@ -1705,9 +1705,9 @@ (define_expand "movdi" (define_insn "*movdi_insn_sp32" [(set (match_operand:DI 0 "nonimmediate_operand" - "=T,o,U,T,r,o,r,r,?*f,?T,?*f,?o,?*e,?*e, r,?*f,?*e,?W,*b,*b") + "=T,o,U,T,r,o,r,r,?*f,?T,?*f,?o,?*e,?*e, r,?*f,?*e,?T,*b,*b") (match_operand:DI 1 "input_operand" - " J,J,T,U,o,r,i,r, T,*f, o,*f, *e, *e,?*f, r, W,*e, J, P"))] + " J,J,T,U,o,r,i,r, T,*f, o,*f, *e, *e,?*f, r, T,*e, J, P"))] "TARGET_ARCH32 && (register_operand (operands[0], DImode) || register_or_zero_operand (operands[1], DImode))" @@ -2336,9 +2336,9 @@ (define_expand "movdf" (define_insn "*movdf_insn_sp32" [(set (match_operand:DF 0 "nonimmediate_operand" - "=T,o,b,b,e,e,*r, f, e,W,U,T, f,o, *r,*r, o") + "=T,o,b,b,e,e,*r, f, e,T,U,T, f,o, *r,*r, o") (match_operand:DF 1 "input_operand" - " G,G,G,C,e,e, f,*r,W#F,e,T,U,o#F,f,*rF, o,*r"))] + " G,G,G,C,e,e, f,*r,T#F,e,T,U,o#F,f,*rF, o,*r"))] "TARGET_ARCH32 && (register_operand (operands[0], DFmode) || register_or_zero_or_all_ones_operand (operands[1], DFmode))" @@ -8543,9 +8543,9 @@ (define_insn "*mov_insn_sp64" (define_insn "*mov_insn_sp32" [(set (match_operand:VM64 0 "nonimmediate_operand" - "=T,o,e,e,e,*r, f,e,W,U,T,e,o,*r,*r, o") + "=T,o,e,e,e,*r, f,e,T,U,T,f,o,*r,*r, o") (match_operand:VM64 1 "input_operand" - " Y,Y,Y,Z,e, f,*r,W,e,T,U,o,e,*r, o,*r"))] + " Y,Y,Y,Z,e, f,*r,T,e,T,U,o,f,*r, o,*r"))] "TARGET_VIS && TARGET_ARCH32 && (register_operand (operands[0], mode)