From patchwork Wed Feb 29 14:48:05 2012 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Stubbs X-Patchwork-Id: 7006 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id 747EC23E4A for ; Wed, 29 Feb 2012 14:48:13 +0000 (UTC) Received: from mail-iy0-f180.google.com (mail-iy0-f180.google.com [209.85.210.180]) by fiordland.canonical.com (Postfix) with ESMTP id 384ECA18155 for ; Wed, 29 Feb 2012 14:48:13 +0000 (UTC) Received: by iage36 with SMTP id e36so3379795iag.11 for ; Wed, 29 Feb 2012 06:48:12 -0800 (PST) Received: from mr.google.com ([10.50.89.201]) by 10.50.89.201 with SMTP id bq9mr542133igb.55.1330526892748 (num_hops = 1); Wed, 29 Feb 2012 06:48:12 -0800 (PST) Received: by 10.50.89.201 with SMTP id bq9mr454296igb.55.1330526892705; Wed, 29 Feb 2012 06:48:12 -0800 (PST) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.231.53.18 with SMTP id k18csp4645ibg; Wed, 29 Feb 2012 06:48:12 -0800 (PST) Received: by 10.68.129.166 with SMTP id nx6mr6199816pbb.153.1330526892073; Wed, 29 Feb 2012 06:48:12 -0800 (PST) Received: from relay1.mentorg.com (relay1.mentorg.com. [192.94.38.131]) by mx.google.com with ESMTPS id h4si26637420pbk.227.2012.02.29.06.48.11 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 29 Feb 2012 06:48:12 -0800 (PST) Received-SPF: neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) client-ip=192.94.38.131; Authentication-Results: mx.google.com; spf=neutral (google.com: 192.94.38.131 is neither permitted nor denied by best guess record for domain of Andrew_Stubbs@mentor.com) smtp.mail=Andrew_Stubbs@mentor.com Received: from svr-orw-fem-01.mgc.mentorg.com ([147.34.98.93]) by relay1.mentorg.com with esmtp id 1S2kp9-0004zV-0Z from Andrew_Stubbs@mentor.com ; Wed, 29 Feb 2012 06:48:11 -0800 Received: from SVR-IES-FEM-01.mgc.mentorg.com ([137.202.0.104]) by svr-orw-fem-01.mgc.mentorg.com over TLS secured channel with Microsoft SMTPSVC(6.0.3790.4675); Wed, 29 Feb 2012 06:48:10 -0800 Received: from [172.30.13.193] (137.202.0.76) by SVR-IES-FEM-01.mgc.mentorg.com (137.202.0.104) with Microsoft SMTP Server id 14.1.289.1; Wed, 29 Feb 2012 14:48:08 +0000 Message-ID: <4F4E3AA5.1070804@codesourcery.com> Date: Wed, 29 Feb 2012 14:48:05 +0000 From: Andrew Stubbs User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:10.0.2) Gecko/20120216 Thunderbird/10.0.2 MIME-Version: 1.0 To: "gcc-patches@gcc.gnu.org" CC: "patches@linaro.org" Subject: [PATCH][ARM] NEON DImode not X-OriginalArrivalTime: 29 Feb 2012 14:48:10.0556 (UTC) FILETIME=[280047C0:01CCF6F1] X-Gm-Message-State: ALoCoQkmDrWlqF2atVdHExoz2PZZlMGLzJfDGj8gbVyCuOguBd6hHcRY5/kVFg4pvuxnuvbo3SBs Hi all, This patch adds support for the DImode not operation in NEON. Currently the compiler must move the value to core registers, invert it there, and move it back again. This is bonkers because the VMVN instruction will do the job perfectly. The patch adds a pattern to support VMVN in DImode (in addition to the vector modes already supported) and retains the support for doing bitwise not in core registers where appropriate. OK for 4.8? Andrew 2012-02-29 Andrew Stubbs gcc/ * config/arm/arm.md (one_cmpldi2): Rename to one_cmpldi2_internal and replace with a new define_expand. (one_cmpldi2_internal): Exclude splitting for VFP registers. * config/arm/neon.md (one_cmpldi2_neon): New pattern. --- gcc/config/arm/arm.md | 13 ++++++++++--- gcc/config/arm/neon.md | 14 ++++++++++++++ 2 files changed, 24 insertions(+), 3 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 751997f..93fde58 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -4206,12 +4206,19 @@ "TARGET_32BIT && TARGET_HARD_FLOAT && (TARGET_FPA || TARGET_VFP_DOUBLE)" "") -(define_insn_and_split "one_cmpldi2" +(define_expand "one_cmpldi2" + [(set (match_operand:DI 0 "s_register_operand" "") + (not:DI (match_operand:DI 1 "s_register_operand" "")))] + "TARGET_32BIT" + "") + +(define_insn_and_split "*one_cmpldi2_internal" [(set (match_operand:DI 0 "s_register_operand" "=&r,&r") (not:DI (match_operand:DI 1 "s_register_operand" "0,r")))] - "TARGET_32BIT" + "TARGET_32BIT && !TARGET_NEON" "#" - "TARGET_32BIT && reload_completed" + "TARGET_32BIT && reload_completed + && arm_general_register_operand (operands[0], DImode)" [(set (match_dup 0) (not:SI (match_dup 1))) (set (match_dup 2) (not:SI (match_dup 3)))] " diff --git a/gcc/config/arm/neon.md b/gcc/config/arm/neon.md index d7caa37..f34d266 100644 --- a/gcc/config/arm/neon.md +++ b/gcc/config/arm/neon.md @@ -896,6 +896,20 @@ [(set_attr "neon_type" "neon_int_1")] ) +(define_insn "*one_cmpldi2_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w,?&r,?&r,?w") + (not:DI (match_operand:DI 1 "s_register_operand" " w, 0, r, w")))] + "TARGET_NEON" + "@ + vmvn\t%P0, %P1 + # + # + vmvn\t%P0, %P1" + [(set_attr "neon_type" "neon_int_1,*,*,neon_int_1") + (set_attr "arch" "nota8,*,*,onlya8") + (set_attr "length" "*,8,8,*")] +) + (define_insn "abs2" [(set (match_operand:VDQW 0 "s_register_operand" "=w") (abs:VDQW (match_operand:VDQW 1 "s_register_operand" "w")))]