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[58.6.183.210]) by smtp.googlemail.com with ESMTPSA id sn9sm12751481pac.16.2015.10.05.18.40.28 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Oct 2015 18:40:31 -0700 (PDT) Subject: Re: [AARCH64] Add missing entries in iterator vwcore To: James Greenhalgh References: <560D9A70.60404@linaro.org> <20151005103322.GA17689@arm.com> Cc: "gcc-patches@gcc.gnu.org" , Marcus Shawcroft From: Kugan Message-ID: <5613268A.6010201@linaro.org> Date: Tue, 6 Oct 2015 12:40:26 +1100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.3.0 MIME-Version: 1.0 In-Reply-To: <20151005103322.GA17689@arm.com> X-IsSubscribed: yes X-Original-Sender: kugan.vivekanandarajah@linaro.org X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c03::236 as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 On 05/10/15 21:33, James Greenhalgh wrote: > On Thu, Oct 01, 2015 at 09:41:20PM +0100, Kugan wrote: >> Hi, >> >> In "aarch64_get_lane" operand 0 is VEL, so for %0, >> iterator vwcore should (?) support all the modes in VEL. >> >> Ran into following error with a local patch for an existing test case. >> However it can also be reproduced with the attached test case. >> >> fnction ???fn1???: >> t.c:25:1: internal compiler error: output_operand: invalid %-code >> } >> ^ >> 0x8198fb output_operand_lossage(char const*, ...) >> ../../base/gcc/final.c:3417 >> 0x81a45b output_asm_insn(char const*, rtx_def**) >> ../../base/gcc/final.c:3782 >> 0x81b9d3 output_asm_insn(char const*, rtx_def**) >> ../../base/gcc/final.c:2364 >> 0x81b9d3 final_scan_insn(rtx_insn*, _IO_FILE*, int, int, int*) >> ../../base/gcc/final.c:3029 >> 0x81be2b final(rtx_insn*, _IO_FILE*, int) >> ../../base/gcc/final.c:2058 >> 0x81c6e7 rest_of_handle_final >> ../../base/gcc/final.c:4449 >> 0x81c6e7 execute >> ../../base/gcc/final.c:4524 >> >> >> Attached patch fixes this. Bootstrapped and regression tested for >> aarch64-none-linux-gnu with no new regression. Is this OK for trunk? >> >> gcc/ChangeLog: >> >> 2015-10-02 Kugan Vivekanandarajah >> >> * config/aarch64/iterators.md: Add missing core element mode for >> mode. >> >> gcc/testsuite/ChangeLog: >> >> 2015-10-02 Kugan Vivekanandarajah >> >> * gcc.target/aarch64/foo.c: New test. >> > > "foo.c" is not OK, please give this testcase a meaningful name. > >> diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md >> index 38c5a24..e49abd5 100644 >> --- a/gcc/config/aarch64/iterators.md >> +++ b/gcc/config/aarch64/iterators.md >> @@ -537,8 +537,11 @@ >> (V4HI "w") (V8HI "w") >> (V2SI "w") (V4SI "w") >> (DI "x") (V2DI "x") >> + (V4HF "w") (V8HF "w") >> (V2SF "w") (V4SF "w") >> - (V2DF "x")]) >> + (V2DF "x") (SI "x") >> + (HI "x") (QI "x")]) > > I don't understand the reasoning here, Surely we want "w" for SI,HI,QI > modes? Though are you sure we need them to fix your bug? I'd have expected > the hunk for V4HF and V8HF to be enough. Yes, the hunk for V4HF and V8HF is enough and that is what I started with. Then I was thinking maybe we should cover all the modes in VEL. Please find the attached that has just V4HF and V8HF. > >> >> ;; Double vector types for ALLX. >> (define_mode_attr Vallxd [(QI "8b") (HI "4h") (SI "2s")]) >> diff --git a/gcc/testsuite/gcc.target/aarch64/foo.c b/gcc/testsuite/gcc.target/aarch64/foo.c >> index e69de29..77f161e 100644 >> --- a/gcc/testsuite/gcc.target/aarch64/foo.c >> +++ b/gcc/testsuite/gcc.target/aarch64/foo.c > > Again, please give this test a meaningful name. Renamed the test case. Is this OK now? Thanks, Kugan gcc/ChangeLog: 2015-10-06 Kugan Vivekanandarajah * config/aarch64/iterators.md: Add missing core element mode for mode. gcc/testsuite/ChangeLog: 2015-10-06 Kugan Vivekanandarajah * gcc.target/aarch64/vcore_ice_test.c: New test. > > Thanks, > James > >> @@ -0,0 +1,25 @@ >> + >> +/* { dg-do compile } */ >> +/* { dg-options "-O3" } */ >> + >> +void fn2 (); >> + >> +typedef __Float16x4_t float16x4_t; >> +__fp16 result_float16x4[1]; >> +float16x4_t exec_vst1_lane_vector_float16x4, exec_vst1_lane___trans_tmp_1; >> + >> +void fn1 () >> +{ >> + exec_vst1_lane_vector_float16x4 = exec_vst1_lane___trans_tmp_1; >> + __fp16 *__a = result_float16x4; >> + float16x4_t __b = exec_vst1_lane___trans_tmp_1; >> + int __lane = 0; >> + *__a = ({ __b[__lane]; }); >> + union { >> + short i; >> + __fp16 f; >> + } tmp_res; >> + tmp_res.f = result_float16x4[0]; >> + if (tmp_res.i) >> + fn2(); >> +} > diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index 38c5a24..90e8533 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -537,6 +537,7 @@ (V4HI "w") (V8HI "w") (V2SI "w") (V4SI "w") (DI "x") (V2DI "x") + (V4HF "w") (V8HF "w") (V2SF "w") (V4SF "w") (V2DF "x")]) diff --git a/gcc/testsuite/gcc.target/aarch64/vcore_ice_test.c b/gcc/testsuite/gcc.target/aarch64/vcore_ice_test.c index e69de29..77f161e 100644 --- a/gcc/testsuite/gcc.target/aarch64/vcore_ice_test.c +++ b/gcc/testsuite/gcc.target/aarch64/vcore_ice_test.c @@ -0,0 +1,25 @@ + +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +void fn2 (); + +typedef __Float16x4_t float16x4_t; +__fp16 result_float16x4[1]; +float16x4_t exec_vst1_lane_vector_float16x4, exec_vst1_lane___trans_tmp_1; + +void fn1 () +{ + exec_vst1_lane_vector_float16x4 = exec_vst1_lane___trans_tmp_1; + __fp16 *__a = result_float16x4; + float16x4_t __b = exec_vst1_lane___trans_tmp_1; + int __lane = 0; + *__a = ({ __b[__lane]; }); + union { + short i; + __fp16 f; + } tmp_res; + tmp_res.f = result_float16x4[0]; + if (tmp_res.i) + fn2(); +}