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[209.132.180.131]) by mx.google.com with ESMTPS id ut11si12951521pab.37.2015.10.14.05.24.44 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 14 Oct 2015 05:24:44 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-410130-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 111521 invoked by alias); 14 Oct 2015 12:24:33 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 111508 invoked by uid 89); 14 Oct 2015 12:24:32 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Oct 2015 12:24:31 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-29-ff8BDiCzSti_N7USgUXqAA-1; Wed, 14 Oct 2015 13:24:26 +0100 Received: from [10.2.207.50] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 14 Oct 2015 13:24:26 +0100 Message-ID: <561E497A.3080506@arm.com> Date: Wed, 14 Oct 2015 13:24:26 +0100 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Ramana Radhakrishnan , Richard Earnshaw Subject: [PATCH][ARM][4.9/5 Backport] PR target/67929 Tighten vfp3_const_double_for_bits checks X-MC-Unique: ff8BDiCzSti_N7USgUXqAA-1 X-IsSubscribed: yes X-Original-Sender: kyrylo.tkachov@arm.com X-Original-Authentication-Results: mx.google.com; spf=pass (google.com: domain of patch+caf_=patchwork-forward=linaro.org@linaro.org designates 2a00:1450:4010:c04::22e as permitted sender) smtp.mailfrom=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi all, This is the 4.9 and GCC 5 version of the patch I posted earlier to fix the referenced PR. Bootstrapped and tested arm-none-linux-gnueabihf on those branches. Ok for the branches? Thanks, Kyrill 2015-10-12 Kyrylo Tkachov PR target/67929 * config/arm/arm.c (vfp3_const_double_for_bits): Rewrite. * config/arm/constraints.md (Dp): Update callsite. * config/arm/predicates.md (const_double_vcvt_power_of_two): Likewise. 2015-10-12 Kyrylo Tkachov PR target/67929 * gcc.target/arm/pr67929_1.c: New test. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index d87eca1..abf2dbb 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -27544,25 +27544,36 @@ vfp3_const_double_for_fract_bits (rtx operand) return 0; } +/* If X is a CONST_DOUBLE with a value that is a power of 2 whose + log2 is in [1, 32], return that log2. Otherwise return -1. + This is used in the patterns for vcvt.s32.f32 floating-point to + fixed-point conversions. */ + int -vfp3_const_double_for_bits (rtx operand) +vfp3_const_double_for_bits (rtx x) { - REAL_VALUE_TYPE r0; + if (!CONST_DOUBLE_P (x)) + return -1; - if (!CONST_DOUBLE_P (operand)) - return 0; + REAL_VALUE_TYPE r; - REAL_VALUE_FROM_CONST_DOUBLE (r0, operand); - if (exact_real_truncate (DFmode, &r0)) - { - HOST_WIDE_INT value = real_to_integer (&r0); - value = value & 0xffffffff; - if ((value != 0) && ( (value & (value - 1)) == 0)) - return int_log2 (value); - } + REAL_VALUE_FROM_CONST_DOUBLE (r, x); + if (REAL_VALUE_NEGATIVE (r) + || REAL_VALUE_ISNAN (r) + || REAL_VALUE_ISINF (r) + || !real_isinteger (&r, SFmode)) + return -1; - return 0; + HOST_WIDE_INT hwint = exact_log2 (real_to_integer (&r)); + + /* The exact_log2 above will have returned -1 if this is + not an exact log2. */ + if (!IN_RANGE (hwint, 1, 32)) + return -1; + + return hwint; } + /* Emit a memory barrier around an atomic sequence according to MODEL. */ diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index f9e11e0..d7d0826 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -339,7 +339,8 @@ "@internal In ARM/ Thumb2 a const_double which can be used with a vcvt.s32.f32 with bits operation" (and (match_code "const_double") - (match_test "TARGET_32BIT && TARGET_VFP && vfp3_const_double_for_bits (op)"))) + (match_test "TARGET_32BIT && TARGET_VFP + && vfp3_const_double_for_bits (op) > 0"))) (define_register_constraint "Ts" "(arm_restrict_it) ? LO_REGS : GENERAL_REGS" "For arm_restrict_it the core registers @code{r0}-@code{r7}. GENERAL_REGS otherwise.") diff --git a/gcc/config/arm/predicates.md b/gcc/config/arm/predicates.md index 08cc899..48e4ba8 100644 --- a/gcc/config/arm/predicates.md +++ b/gcc/config/arm/predicates.md @@ -668,7 +668,7 @@ (define_predicate "const_double_vcvt_power_of_two" (and (match_code "const_double") (match_test "TARGET_32BIT && TARGET_VFP - && vfp3_const_double_for_bits (op)"))) + && vfp3_const_double_for_bits (op) > 0"))) (define_predicate "neon_struct_operand" (and (match_code "mem") diff --git a/gcc/testsuite/gcc.target/arm/pr67929_1.c b/gcc/testsuite/gcc.target/arm/pr67929_1.c new file mode 100644 index 0000000..14943b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/pr67929_1.c @@ -0,0 +1,21 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_vfp3_ok } */ +/* { dg-options "-O2 -fno-inline" } */ +/* { dg-add-options arm_vfp3 } */ +/* { dg-skip-if "need fp instructions" { *-*-* } { "-mfloat-abi=soft" } { "" } } */ + +int +foo (float a) +{ + return a * 4.9f; +} + + +int +main (void) +{ + if (foo (10.0f) != 49) + __builtin_abort (); + + return 0; +} \ No newline at end of file