From patchwork Tue Nov 10 09:27:11 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrylo Tkachov X-Patchwork-Id: 56292 Delivered-To: patch@linaro.org Received: by 10.112.155.196 with SMTP id vy4csp659359lbb; Tue, 10 Nov 2015 01:27:33 -0800 (PST) X-Received: by 10.68.102.33 with SMTP id fl1mr4098935pbb.40.1447147653538; Tue, 10 Nov 2015 01:27:33 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id se6si4044931pbc.7.2015.11.10.01.27.33 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 10 Nov 2015 01:27:33 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-413445-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-return-413445-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-413445-patch=linaro.org@gcc.gnu.org; dkim=pass header.i=@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; q=dns; s=default; b=lBmVH624y4FMvNF8SN8wxFf+lwUUwQH6oh5UOx0eI61 hKhJ7LPl7SaWhdQFLOGsJ99qNGzwe2rTNn2h5pIN+F05afDkR5gIpJwYqNqF9luc FIsybEu2gQxke9SbciRiB1WRShN8rd6tW/68xq2+IpctNv2f/uf98Bwe8zy5HIqs = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:cc:subject:content-type; s=default; bh=PH0g2K2GnhTJmdm8uryE5mELu/s=; b=RVMIMW/QoG4eGVCsB NBjJ/9vYipmNZsQknS0lVSlG65OFeEvpsF2e9uMrTIt9DQdhHi4oifjwGsd63EhD jI45MdFy9tX4/2F8CYWG0eYt6R1VztUM9m0B5piKXyutj+F+Ec3G/v3mBkphah3x lMC9g1UB7vwowB1viVd4fSBCRo= Received: (qmail 97360 invoked by alias); 10 Nov 2015 09:27:20 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 96203 invoked by uid 89); 10 Nov 2015 09:27:18 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.7 required=5.0 tests=AWL, BAYES_00, SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (146.101.78.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 10 Nov 2015 09:27:16 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by eu-smtp-1.mimecast.com with ESMTP id uk-mta-5-KJAs-dGlRfq4YBj_CxnjJw-1; Tue, 10 Nov 2015 09:27:11 +0000 Received: from [10.2.206.200] ([10.1.2.79]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 10 Nov 2015 09:27:11 +0000 Message-ID: <5641B86F.1040202@arm.com> Date: Tue, 10 Nov 2015 09:27:11 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches CC: Ramana Radhakrishnan , Richard Earnshaw Subject: [PATCH][ARM][3/3][v2] Implement negsicc, notsicc optabs X-MC-Unique: KJAs-dGlRfq4YBj_CxnjJw-1 X-IsSubscribed: yes Hi all, This is a slight respin of https://gcc.gnu.org/ml/gcc-patches/2015-09/msg00075.html. This had been ok'd but I've encountered a bug with the *if__move pattern For some reason, after reload operands[1] doesn't end up living in the same register as operands[0] even though it has the constraint '0'. Maybe I misunderstood the semantics of the '0' constraints. In any case, telling the splitter to explicitly emit the move before the cond_exec if the registers don't match fixes this. Bootstrapped and tested on arm. Ok to commit this updated version instead? Thanks, Kyrill 2015-11-10 Kyrylo Tkachov * config/arm/arm.md (sicc): New define_expand. (*if_neg_move): Rename to... (*if__move): ... This. Use NOT_NEG code iterator. Move operands[1] into operands[0] if they don't match up. * config/arm/iterators.md (NOT_NEG): New code iterator. (NOT_NEG_op): New code attribute. 2015-11-10 Kyrylo Tkachov * gcc.target/arm/cond_op_imm_1.c: New test. commit c5a3ade022a18dad02d3391aab7af9ddf7e26340 Author: Kyrylo Tkachov Date: Fri Aug 14 13:42:51 2015 +0100 [ARM][3/3] Implement negsicc, notsicc optabs diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 8ebb1bf..ab7ece9 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -10079,19 +10079,43 @@ (define_insn "*ifcompare_neg_move" (set_attr "type" "multiple")] ) -(define_insn_and_split "*if_neg_move" +;; The negsicc and notsicc optabs. +(define_expand "sicc" + [(set (match_operand:SI 0 "s_register_operand" "") + (if_then_else:SI (match_operand 1 "arm_comparison_operator" "") + (NOT_NEG:SI (match_operand:SI 2 "s_register_operand" "")) + (match_operand:SI 3 "s_register_operand" "")))] + "TARGET_32BIT" + { + rtx ccreg; + enum rtx_code code = GET_CODE (operands[1]); + + if (code == UNEQ || code == LTGT) + FAIL; + + ccreg = arm_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1), NULL); + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + } +) + + +(define_insn_and_split "*if__move" [(set (match_operand:SI 0 "s_register_operand" "=l,r") (if_then_else:SI (match_operator 4 "arm_comparison_operator" [(match_operand 3 "cc_register" "") (const_int 0)]) - (neg:SI (match_operand:SI 2 "s_register_operand" "l,r")) + (NOT_NEG:SI (match_operand:SI 2 "s_register_operand" "l,r")) (match_operand:SI 1 "s_register_operand" "0,0")))] "TARGET_32BIT" "#" "&& reload_completed" [(cond_exec (match_op_dup 4 [(match_dup 3) (const_int 0)]) - (set (match_dup 0) (neg:SI (match_dup 2))))] - "" + (set (match_dup 0) (NOT_NEG:SI (match_dup 2))))] + { + if (!rtx_equal_p (operands[0], operands[1])) + emit_move_insn (operands[0], operands[1]); + } [(set_attr "conds" "use") (set_attr "length" "4") (set_attr "arch" "t2,32") diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 6a54125..2f4bc5c 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -209,6 +209,9 @@ (define_code_iterator COMPARISONS [eq gt ge le lt]) ;; A list of ... (define_code_iterator IOR_XOR [ior xor]) +;; Bitwise complement and negation +(define_code_iterator NOT_NEG [not neg]) + ;; Operations on two halves of a quadword vector. (define_code_iterator VQH_OPS [plus smin smax umin umax]) @@ -656,6 +659,8 @@ (define_code_attr VQH_type [(plus "add") (smin "minmax") (smax "minmax") (define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") (umax "u")]) +(define_code_attr NOT_NEG_op [(not "not") (neg "neg")]) + (define_code_attr cnb [(ltu "CC_C") (geu "CC")]) (define_code_attr optab [(ltu "ltu") (geu "geu")]) diff --git a/gcc/testsuite/gcc.target/arm/cond_op_imm_1.c b/gcc/testsuite/gcc.target/arm/cond_op_imm_1.c new file mode 100644 index 0000000..9d335e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/cond_op_imm_1.c @@ -0,0 +1,42 @@ +/* { dg-do run } */ +/* { dg-options "-save-temps -O2 -fno-inline" } */ +/* { dg-require-effective-target arm_cond_exec } */ + +extern void abort (void); + +#define N 25089992 + +int +foonegsi (int a) +{ + return a ? N : -N; +} + +int +fooinvsi (int a) +{ + return a ? N : ~N; +} + + + +int +main (void) +{ + if (foonegsi (1) != N) + abort (); + + if (foonegsi (0) != -N) + abort (); + + if (fooinvsi (1) != N) + abort (); + + if (fooinvsi (0) != ~N) + abort (); + + return 0; +} + +/* { dg-final { scan-assembler "rsbne" } } */ +/* { dg-final { scan-assembler "mvnne" } } */