From patchwork Tue Dec 6 16:53:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 86873 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp2116059qgi; Tue, 6 Dec 2016 08:53:49 -0800 (PST) X-Received: by 10.99.185.84 with SMTP id v20mr16297088pgo.98.1481043229426; Tue, 06 Dec 2016 08:53:49 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id k11si20135570pgp.150.2016.12.06.08.53.49 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 06 Dec 2016 08:53:49 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-443613-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-443613-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-443613-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; q= dns; s=default; b=f6YlVNAUp+egm3h+zeN8mmbHGfZpzK/9GX+ESB9Lc0KvdW YjEoogZZrrZYYycX6po/0W4kusKHENPRISW0/wMSkrM/ECRNyWMKC3AWLua55naT TmhmmrHkLTg3KlfNK5lVIUfoREYRvE1vH6THIuI22X8TlcU9lvhR06hOWbu/Q= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:date:from:mime-version:to:subject:content-type; s= default; bh=QP5ndsB75slrpfFwtiN0/AQQbiU=; b=IuYWGEBpKL0K/k3w1WiU Z7dikAqyyD9XfcF0ct6rB6kdqkrq2dQnqNhl/EjgQDoZ7OmJ0Cdwg4MTaoDEUpcl btW7CaHDln7p2ESEe1SbGVs/y2iO+V+QNjOWMUTx0UDT0eLis9s2TjpGhlp5LyiB L87SThCCZBjYLufrP+Itrmo= Received: (qmail 130793 invoked by alias); 6 Dec 2016 16:53:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 130781 invoked by uid 89); 6 Dec 2016 16:53:35 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-3.8 required=5.0 tests=BAYES_00, KAM_LAZY_DOMAIN_SECURITY, RP_MATCHES_RCVD autolearn=ham version=3.3.2 spammy=kyrylotkachovarmcom, kyrylo, kyrylo.tkachov@arm.com, Kyrylo X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 06 Dec 2016 16:53:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8E0E215A1; Tue, 6 Dec 2016 08:53:23 -0800 (PST) Received: from [10.2.207.77] (e100706-lin.cambridge.arm.com [10.2.207.77]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3F58B3F220 for ; Tue, 6 Dec 2016 08:53:23 -0800 (PST) Message-ID: <5846ED01.3090007@foss.arm.com> Date: Tue, 06 Dec 2016 16:53:21 +0000 From: Kyrill Tkachov User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.2.0 MIME-Version: 1.0 To: GCC Patches Subject: [PATCH][ARM][committed] Sort ARMv8 processors by alphabetic order Hi all, I believe we try to keep the lists of processors in arm-cores.def in alphabetical order (though we don't follow it strictly) and the order of the cortex-m23 and cortex-m33 sticks out a bit. This patch puts them together and in alphabetical order in relation to the other processors in that group. Tested on arm-none-eabi. Committing as obvious. Thanks, Kyrill 2016-12-06 Kyrylo Tkachov * config/arm/arm-cores.def (cortex-m23, cortex-m33): Move into alphabetical order with respect to other ARMv8 processors. * config/arm/arm-tables.opt: Regenerate. * config/arm/arm-tune.md: Likewise. commit 26f63def862c4240a3166d6fa2801ffcd94878d5 Author: Kyrylo Tkachov Date: Mon Dec 5 09:51:29 2016 +0000 [ARM] Sort ARMv8 processors by alphabetic order diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index 3f77c71..fd96a41 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -166,14 +166,14 @@ ARM_CORE("cortex-a15.cortex-a7", cortexa15cortexa7, cortexa7, 7A, ARM_FSET_MAKE_ ARM_CORE("cortex-a17.cortex-a7", cortexa17cortexa7, cortexa7, 7A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_THUMB_DIV | FL_ARM_DIV | FL_FOR_ARCH7A), cortex_a12) /* V8 Architecture Processors */ -ARM_CORE("cortex-m23", cortexm23, cortexm23, 8M_BASE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8M_BASE), v6m) ARM_CORE("cortex-a32", cortexa32, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35) -ARM_CORE("cortex-m33", cortexm33, cortexm33, 8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m) ARM_CORE("cortex-a35", cortexa35, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a35) ARM_CORE("cortex-a53", cortexa53, cortexa53, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a53) ARM_CORE("cortex-a57", cortexa57, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) ARM_CORE("cortex-a72", cortexa72, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a57) ARM_CORE("cortex-a73", cortexa73, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), cortex_a73) +ARM_CORE("cortex-m23", cortexm23, cortexm23, 8M_BASE, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_FOR_ARCH8M_BASE), v6m) +ARM_CORE("cortex-m33", cortexm33, cortexm33, 8M_MAIN, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_ARCH7EM | FL_FOR_ARCH8M_MAIN), v7m) ARM_CORE("exynos-m1", exynosm1, exynosm1, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), exynosm1) ARM_CORE("falkor", falkor, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx) ARM_CORE("qdf24xx", qdf24xx, cortexa57, 8A, ARM_FSET_MAKE_CPU1 (FL_LDSCHED | FL_CRC32 | FL_FOR_ARCH8A), qdf24xx) diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index b12e458..b5e12dc 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -307,15 +307,9 @@ EnumValue Enum(processor_type) String(cortex-a17.cortex-a7) Value( TARGET_CPU_cortexa17cortexa7) EnumValue -Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23) - -EnumValue Enum(processor_type) String(cortex-a32) Value( TARGET_CPU_cortexa32) EnumValue -Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33) - -EnumValue Enum(processor_type) String(cortex-a35) Value( TARGET_CPU_cortexa35) EnumValue @@ -331,6 +325,12 @@ EnumValue Enum(processor_type) String(cortex-a73) Value( TARGET_CPU_cortexa73) EnumValue +Enum(processor_type) String(cortex-m23) Value( TARGET_CPU_cortexm23) + +EnumValue +Enum(processor_type) String(cortex-m33) Value( TARGET_CPU_cortexm33) + +EnumValue Enum(processor_type) String(exynos-m1) Value( TARGET_CPU_exynosm1) EnumValue diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md index 42a6d7a..4c92927 100644 --- a/gcc/config/arm/arm-tune.md +++ b/gcc/config/arm/arm-tune.md @@ -32,9 +32,9 @@ (define_attr "tune" cortexr4f,cortexr5,cortexr7, cortexr8,cortexm7,cortexm4, cortexm3,marvell_pj4,cortexa15cortexa7, - cortexa17cortexa7,cortexm23,cortexa32, - cortexm33,cortexa35,cortexa53, - cortexa57,cortexa72,cortexa73, + cortexa17cortexa7,cortexa32,cortexa35, + cortexa53,cortexa57,cortexa72, + cortexa73,cortexm23,cortexm33, exynosm1,falkor,qdf24xx, xgene1,cortexa57cortexa53,cortexa72cortexa53, cortexa73cortexa35,cortexa73cortexa53"