===================================================================
@@ -5082,7 +5082,7 @@ DEFHOOK
for the cstore being performed. Not definiting this hook is the same\
as accepting the mode encoded into operand 0 of the cstore expander\
patterns.",
- machine_mode, (enum insn_code icode),
+ scalar_int_mode, (enum insn_code icode),
default_cstore_mode)
/* This target hook allows the backend to compute the register pressure
===================================================================
@@ -2902,7 +2902,7 @@ This hook defines a class of registers w
This hook should return @code{true} if given class of registers should be an allocno class in any way. Usually RA uses only one register class from all classes containing the same register set. In some complicated cases, you need to have two or more such classes as allocno ones for RA correct work. Not defining this hook is equivalent to returning @code{false} for all inputs.
@end deftypefn
-@deftypefn {Target Hook} machine_mode TARGET_CSTORE_MODE (enum insn_code @var{icode})
+@deftypefn {Target Hook} scalar_int_mode TARGET_CSTORE_MODE (enum insn_code @var{icode})
This hook defines the machine mode to use for the boolean result of conditional store patterns. The ICODE argument is the instruction code for the cstore being performed. Not definiting this hook is the same as accepting the mode encoded into operand 0 of the cstore expander patterns.
@end deftypefn
===================================================================
@@ -670,7 +670,7 @@ static void sparc_print_operand_address
static reg_class_t sparc_secondary_reload (bool, rtx, reg_class_t,
machine_mode,
secondary_reload_info *);
-static machine_mode sparc_cstore_mode (enum insn_code icode);
+static scalar_int_mode sparc_cstore_mode (enum insn_code icode);
static void sparc_atomic_assign_expand_fenv (tree *, tree *, tree *);
static bool sparc_fixed_condition_code_regs (unsigned int *, unsigned int *);
static unsigned int sparc_min_arithmetic_precision (void);
@@ -13158,7 +13158,7 @@ sparc_modes_tieable_p (machine_mode mode
/* Implement TARGET_CSTORE_MODE. */
-static machine_mode
+static scalar_int_mode
sparc_cstore_mode (enum insn_code icode ATTRIBUTE_UNUSED)
{
return (TARGET_ARCH64 ? DImode : SImode);
===================================================================
@@ -229,7 +229,7 @@ extern const char *default_pch_valid_p (
extern void default_asm_output_ident_directive (const char*);
-extern machine_mode default_cstore_mode (enum insn_code);
+extern scalar_int_mode default_cstore_mode (enum insn_code);
extern bool default_member_type_forces_blk (const_tree, machine_mode);
extern void default_atomic_assign_expand_fenv (tree *, tree *, tree *);
extern tree build_va_arg_indirect_ref (tree);
===================================================================
@@ -1831,10 +1831,10 @@ default_pch_valid_p (const void *data_p,
/* Default version of cstore_mode. */
-machine_mode
+scalar_int_mode
default_cstore_mode (enum insn_code icode)
{
- return insn_data[(int) icode].operand[0].mode;
+ return as_a <scalar_int_mode> (insn_data[(int) icode].operand[0].mode);
}
/* Default version of member_type_forces_blk. */
===================================================================
@@ -5235,7 +5235,8 @@ emit_cstore (rtx target, enum insn_code
struct expand_operand ops[4];
rtx op0, comparison, subtarget;
rtx_insn *last;
- machine_mode result_mode = targetm.cstore_mode (icode);
+ scalar_int_mode result_mode = targetm.cstore_mode (icode);
+ scalar_int_mode int_target_mode;
last = get_last_insn ();
x = prepare_operand (icode, x, 2, mode, compare_mode, unsignedp);
@@ -5247,9 +5248,11 @@ emit_cstore (rtx target, enum insn_code
}
if (target_mode == VOIDmode)
- target_mode = result_mode;
+ int_target_mode = result_mode;
+ else
+ int_target_mode = as_a <scalar_int_mode> (target_mode);
if (!target)
- target = gen_reg_rtx (target_mode);
+ target = gen_reg_rtx (int_target_mode);
comparison = gen_rtx_fmt_ee (code, result_mode, x, y);
@@ -5265,20 +5268,20 @@ emit_cstore (rtx target, enum insn_code
subtarget = ops[0].value;
/* If we are converting to a wider mode, first convert to
- TARGET_MODE, then normalize. This produces better combining
+ INT_TARGET_MODE, then normalize. This produces better combining
opportunities on machines that have a SIGN_EXTRACT when we are
testing a single bit. This mostly benefits the 68k.
If STORE_FLAG_VALUE does not have the sign bit set when
interpreted in MODE, we can do this conversion as unsigned, which
is usually more efficient. */
- if (GET_MODE_SIZE (target_mode) > GET_MODE_SIZE (result_mode))
+ if (GET_MODE_SIZE (int_target_mode) > GET_MODE_SIZE (result_mode))
{
convert_move (target, subtarget,
val_signbit_known_clear_p (result_mode,
STORE_FLAG_VALUE));
op0 = target;
- result_mode = target_mode;
+ result_mode = int_target_mode;
}
else
op0 = subtarget;
@@ -5314,7 +5317,7 @@ emit_cstore (rtx target, enum insn_code
}
/* If we were converting to a smaller mode, do the conversion now. */
- if (target_mode != result_mode)
+ if (int_target_mode != result_mode)
{
convert_move (target, op0, 0);
return target;