From patchwork Wed Jun 1 17:27:59 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 1707 Return-Path: Delivered-To: unknown Received: from imap.gmail.com (74.125.159.109) by localhost6.localdomain6 with IMAP4-SSL; 08 Jun 2011 14:54:34 -0000 Delivered-To: patches@linaro.org Received: by 10.52.181.10 with SMTP id ds10cs322360vdc; Wed, 1 Jun 2011 10:28:02 -0700 (PDT) Received: by 10.52.66.206 with SMTP id h14mr4774343vdt.40.1306949281524; Wed, 01 Jun 2011 10:28:01 -0700 (PDT) Received: from mail-qy0-f171.google.com (mail-qy0-f171.google.com [209.85.216.171]) by mx.google.com with ESMTPS id br2si1620970vdb.142.2011.06.01.10.28.00 (version=TLSv1/SSLv3 cipher=OTHER); Wed, 01 Jun 2011 10:28:00 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.216.171 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.216.171; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.216.171 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by qyj19 with SMTP id 19so2327050qyj.16 for ; Wed, 01 Jun 2011 10:27:59 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.104.141 with SMTP id p13mr5363535qao.128.1306949279638; Wed, 01 Jun 2011 10:27:59 -0700 (PDT) Received: by 10.224.61.5 with HTTP; Wed, 1 Jun 2011 10:27:59 -0700 (PDT) Date: Wed, 1 Jun 2011 18:27:59 +0100 Message-ID: Subject: [Patch ARM] Unbreak bootstrap for --with-fpu=neon. From: Ramana Radhakrishnan To: gcc-patches@gcc.gnu.org Cc: Patch Tracking , Michael Hope Hi, It turns out that my effort last week in canonicalizing the vbic and the vorn patterns in the neon bug exposed a latent bug while bootstrapping trunk with Neon which Michael's tester picked up.. The splitting is slightly tricky because in T2 state you've got the orn instruction but in ARM state you don't . I intend to follow this up with a separate patch that turns some of these patterns off on the A8 in line with the other patches that have come in recently to do. Before doing that I also need to reorganize the arch attributes a bit and move the a8 and nota8 bits into a separate attribute - so that's the matter of another patch. Verified that the compiler passes bootstrap in both ARM and Thumb2 states . Regression tests are still running. It will be committed after tests finish. cheers Ramana 2011-05-31 Ramana Radhakrishnan * config/arm/neon.md (orndi3_neon): Actually split it. Index: gcc/config/arm/neon.md =================================================================== --- gcc/config/arm/neon.md (revision 174266) +++ gcc/config/arm/neon.md (working copy) @@ -801,17 +801,44 @@ [(set_attr "neon_type" "neon_int_1")] ) -(define_insn "orndi3_neon" - [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?&r") - (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,r")) - (match_operand:DI 1 "s_register_operand" "w,r,0")))] +;; TODO: investigate whether we should disable +;; this and bicdi3_neon for the A8 in line with the other +;; changes above. +(define_insn_and_split "orndi3_neon" + [(set (match_operand:DI 0 "s_register_operand" "=w,?=&r,?=&r,?&r") + (ior:DI (not:DI (match_operand:DI 2 "s_register_operand" "w,0,0,r")) + (match_operand:DI 1 "s_register_operand" "w,r,r,0")))] "TARGET_NEON" "@ vorn\t%P0, %P1, %P2 # + # #" - [(set_attr "neon_type" "neon_int_1,*,*") - (set_attr "length" "*,8,8")] + "reload_completed && + (TARGET_NEON && !(IS_VFP_REGNUM (REGNO (operands[0]))))" + [(set (match_dup 0) (ior:SI (not:SI (match_dup 2)) (match_dup 1))) + (set (match_dup 3) (ior:SI (not:SI (match_dup 4)) (match_dup 5)))] + " + { + if (TARGET_THUMB2) + { + operands[3] = gen_highpart (SImode, operands[0]); + operands[0] = gen_lowpart (SImode, operands[0]); + operands[4] = gen_highpart (SImode, operands[2]); + operands[2] = gen_lowpart (SImode, operands[2]); + operands[5] = gen_highpart (SImode, operands[1]); + operands[1] = gen_lowpart (SImode, operands[1]); + } + else + { + emit_insn (gen_one_cmpldi2 (operands[0], operands[2])); + emit_insn (gen_iordi3 (operands[0], operands[1], operands[0])); + DONE; + } + }" + [(set_attr "neon_type" "neon_int_1,*,*,*") + (set_attr "length" "*,16,8,8") + (set_attr "arch" "any,a,t2,t2")] ) (define_insn "bic3_neon"