From patchwork Mon Jun 20 12:16:24 2011 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramana Radhakrishnan X-Patchwork-Id: 2083 Return-Path: X-Original-To: patchwork@peony.canonical.com Delivered-To: patchwork@peony.canonical.com Received: from fiordland.canonical.com (fiordland.canonical.com [91.189.94.145]) by peony.canonical.com (Postfix) with ESMTP id A005E23F08 for ; Mon, 20 Jun 2011 12:16:26 +0000 (UTC) Received: from mail-vx0-f180.google.com (mail-vx0-f180.google.com [209.85.220.180]) by fiordland.canonical.com (Postfix) with ESMTP id 696CBA185FB for ; Mon, 20 Jun 2011 12:16:26 +0000 (UTC) Received: by vxd7 with SMTP id 7so2297174vxd.11 for ; Mon, 20 Jun 2011 05:16:25 -0700 (PDT) Received: by 10.52.175.197 with SMTP id cc5mr3365819vdc.287.1308572185621; Mon, 20 Jun 2011 05:16:25 -0700 (PDT) X-Forwarded-To: linaro-patchwork@canonical.com X-Forwarded-For: patch@linaro.org linaro-patchwork@canonical.com Delivered-To: patches@linaro.org Received: by 10.52.183.130 with SMTP id em2cs59vdc; Mon, 20 Jun 2011 05:16:25 -0700 (PDT) Received: by 10.52.177.166 with SMTP id cr6mr607628vdc.151.1308572184863; Mon, 20 Jun 2011 05:16:24 -0700 (PDT) Received: from mail-qy0-f171.google.com (mail-qy0-f171.google.com [209.85.216.171]) by mx.google.com with ESMTPS id f14si2659190vdt.78.2011.06.20.05.16.24 (version=TLSv1/SSLv3 cipher=OTHER); Mon, 20 Jun 2011 05:16:24 -0700 (PDT) Received-SPF: neutral (google.com: 209.85.216.171 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) client-ip=209.85.216.171; Authentication-Results: mx.google.com; spf=neutral (google.com: 209.85.216.171 is neither permitted nor denied by best guess record for domain of ramana.radhakrishnan@linaro.org) smtp.mail=ramana.radhakrishnan@linaro.org Received: by mail-qy0-f171.google.com with SMTP id 38so1698490qyl.16 for ; Mon, 20 Jun 2011 05:16:24 -0700 (PDT) MIME-Version: 1.0 Received: by 10.224.175.211 with SMTP id bb19mr3658306qab.95.1308572184527; Mon, 20 Jun 2011 05:16:24 -0700 (PDT) Received: by 10.224.29.8 with HTTP; Mon, 20 Jun 2011 05:16:24 -0700 (PDT) Date: Mon, 20 Jun 2011 13:16:24 +0100 Message-ID: Subject: [Patch ARM] fix PR target/49385 From: Ramana Radhakrishnan To: gcc-patches Cc: Patch Tracking Hi, This fixes PR49385. We were allowing mem -> mem moves earlier. Thanks to Revital for spotting this. Tested on qemu with arm-linux-gnueabi cross and committed to trunk. Cheers Ramana 2011-06-20 Ramana Radhakrishnan PR target/49385 * config/arm/thumb2.md (*thumb2_movhi_insn): Make sure atleast one of the operands is a register. Index: gcc/config/arm/thumb2.md =================================================================== --- gcc/config/arm/thumb2.md (revision 175205) +++ gcc/config/arm/thumb2.md (working copy) @@ -207,7 +207,9 @@ (define_insn "*thumb2_movhi_insn" [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,m,r") (match_operand:HI 1 "general_operand" "rI,n,r,m"))] - "TARGET_THUMB2" + "TARGET_THUMB2 + && (register_operand (operands[0], HImode) + || register_operand (operands[1], HImode))" "@ mov%?\\t%0, %1\\t%@ movhi movw%?\\t%0, %L1\\t%@ movhi