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[209.132.180.131]) by mx.google.com with ESMTPS id uc9si11874602pac.376.2014.03.18.01.16.22 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 18 Mar 2014 01:16:27 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-363416-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Received: (qmail 25059 invoked by alias); 18 Mar 2014 08:16:09 -0000 Mailing-List: list patchwork-forward@linaro.org; contact patchwork-forward+owners@linaro.org Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: , List-Help: , Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 25048 invoked by uid 89); 18 Mar 2014 08:16:08 -0000 X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.5 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-la0-f50.google.com Received: from mail-la0-f50.google.com (HELO mail-la0-f50.google.com) (209.85.215.50) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Tue, 18 Mar 2014 08:16:07 +0000 Received: by mail-la0-f50.google.com with SMTP id y1so4479948lam.37 for ; Tue, 18 Mar 2014 01:16:03 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.152.87.14 with SMTP id t14mr51011laz.52.1395130563548; Tue, 18 Mar 2014 01:16:03 -0700 (PDT) Received: by 10.112.135.105 with HTTP; Tue, 18 Mar 2014 01:16:03 -0700 (PDT) Date: Tue, 18 Mar 2014 16:16:03 +0800 Message-ID: Subject: [PATCH, AARCH64] movcc for fcsel From: Zhenqiang Chen To: "gcc-patches@gcc.gnu.org" Cc: Marcus Shawcroft , Richard Earnshaw X-IsSubscribed: yes X-Original-Sender: zhenqiang.chen@linaro.org X-Original-Authentication-Results: mx.google.com; spf=neutral (google.com: 2607:f8b0:400c:c01::229 is neither permitted nor denied by best guess record for domain of patch+caf_=patchwork-forward=linaro.org@linaro.org) smtp.mail=patch+caf_=patchwork-forward=linaro.org@linaro.org; dkim=pass header.i=@gcc.gnu.org X-Google-Group-Id: 836684582541 Hi, For float value, movsfcc/movdfcc is required by emit_conditional_move called in ifcvt pass to expand if-then-else to "fcsel" insn. Bootstrap and no make check regression with qemu-aarch64. Is it OK for next stage1? Thanks! -Zhenqiang ChangeLog: 2014-03-18 Zhenqiang Chen * config/aarch64/aarch64.md (movcc): New for GPF. testsuite/ChangeLog: 2014-03-18 Zhenqiang Chen * gcc.target/aarch64/fcsel.c: New test case. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 99a6ac8..0f4b8ebf 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -2344,6 +2344,25 @@ } ) +(define_expand "movcc" + [(set (match_operand:GPF 0 "register_operand" "") + (if_then_else:GPF (match_operand 1 "aarch64_comparison_operator" "") + (match_operand:GPF 2 "register_operand" "") + (match_operand:GPF 3 "register_operand" "")))] + "" + { + rtx ccreg; + enum rtx_code code = GET_CODE (operands[1]); + + if (code == UNEQ || code == LTGT) + FAIL; + + ccreg = aarch64_gen_compare_reg (code, XEXP (operands[1], 0), + XEXP (operands[1], 1)); + operands[1] = gen_rtx_fmt_ee (code, VOIDmode, ccreg, const0_rtx); + } +) + (define_insn "*csinc2_insn" [(set (match_operand:GPI 0 "register_operand" "=r") (plus:GPI (match_operator:GPI 2 "aarch64_comparison_operator" diff --git a/gcc/testsuite/gcc.target/aarch64/fcsel.c b/gcc/testsuite/gcc.target/aarch64/fcsel.c new file mode 100644 index 0000000..9c5431a --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/fcsel.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 " } */ + +float f1 (float a, float b, float c, float d) +{ + if (a > 0.0) + return c; + else + return 2.0; +} + +double f2 (double a, double b, double c, double d) +{ + if (a > b) + return c; + else + return d; +} + +/* { dg-final { scan-assembler-times "\tfcsel" 2 } } */