From patchwork Sat Oct 31 03:34:56 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Charles Baylis X-Patchwork-Id: 55865 Delivered-To: patch@linaro.org Received: by 10.112.61.134 with SMTP id p6csp196433lbr; Fri, 30 Oct 2015 20:35:32 -0700 (PDT) X-Received: by 10.68.203.73 with SMTP id ko9mr12648213pbc.139.1446262532220; Fri, 30 Oct 2015 20:35:32 -0700 (PDT) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id ax2si15625832pbc.170.2015.10.30.20.35.31 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 30 Oct 2015 20:35:32 -0700 (PDT) Received-SPF: pass (google.com: domain of gcc-patches-return-412244-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; spf=pass (google.com: domain of gcc-patches-return-412244-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-412244-patch=linaro.org@gcc.gnu.org; dkim=pass header.i=@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:cc:content-type; q=dns; s=default; b=Fp6TSkYqQAWlUgs8kDYwvPwmIQAfZt31p/Ex0AYWLai /1ntJetbCWU26ueEbH9ELmevfY5Y4BwAIPK+F5xeoUmyCrOBAbfcZOn/XO36zLJe bugoaDQKACSjtlxLaFtl3uhle2jBtVZ6AOv5vFhVAtWcx8ehnqWXmuNLKG/YYMJA = DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:cc:content-type; s=default; bh=v66DNGqJVG42xlnkBYC5xae91Bo=; b=yJ5OXHANMDSMqVcVl pg4yBINQpseIf9ZKtVEfWjOCJ7HQ6Hb5rALGqyY/UFJXwTunRWKPgKwToceO+Mh2 vA/snAUlnjxhRTDMujIZ23w9Ke85NM+uU6egNXpFM04bfyDUqM8YzOqdJGOGKm1K QfN+ncSkMPh051xikNG4YBAyCE= Received: (qmail 20007 invoked by alias); 31 Oct 2015 03:35:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 2441 invoked by uid 89); 31 Oct 2015 03:35:01 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.4 required=5.0 tests=AWL, BAYES_00, RCVD_IN_DNSWL_LOW, SPF_PASS, UPPERCASE_50_75 autolearn=ham version=3.3.2 X-HELO: mail-ob0-f169.google.com Received: from mail-ob0-f169.google.com (HELO mail-ob0-f169.google.com) (209.85.214.169) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-GCM-SHA256 encrypted) ESMTPS; Sat, 31 Oct 2015 03:34:58 +0000 Received: by obbwb3 with SMTP id wb3so59266138obb.0 for ; Fri, 30 Oct 2015 20:34:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:mime-version:date:message-id:subject:from:to:cc :content-type; bh=V+tv2GeyQ50JLS845E7U3zG9xX/6dJ5gbJpxHkiy80s=; b=d5L1DZLPln8V7ouhTCx4utmved7OGbKIcpu1eQV1KKeE7733exHqwACrQkfdnajRGr GOoxJNSNtjdLCtiHdPYuSD+fOMrlbKs5yBSdpGZOq3TzTCp8OisJFdZmK+MpQUS4lLvH BCnp71qzXtBUSpxbdtDSdfOYpZ8OEORH4ln4sZblgc620MirrQyNiBZINLsjw1iogDsX exDV3Zm3JpChb1ihbiqM8cL+qkxgUIQz2IdQT6BU7y3nE7/5U5nqiCYdoYLp9hbl+c6s ad8F0ljBRidgVerjOJkbyOvVtTqpc/jW0OK2QQm6GSXrYsMKnLFqF4x8UtdEGbuXpU6T c3KA== X-Gm-Message-State: ALoCoQn9PqDGXF9HoB9mtOJ1yW4d5FXcYpIGctjcHkP5zAMMEY++5Ih3g082+sQsBuEsGbY7jE8Y MIME-Version: 1.0 X-Received: by 10.60.123.2 with SMTP id lw2mr8465170oeb.2.1446262496302; Fri, 30 Oct 2015 20:34:56 -0700 (PDT) Received: by 10.202.65.69 with HTTP; Fri, 30 Oct 2015 20:34:56 -0700 (PDT) Date: Sat, 31 Oct 2015 03:34:56 +0000 Message-ID: Subject: [PATCH] [ARM] PR61551 RFC: Improve costs for NEON addressing modes From: Charles Baylis To: Ramana Radhakrishnan Cc: GCC Patches , Kyrylo Tkachov , Richard Earnshaw X-IsSubscribed: yes Hi Ramana, [revisiting https://gcc.gnu.org/ml/gcc-patches/2015-06/msg01593.html] https://gcc.gnu.org/bugzilla/show_bug.cgi?id=61551 This patch is an initial attempt to rework the ARM rtx costs to better handle the costs of various addressing modes, in particular to remove the incorrect large costs associated with post-indexed addressing in NEON memory operations. This patch introduces per-core tables for the costs of using different addressing modes for different access modes. I have retained the original code so that the calculated costs can be compared. Currently, the tables replicate the costs calculated by the original code, and a debug assert is left in place. Obviously, a fair amount of clean up is needed before this can be applied, but I would like a quick comment on the general approach to check that I haven't completely missed the point before continuing. After that, I will clean up the coding style, check for impact on the AArch64 backend, remove the debug code and in a separate patch improve the tuning for the vector modes. Thanks Charles >From b10c6dd7af1f5b9821946783ba9d96b08c751f2b Mon Sep 17 00:00:00 2001 From: Charles Baylis Date: Wed, 28 Oct 2015 18:48:16 +0000 Subject: [PATCH] WIP Change-Id: If349ffd7dbbe13a814be4a0d022382ddc8270973 --- gcc/config/arm/aarch-common-protos.h | 28 ++ gcc/config/arm/aarch-cost-tables.h | 328 +++++++++++++++++ gcc/config/arm/arm.c | 677 ++++++++++++++++++++++++++++++++++- 3 files changed, 1023 insertions(+), 10 deletions(-) diff --git a/gcc/config/arm/aarch-common-protos.h b/gcc/config/arm/aarch-common-protos.h index 348ae74..dae42d7 100644 --- a/gcc/config/arm/aarch-common-protos.h +++ b/gcc/config/arm/aarch-common-protos.h @@ -130,6 +130,33 @@ struct vector_cost_table const int alu; }; +struct cbmem_cost_table +{ + enum access_type + { + REG, + POST_INCDEC, + PRE_INCDEC, + /*PRE_MODIFY,*/ + POST_MODIFY, + PLUS, + ACCESS_TYPE_LAST = PLUS + }; + const int si[ACCESS_TYPE_LAST + 1]; + const int di[ACCESS_TYPE_LAST + 1]; + const int cdi[ACCESS_TYPE_LAST + 1]; + const int sf[ACCESS_TYPE_LAST + 1]; + const int df[ACCESS_TYPE_LAST + 1]; + const int cdf[ACCESS_TYPE_LAST + 1]; + const int blk[ACCESS_TYPE_LAST + 1]; + const int vec64[ACCESS_TYPE_LAST + 1]; + const int vec128[ACCESS_TYPE_LAST + 1]; + const int vec192[ACCESS_TYPE_LAST + 1]; + const int vec256[ACCESS_TYPE_LAST + 1]; + const int vec384[ACCESS_TYPE_LAST + 1]; + const int vec512[ACCESS_TYPE_LAST + 1]; +}; + struct cpu_cost_table { const struct alu_cost_table alu; @@ -137,6 +164,7 @@ struct cpu_cost_table const struct mem_cost_table ldst; const struct fp_cost_table fp[2]; /* SFmode and DFmode. */ const struct vector_cost_table vect; + const struct cbmem_cost_table addr; }; diff --git a/gcc/config/arm/aarch-cost-tables.h b/gcc/config/arm/aarch-cost-tables.h index 66e09a8..c5ecdcf 100644 --- a/gcc/config/arm/aarch-cost-tables.h +++ b/gcc/config/arm/aarch-cost-tables.h @@ -122,6 +122,88 @@ const struct cpu_cost_table generic_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; @@ -225,6 +307,88 @@ const struct cpu_cost_table cortexa53_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; @@ -328,6 +492,88 @@ const struct cpu_cost_table cortexa57_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; @@ -431,6 +677,88 @@ const struct cpu_cost_table xgene1_extra_costs = /* Vector */ { COSTS_N_INSNS (2) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index a598c84..29e94ed 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -1063,6 +1063,88 @@ const struct cpu_cost_table cortexa9_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; @@ -1166,6 +1248,88 @@ const struct cpu_cost_table cortexa8_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; @@ -1270,6 +1434,88 @@ const struct cpu_cost_table cortexa5_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; @@ -1375,6 +1621,88 @@ const struct cpu_cost_table cortexa7_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; @@ -1478,6 +1806,88 @@ const struct cpu_cost_table cortexa12_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; @@ -1581,6 +1991,88 @@ const struct cpu_cost_table cortexa15_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; @@ -1684,6 +2176,88 @@ const struct cpu_cost_table v7m_extra_costs = /* Vector */ { COSTS_N_INSNS (1) /* alu. */ + }, + /* Memory */ + { + { 0, 0, 0, 0, 0 }, /* si */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* di */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdi */ + { 0, 0, 0, 0, 0 }, /* sf */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* df */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* cdf */ + { + 0, + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + - COSTS_N_INSNS (1), + }, /* blk */ + { + 0, + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1), + COSTS_N_INSNS (1) + }, /* vec64 */ + { + 0, + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3), + COSTS_N_INSNS (3) + }, /* vec128 */ + { + 0, + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5), + COSTS_N_INSNS (5) + }, /* vec192 */ + { + 0, + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7), + COSTS_N_INSNS (7) + }, /* vec256 */ + { + 0, + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11), + COSTS_N_INSNS (11) + }, /* vec384 */ + { + 0, + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15), + COSTS_N_INSNS (15) + } /* vec512 */ } }; @@ -9442,6 +10016,22 @@ arm_unspec_cost (rtx x, enum rtx_code /* outer_code */, bool speed_p, int *cost) } \ while (0); +/* Return TRUE if MODE is any of the large INT modes. */ +static bool +arm_vect_struct_mode_p (machine_mode mode) +{ + return mode == OImode || mode == EImode || mode == TImode || mode == CImode + || mode == XImode; +} + + +/* Return TRUE if MODE is any of the vector modes. */ +static bool +arm_vector_mode_p (machine_mode mode) +{ + return arm_vector_mode_supported_p (mode) || arm_vect_struct_mode_p (mode); +} + /* RTX costs. Make an estimate of the cost of executing the operation X, which is contained with an operation with code OUTER_CODE. SPEED_P indicates whether the cost desired is the performance cost, @@ -9524,16 +10114,83 @@ arm_new_rtx_costs (rtx x, enum rtx_code code, enum rtx_code outer_code, case MEM: /* A memory access costs 1 insn if the mode is small, or the address is a single register, otherwise it costs one insn per word. */ - if (REG_P (XEXP (x, 0))) - *cost = COSTS_N_INSNS (1); - else if (flag_pic - && GET_CODE (XEXP (x, 0)) == PLUS - && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) - /* This will be split into two instructions. - See arm.md:calculate_pic_address. */ - *cost = COSTS_N_INSNS (2); - else - *cost = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + { + int cost_old; + int cost_new; + cbmem_cost_table::access_type op; + if (REG_P (XEXP (x, 0))) + cost_old = COSTS_N_INSNS (1); + else if (flag_pic + && GET_CODE (XEXP (x, 0)) == PLUS + && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) + /* This will be split into two instructions. + See arm.md:calculate_pic_address. */ + cost_old = COSTS_N_INSNS (2); + else + cost_old = COSTS_N_INSNS (ARM_NUM_REGS (mode)); + switch (GET_CODE (XEXP (x, 0))) + { + case REG: + op = cbmem_cost_table::REG; + break; + case POST_INC: + case POST_DEC: + op = cbmem_cost_table::POST_INCDEC; + break; + case PRE_INC: + case PRE_DEC: + op = cbmem_cost_table::PRE_INCDEC; + break; + case POST_MODIFY: + op = cbmem_cost_table::POST_MODIFY; + break; + default: + case PLUS: + op = cbmem_cost_table::PLUS; + break; + } + if (flag_pic + && GET_CODE (XEXP (x, 0)) == PLUS + && will_be_in_index_register (XEXP (XEXP (x, 0), 1))) + cost_new = COSTS_N_INSNS (2); + else + { + cost_new = COSTS_N_INSNS (1); + if (arm_vector_mode_p (mode)) + { + cost_new += + (ARM_NUM_REGS (mode) <= 2 ? extra_cost->addr.vec64[op] + : ARM_NUM_REGS (mode) <= 4 ? extra_cost->addr.vec128[op] + : ARM_NUM_REGS (mode) <= 6 ? extra_cost->addr.vec192[op] + : ARM_NUM_REGS (mode) <= 8 ? extra_cost->addr.vec256[op] + : ARM_NUM_REGS (mode) <= 12 ? extra_cost->addr.vec384[op] + : extra_cost->addr.vec512[op]); + } + else if (FLOAT_MODE_P (mode)) + { + cost_new += + (ARM_NUM_REGS (mode) <= 1 ? extra_cost->addr.sf[op] + : ARM_NUM_REGS (mode) <= 2 ? extra_cost->addr.df[op] + : extra_cost->addr.cdf[op]); + } + else if (mode == BLKmode) + cost_new += extra_cost->addr.blk[op]; + else + { /* integer modes */ + cost_new += + (ARM_NUM_REGS (mode) <= 1 ? extra_cost->addr.si[op] + : ARM_NUM_REGS (mode) <= 2 ? extra_cost->addr.di[op] + : extra_cost->addr.cdi[op]); + } + } + *cost = cost_old; + if (cost_old != cost_new) + { + debug_rtx(x); + fprintf(stderr,"old(%d) new(%d)\n", cost_old, cost_new); + gcc_assert (cost_old == cost_new); + } + } /* For speed optimizations, add the costs of the address and accessing memory. */ -- 1.9.1