From patchwork Thu Dec 15 16:06:19 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 88180 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp880387qgi; Thu, 15 Dec 2016 08:07:42 -0800 (PST) X-Received: by 10.99.1.132 with SMTP id 126mr3337619pgb.129.1481818062160; Thu, 15 Dec 2016 08:07:42 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id 1si3089444plu.329.2016.12.15.08.07.41 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Dec 2016 08:07:42 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-444522-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-444522-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-444522-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; q=dns; s=default; b=Ecq9I7djIP/n/LSw797SEk8dIzgRP fT8nHwi/8mMaS1IS+R28oMR1+0DqnDsauHqchwHGaH1sVWTAKnNuZgPUWRVUgucU W/nABi1eoT47Qu+CoVlurZM6gtr5UClSgv05uLfrD9FU0hhz91IhMI2xVxAKieZ5 ODQaw3odZ9p7+E= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; s=default; bh=2rO0V1y3lH3qfHGvnT5l0GG7gTc=; b=RoP tkjJIs+cDW/cEW+aO5IbjQVbCOtAkHf7196/dM2EKwrs0TLYdOf/diKEEjuAsBtx jgL9opnAFN21umn7eZfjCkn5k/M2Bt3Snwzb4ZagvxYILzttrZY4aCzRS7GFmEaQ OFTVR3kZeD2c9umM4IHwavKKshDIdxAzfCCXXEg8= Received: (qmail 34763 invoked by alias); 15 Dec 2016 16:06:30 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 34704 invoked by uid 89); 15 Dec 2016 16:06:30 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.0 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=choices X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Dec 2016 16:06:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B9E61516; Thu, 15 Dec 2016 08:06:21 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2E4FA3F445 for ; Thu, 15 Dec 2016 08:06:21 -0800 (PST) From: "Richard Earnshaw (lists)" Subject: [PATCH 08/21] [arm] Remove insn_flags. To: gcc-patches@gcc.gnu.org References: Message-ID: Date: Thu, 15 Dec 2016 16:06:19 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: This patch finishes the job of removing insn_flags and moves the logic over to using the new data structures. I've added a new boolean variable to detect when we have ARMv7ve-like capabilities and thus have 64-bit atomic operations since that would be a complex query and expensive to do in full. It might be better to add a specific bit to the ISA data structures to indicate this capability directly. * arm-protos.h (insn_flags): Delete declaration. (arm_arch7ve): Declare. * arm.c (insn_flags): Delete. (arm_arch7ve): New variable. (arm_selected_cpu): Delete. (arm_option_check_internal): Use new ISA bitmap. (arm_option_override_internal): Likewise. (arm_configure_build_target): Declare arm_selected_cpu locally. (arm_option_override): Use new ISA bitmap. Initialize arm_arch7ve. Rearrange variable intialization by general function. * arm.h (TARGET_HAVE_LPAE): Use arm_arch7ve. --- gcc/config/arm/arm-protos.h | 7 ++- gcc/config/arm/arm.c | 103 +++++++++++++++++++++++--------------------- gcc/config/arm/arm.h | 3 +- 3 files changed, 57 insertions(+), 56 deletions(-) diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 7673e3a..659959b 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -353,10 +353,6 @@ extern void arm_cpu_cpp_builtins (struct cpp_reader *); extern bool arm_is_constant_pool_ref (rtx); -/* The bits in this mask specify which - instructions we are allowed to generate. */ -extern arm_feature_set insn_flags; - /* The bits in this mask specify which instruction scheduling options should be used. */ extern unsigned int tune_flags; @@ -391,6 +387,9 @@ extern int arm_arch6m; /* Nonzero if this chip supports the ARM 7 extensions. */ extern int arm_arch7; +/* Nonzero if this chip supports the ARM 7ve extensions. */ +extern int arm_arch7ve; + /* Nonzero if instructions not present in the 'M' profile can be used. */ extern int arm_arch_notm; diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index c6be4d8..0b82714 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -779,10 +779,6 @@ int arm_fpu_attr; rtx thumb_call_via_label[14]; static int thumb_call_reg_needed; -/* The bits in this mask specify which - instructions we are allowed to generate. */ -arm_feature_set insn_flags = ARM_FSET_EMPTY; - /* The bits in this mask specify which instruction scheduling options should be used. */ unsigned int tune_flags = 0; @@ -828,6 +824,9 @@ int arm_arch6m = 0; /* Nonzero if this chip supports the ARM 7 extensions. */ int arm_arch7 = 0; +/* Nonzero if this chip supports the ARM 7ve extensions. */ +int arm_arch7ve = 0; + /* Nonzero if instructions not present in the 'M' profile can be used. */ int arm_arch_notm = 0; @@ -2316,11 +2315,6 @@ static const struct processors all_architectures[] = {NULL, TARGET_CPU_arm_none, 0, NULL, BASE_ARCH_0, {isa_nobit}, ARM_FSET_EMPTY, NULL} }; - -/* These are populated as commandline arguments are processed, or NULL - if not specified. */ -static const struct processors *arm_selected_cpu; - /* The name of the preprocessor macro to define for this architecture. PROFILE is replaced by the architecture name (eg. 8A) in arm_option_override () and is thus chosen to be big enough to hold the longest architecture name. */ @@ -2821,13 +2815,14 @@ arm_option_check_internal (struct gcc_options *opts) const struct arm_fpu_desc *fpu_desc = &all_fpus[opts->x_arm_fpu_index]; /* iWMMXt and NEON are incompatible. */ - if (TARGET_IWMMXT - && ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON)) + if (TARGET_IWMMXT + && ARM_FPU_FSET_HAS (fpu_desc->features, FPU_FL_NEON)) error ("iWMMXt and NEON are incompatible"); /* Make sure that the processor choice does not conflict with any of the other command line choices. */ - if (TARGET_ARM_P (flags) && !ARM_FSET_HAS_CPU1 (insn_flags, FL_NOTM)) + if (TARGET_ARM_P (flags) + && !bitmap_bit_p (arm_active_target.isa, isa_bit_notm)) error ("target CPU does not support ARM mode"); /* TARGET_BACKTRACE calls leaf_function_p, which causes a crash if done @@ -2949,7 +2944,7 @@ arm_option_override_internal (struct gcc_options *opts, { arm_override_options_after_change_1 (opts); - if (TARGET_INTERWORK && !ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB)) + if (TARGET_INTERWORK && !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb)) { /* The default is to enable interworking, so this warning message would be confusing to users who have just compiled with, eg, -march=armv3. */ @@ -2958,7 +2953,7 @@ arm_option_override_internal (struct gcc_options *opts, } if (TARGET_THUMB_P (opts->x_target_flags) - && !(ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB))) + && !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb)) { warning (0, "target CPU does not support THUMB instructions"); opts->x_target_flags &= ~MASK_THUMB; @@ -3069,8 +3064,7 @@ arm_configure_build_target (struct arm_build_target *target, { const struct processors *arm_selected_tune = NULL; const struct processors *arm_selected_arch = NULL; - - arm_selected_cpu = NULL; + const struct processors *arm_selected_cpu = NULL; bitmap_clear (target->isa); target->core_name = NULL; @@ -3284,7 +3278,6 @@ arm_option_override (void) #endif sprintf (arm_arch_name, "__ARM_ARCH_%s__", arm_active_target.arch_pp_name); - insn_flags = arm_selected_cpu->flags; arm_base_arch = arm_active_target.base_arch; arm_tune = arm_active_target.tune_core; @@ -3298,7 +3291,8 @@ arm_option_override (void) /* BPABI targets use linker tricks to allow interworking on cores without thumb support. */ if (TARGET_INTERWORK - && !(ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB) || TARGET_BPABI)) + && !TARGET_BPABI + && !bitmap_bit_p (arm_active_target.isa, isa_bit_thumb)) { warning (0, "target CPU does not support interworking" ); target_flags &= ~MASK_INTERWORK; @@ -3319,46 +3313,55 @@ arm_option_override (void) if (TARGET_APCS_REENT) warning (0, "APCS reentrant code not supported. Ignored"); - /* Initialize boolean versions of the flags, for use in the arm.md file. */ - arm_arch3m = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH3M); - arm_arch4 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH4); - arm_arch4t = arm_arch4 && (ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB)); - arm_arch5 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH5); - arm_arch5e = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH5E); - arm_arch6 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6); - arm_arch6k = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6K); - arm_arch6kz = arm_arch6k && ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH6KZ); - arm_arch_notm = ARM_FSET_HAS_CPU1 (insn_flags, FL_NOTM); + /* Initialize boolean versions of the architectural flags, for use + in the arm.md file. */ + arm_arch3m = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv3m); + arm_arch4 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv4); + arm_arch4t = arm_arch4 && bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); + arm_arch5 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv5); + arm_arch5e = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv5e); + arm_arch6 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv6); + arm_arch6k = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv6k); + arm_arch_notm = bitmap_bit_p (arm_active_target.isa, isa_bit_notm); arm_arch6m = arm_arch6 && !arm_arch_notm; - arm_arch7 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7); - arm_arch7em = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH7EM); - arm_arch8 = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARCH8); - arm_arch8_1 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_1); - arm_arch8_2 = ARM_FSET_HAS_CPU2 (insn_flags, FL2_ARCH8_2); - arm_arch_thumb1 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB); - arm_arch_thumb2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB2); - arm_arch_xscale = ARM_FSET_HAS_CPU1 (insn_flags, FL_XSCALE); + arm_arch7 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv7); + arm_arch7em = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv7em); + arm_arch8 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8); + arm_arch8_1 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8_1); + arm_arch8_2 = bitmap_bit_p (arm_active_target.isa, isa_bit_ARMv8_2); + arm_arch_thumb1 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb); + arm_arch_thumb2 = bitmap_bit_p (arm_active_target.isa, isa_bit_thumb2); + arm_arch_xscale = bitmap_bit_p (arm_active_target.isa, isa_bit_xscale); + arm_arch_iwmmxt = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt); + arm_arch_iwmmxt2 = bitmap_bit_p (arm_active_target.isa, isa_bit_iwmmxt2); + arm_arch_thumb_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_tdiv); + arm_arch_arm_hwdiv = bitmap_bit_p (arm_active_target.isa, isa_bit_adiv); + arm_arch_crc = bitmap_bit_p (arm_active_target.isa, isa_bit_crc32); + arm_arch_cmse = bitmap_bit_p (arm_active_target.isa, isa_bit_cmse); + arm_fp16_inst = bitmap_bit_p (arm_active_target.isa, isa_bit_fp16); + arm_arch7ve + = (arm_arch6k && arm_arch7 && arm_arch_thumb_hwdiv && arm_arch_arm_hwdiv); + if (arm_fp16_inst) + { + if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) + error ("selected fp16 options are incompatible."); + arm_fp16_format = ARM_FP16_FORMAT_IEEE; + } + + /* Set up some tuning parameters. */ arm_ld_sched = (tune_flags & TF_LDSCHED) != 0; arm_tune_strongarm = (tune_flags & TF_STRONG) != 0; arm_tune_wbuf = (tune_flags & TF_WBUF) != 0; arm_tune_xscale = (tune_flags & TF_XSCALE) != 0; - arm_arch_iwmmxt = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT); - arm_arch_iwmmxt2 = ARM_FSET_HAS_CPU1 (insn_flags, FL_IWMMXT2); - arm_arch_thumb_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_THUMB_DIV); - arm_arch_arm_hwdiv = ARM_FSET_HAS_CPU1 (insn_flags, FL_ARM_DIV); - arm_arch_no_volatile_ce = ARM_FSET_HAS_CPU1 (insn_flags, FL_NO_VOLATILE_CE); arm_tune_cortex_a9 = (arm_tune == TARGET_CPU_cortexa9) != 0; - arm_arch_crc = ARM_FSET_HAS_CPU1 (insn_flags, FL_CRC32); - arm_arch_cmse = ARM_FSET_HAS_CPU2 (insn_flags, FL2_CMSE); arm_m_profile_small_mul = (tune_flags & TF_SMALLMUL) != 0; - arm_fp16_inst = ARM_FSET_HAS_CPU2 (insn_flags, FL2_FP16INST); - if (arm_fp16_inst) - { - if (arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) - error ("selected fp16 options are incompatible."); - arm_fp16_format = ARM_FP16_FORMAT_IEEE; - } + + /* And finally, set up some quirks. */ + arm_arch_no_volatile_ce + = bitmap_bit_p (arm_active_target.isa, isa_quirk_no_volatile_ce); + arm_arch6kz + = arm_arch6k && bitmap_bit_p (arm_active_target.isa, isa_quirk_ARMv6kz); /* V5 code we generate is completely interworking capable, so we turn off TARGET_INTERWORK here to avoid many tests later on. */ diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 928fad4..6661314 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -252,8 +252,7 @@ extern tree arm_fp16_type_node; || (arm_arch8 && !arm_arch_notm)) /* Nonzero if this chip supports LPAE. */ -#define TARGET_HAVE_LPAE \ - (arm_arch7 && ARM_FSET_HAS_CPU1 (insn_flags, FL_FOR_ARCH7VE)) +#define TARGET_HAVE_LPAE (arm_arch7ve) /* Nonzero if this chip supports ldrex{bh} and strex{bh}. */ #define TARGET_HAVE_LDREXBH ((arm_arch6k && TARGET_ARM) \