From patchwork Thu Dec 15 16:08:05 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Richard Earnshaw \(lists\)" X-Patchwork-Id: 88193 Delivered-To: patch@linaro.org Received: by 10.140.20.101 with SMTP id 92csp882952qgi; Thu, 15 Dec 2016 08:11:38 -0800 (PST) X-Received: by 10.84.197.129 with SMTP id n1mr3949352pld.30.1481818298277; Thu, 15 Dec 2016 08:11:38 -0800 (PST) Return-Path: Received: from sourceware.org (server1.sourceware.org. [209.132.180.131]) by mx.google.com with ESMTPS id g33si3108522plb.310.2016.12.15.08.11.37 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 15 Dec 2016 08:11:38 -0800 (PST) Received-SPF: pass (google.com: domain of gcc-patches-return-444535-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) client-ip=209.132.180.131; Authentication-Results: mx.google.com; dkim=pass header.i=@gcc.gnu.org; spf=pass (google.com: domain of gcc-patches-return-444535-patch=linaro.org@gcc.gnu.org designates 209.132.180.131 as permitted sender) smtp.mailfrom=gcc-patches-return-444535-patch=linaro.org@gcc.gnu.org DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; q=dns; s=default; b=nYVeGfNjkG/288skWIewCSdwqN/E7 glMkXCRUk1IIWxRzDQ12yOBXmLCZcuD/g83/TbbiyrW9dHq478RUcB87CRM9lKE1 jZc5DoZyypTsAuDEgxs6GCOOkhhbfMUd/6/O3PVNxZGpxBi7tcJ6hGi0uRd6MAh1 X1oyTNnCYTBtl8= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:references:message-id:date:mime-version:in-reply-to :content-type; s=default; bh=tS2vqYdhgZNRcQECBtZV2PxHZ7Y=; b=EyF dwfqhatTnXWhetUdUA3dB1ilJ8CJi1zStBIS/kvyXMl955phLIzNsC7T3E+pzNPi Qww/cwQuUOMhVhyMGbqmaHBXsLd8GYFk/UmTZLfUF1JS7/P+yGBJkKZSm7mk27vw //rNPo2+CCSwjPo6yrVTdiCyXGeyKjl72kBPiAPE= Received: (qmail 45001 invoked by alias); 15 Dec 2016 16:08:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 44926 invoked by uid 89); 15 Dec 2016 16:08:13 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-5.0 required=5.0 tests=BAYES_00, RP_MATCHES_RCVD, SPF_PASS autolearn=ham version=3.3.2 spammy=CNAME, cname X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Dec 2016 16:08:09 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BB0D41570; Thu, 15 Dec 2016 08:08:07 -0800 (PST) Received: from e105689-lin.cambridge.arm.com (e105689-lin.cambridge.arm.com [10.2.207.32]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6C91A3F445 for ; Thu, 15 Dec 2016 08:08:07 -0800 (PST) From: "Richard Earnshaw (lists)" Subject: [PATCH 21/21] [arm] Permit 'auto' in -mfpu. To: gcc-patches@gcc.gnu.org References: Message-ID: Date: Thu, 15 Dec 2016 16:08:05 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.5.1 MIME-Version: 1.0 In-Reply-To: Now we finally have the infrastructure in place we can now derive details of the FPU from a CPU entry. This patch enables this for the existing cores that already have an explicit FPU in their product names. * arm-fpus.def: Add CNAME field to all FPU definitions. * genopt.sh: Use explicit enumeration tags for FPU entries. * arm-tables.opt: Regenerated. * arm.opt (mfpu): Provide initial value. * arm-opts.h (enum fpu_type): Build the enumeration from the list of available FPUs. Add 'auto' entry on the end. * arm.c (arm_configure_build_target): Only do explicit configuration of the FPU features if the selected FPU is not 'auto'. (arm_option_override): Adjust initialization of arm_fpu_index. Emit an error if we have a hard float ABI request, but the processor does not support floating-point. (arm_option_print): Handle -mfpu=auto. (arm_valid_target_attribute_rec): Don't permit fpu=auto in pragmas or function attributes. (arm_identify_fpu_from_isa): Handle effective soft-float when the FPU is automatically detected. * arm-cores.def (arm1136jf-s): Add feature ISA_FP_DBL. (arm1176jzf-s): Likewise. (mpcore): Likewise. (arm1156t2f-s): Likewise. --- gcc/config/arm/arm-cores.def | 8 +++---- gcc/config/arm/arm-fpus.def | 48 +++++++++++++++++++------------------ gcc/config/arm/arm-opts.h | 10 ++++++++ gcc/config/arm/arm-tables.opt | 46 +++++++++++++++++++----------------- gcc/config/arm/arm.c | 55 ++++++++++++++++++++++++++++++++++--------- gcc/config/arm/arm.opt | 2 +- gcc/config/arm/genopt.sh | 15 +++++++----- 7 files changed, 117 insertions(+), 67 deletions(-) diff --git a/gcc/config/arm/arm-cores.def b/gcc/config/arm/arm-cores.def index a232d37..544579c 100644 --- a/gcc/config/arm/arm-cores.def +++ b/gcc/config/arm/arm-cores.def @@ -124,13 +124,13 @@ ARM_CORE("arm1026ej-s", arm1026ejs, arm1026ejs, TF_LDSCHED, 5TEJ, ISA_FEAT(I /* V6 Architecture Processors */ ARM_CORE("arm1136j-s", arm1136js, arm1136js, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j), 9e) -ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j) ISA_FEAT(isa_bit_VFPv2), 9e) +ARM_CORE("arm1136jf-s", arm1136jfs, arm1136jfs, TF_LDSCHED, 6J, ISA_FEAT(ISA_ARMv6j) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e) ARM_CORE("arm1176jz-s", arm1176jzs, arm1176jzs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz), 9e) -ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(isa_bit_VFPv2), 9e) +ARM_CORE("arm1176jzf-s", arm1176jzfs, arm1176jzfs, TF_LDSCHED, 6KZ, ISA_FEAT(ISA_ARMv6kz) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e) ARM_CORE("mpcorenovfp", mpcorenovfp, mpcorenovfp, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k), 9e) -ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k) ISA_FEAT(isa_bit_VFPv2), 9e) +ARM_CORE("mpcore", mpcore, mpcore, TF_LDSCHED, 6K, ISA_FEAT(ISA_ARMv6k) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), 9e) ARM_CORE("arm1156t2-s", arm1156t2s, arm1156t2s, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2), v6t2) -ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(isa_bit_VFPv2), v6t2) +ARM_CORE("arm1156t2f-s", arm1156t2fs, arm1156t2fs, TF_LDSCHED, 6T2, ISA_FEAT(ISA_ARMv6t2) ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL), v6t2) /* V6M Architecture Processors */ ARM_CORE("cortex-m1", cortexm1, cortexm1, TF_LDSCHED, 6M, ISA_FEAT(ISA_ARMv6m), v6m) diff --git a/gcc/config/arm/arm-fpus.def b/gcc/config/arm/arm-fpus.def index ae8197d..f07711c 100644 --- a/gcc/config/arm/arm-fpus.def +++ b/gcc/config/arm/arm-fpus.def @@ -19,31 +19,33 @@ /* Before using #include to read this file, define a macro: - ARM_FPU(NAME, ISA) + ARM_FPU(NAME, CNAME, ISA) - The arguments are the fields of struct arm_fpu_desc. + NAME is the publicly visible option name. + CNAME is a C-compatible variable name substring. + ISA is the list of feature bits that this FPU provides. genopt.sh assumes no whitespace up to the first "," in each entry. */ -ARM_FPU("vfp", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL)) -ARM_FPU("vfpv2", ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL)) -ARM_FPU("vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32)) -ARM_FPU("vfpv3-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv)) -ARM_FPU("vfpv3-d16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL)) -ARM_FPU("vfpv3-d16-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv)) -ARM_FPU("vfpv3xd", ISA_FEAT(ISA_VFPv3)) -ARM_FPU("vfpv3xd-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv)) -ARM_FPU("neon", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON)) -ARM_FPU("neon-vfpv3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON)) -ARM_FPU("neon-fp16", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv)) -ARM_FPU("vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32)) -ARM_FPU("neon-vfpv4", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON)) -ARM_FPU("vfpv4-d16", ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL)) -ARM_FPU("fpv4-sp-d16", ISA_FEAT(ISA_VFPv4)) -ARM_FPU("fpv5-sp-d16", ISA_FEAT(ISA_FPv5)) -ARM_FPU("fpv5-d16", ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL)) -ARM_FPU("fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32)) -ARM_FPU("neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON)) -ARM_FPU("crypto-neon-fp-armv8", ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO)) +ARM_FPU("vfp", vfp, ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("vfpv2", vfpv2, ISA_FEAT(ISA_VFPv2) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("vfpv3", vfpv3, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32)) +ARM_FPU("vfpv3-fp16", vfpv3_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("vfpv3-d16", vfpv3_d16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("vfpv3-d16-fp16", vfpv3_d16_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_DBL) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("vfpv3xd", vfpv3xd, ISA_FEAT(ISA_VFPv3)) +ARM_FPU("vfpv3xd-fp16", vfpv3xd_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("neon", neon, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON)) +ARM_FPU("neon-vfpv3", neon_vfpv3, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON)) +ARM_FPU("neon-fp16", neon_fp16, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_NEON) ISA_FEAT(isa_bit_fp16conv)) +ARM_FPU("vfpv4", vfpv4, ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_D32)) +ARM_FPU("neon-vfpv4", neon_vfpv4, ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_NEON)) +ARM_FPU("vfpv4-d16", vfpv4_d16, ISA_FEAT(ISA_VFPv4) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("fpv4-sp-d16", fpv4_sp_d16, ISA_FEAT(ISA_VFPv4)) +ARM_FPU("fpv5-sp-d16", fpv5_sp_d16, ISA_FEAT(ISA_FPv5)) +ARM_FPU("fpv5-d16", fpv5_d16, ISA_FEAT(ISA_FPv5) ISA_FEAT(ISA_FP_DBL)) +ARM_FPU("fp-armv8", fp_armv8, ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_FP_D32)) +ARM_FPU("neon-fp-armv8", neon_fp_armv8, ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_NEON)) +ARM_FPU("crypto-neon-fp-armv8", crypto_neon_fp_armv8, ISA_FEAT(ISA_FP_ARMv8) ISA_FEAT(ISA_CRYPTO)) /* Compatibility aliases. */ -ARM_FPU("vfp3", ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32)) +ARM_FPU("vfp3", vfp3, ISA_FEAT(ISA_VFPv3) ISA_FEAT(ISA_FP_D32)) diff --git a/gcc/config/arm/arm-opts.h b/gcc/config/arm/arm-opts.h index 3de110e..846abad 100644 --- a/gcc/config/arm/arm-opts.h +++ b/gcc/config/arm/arm-opts.h @@ -40,6 +40,16 @@ enum processor_type TARGET_CPU_arm_none }; +/* The various ARM FPUs. */ +enum fpu_type +{ +#undef ARM_FPU +#define ARM_FPU(NAME, CNAME, ISA) TARGET_FPU_##CNAME, +#include "arm-fpus.def" + TARGET_FPU_auto +#undef ARM_FPU +}; + /* Which __fp16 format to use. The enumeration values correspond to the numbering for the Tag_ABI_FP_16bit_format attribute. diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt index faa00aa..574eadc 100644 --- a/gcc/config/arm/arm-tables.opt +++ b/gcc/config/arm/arm-tables.opt @@ -464,69 +464,71 @@ EnumValue Enum(arm_arch) String(iwmmxt2) Value(34) Enum -Name(arm_fpu) Type(int) +Name(arm_fpu) Type(enum fpu_type) Known ARM FPUs (for use with the -mfpu= option): EnumValue -Enum(arm_fpu) String(vfp) Value(0) +Enum(arm_fpu) String(vfp) Value(TARGET_FPU_vfp) EnumValue -Enum(arm_fpu) String(vfpv2) Value(1) +Enum(arm_fpu) String(vfpv2) Value(TARGET_FPU_vfpv2) EnumValue -Enum(arm_fpu) String(vfpv3) Value(2) +Enum(arm_fpu) String(vfpv3) Value(TARGET_FPU_vfpv3) EnumValue -Enum(arm_fpu) String(vfpv3-fp16) Value(3) +Enum(arm_fpu) String(vfpv3-fp16) Value(TARGET_FPU_vfpv3_fp16) EnumValue -Enum(arm_fpu) String(vfpv3-d16) Value(4) +Enum(arm_fpu) String(vfpv3-d16) Value(TARGET_FPU_vfpv3_d16) EnumValue -Enum(arm_fpu) String(vfpv3-d16-fp16) Value(5) +Enum(arm_fpu) String(vfpv3-d16-fp16) Value(TARGET_FPU_vfpv3_d16_fp16) EnumValue -Enum(arm_fpu) String(vfpv3xd) Value(6) +Enum(arm_fpu) String(vfpv3xd) Value(TARGET_FPU_vfpv3xd) EnumValue -Enum(arm_fpu) String(vfpv3xd-fp16) Value(7) +Enum(arm_fpu) String(vfpv3xd-fp16) Value(TARGET_FPU_vfpv3xd_fp16) EnumValue -Enum(arm_fpu) String(neon) Value(8) +Enum(arm_fpu) String(neon) Value(TARGET_FPU_neon) EnumValue -Enum(arm_fpu) String(neon-vfpv3) Value(9) +Enum(arm_fpu) String(neon-vfpv3) Value(TARGET_FPU_neon_vfpv3) EnumValue -Enum(arm_fpu) String(neon-fp16) Value(10) +Enum(arm_fpu) String(neon-fp16) Value(TARGET_FPU_neon_fp16) EnumValue -Enum(arm_fpu) String(vfpv4) Value(11) +Enum(arm_fpu) String(vfpv4) Value(TARGET_FPU_vfpv4) EnumValue -Enum(arm_fpu) String(neon-vfpv4) Value(12) +Enum(arm_fpu) String(neon-vfpv4) Value(TARGET_FPU_neon_vfpv4) EnumValue -Enum(arm_fpu) String(vfpv4-d16) Value(13) +Enum(arm_fpu) String(vfpv4-d16) Value(TARGET_FPU_vfpv4_d16) EnumValue -Enum(arm_fpu) String(fpv4-sp-d16) Value(14) +Enum(arm_fpu) String(fpv4-sp-d16) Value(TARGET_FPU_fpv4_sp_d16) EnumValue -Enum(arm_fpu) String(fpv5-sp-d16) Value(15) +Enum(arm_fpu) String(fpv5-sp-d16) Value(TARGET_FPU_fpv5_sp_d16) EnumValue -Enum(arm_fpu) String(fpv5-d16) Value(16) +Enum(arm_fpu) String(fpv5-d16) Value(TARGET_FPU_fpv5_d16) EnumValue -Enum(arm_fpu) String(fp-armv8) Value(17) +Enum(arm_fpu) String(fp-armv8) Value(TARGET_FPU_fp_armv8) EnumValue -Enum(arm_fpu) String(neon-fp-armv8) Value(18) +Enum(arm_fpu) String(neon-fp-armv8) Value(TARGET_FPU_neon_fp_armv8) EnumValue -Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(19) +Enum(arm_fpu) String(crypto-neon-fp-armv8) Value(TARGET_FPU_crypto_neon_fp_armv8) EnumValue -Enum(arm_fpu) String(vfp3) Value(20) +Enum(arm_fpu) String(vfp3) Value(TARGET_FPU_vfp3) +EnumValue +Enum(arm_fpu) String(auto) Value(TARGET_FPU_auto) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 522989d..f068796 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2328,7 +2328,8 @@ char arm_arch_name[] = "__ARM_ARCH_PROFILE__"; const struct arm_fpu_desc all_fpus[] = { -#define ARM_FPU(NAME, ISA) \ +#undef ARM_FPU +#define ARM_FPU(NAME, CNAME, ISA) \ { NAME, {ISA isa_nobit} }, #include "arm-fpus.def" #undef ARM_FPU @@ -3255,12 +3256,19 @@ arm_configure_build_target (struct arm_build_target *target, gcc_assert (arm_selected_cpu); - arm_selected_fpu = &all_fpus[opts->x_arm_fpu_index]; - auto_sbitmap fpu_bits (isa_num_bits); + if (opts->x_arm_fpu_index != TARGET_FPU_auto) + { + arm_selected_fpu = &all_fpus[opts->x_arm_fpu_index]; + auto_sbitmap fpu_bits (isa_num_bits); - arm_initialize_isa (fpu_bits, arm_selected_fpu->isa_bits); - bitmap_and_compl (target->isa, target->isa, isa_all_fpubits); - bitmap_ior (target->isa, target->isa, fpu_bits); + arm_initialize_isa (fpu_bits, arm_selected_fpu->isa_bits); + bitmap_and_compl (target->isa, target->isa, isa_all_fpubits); + bitmap_ior (target->isa, target->isa, fpu_bits); + } + else if (target->core_name == NULL) + /* To support this we need to be able to parse FPU feature options + from the architecture string. */ + sorry ("-mfpu=auto not currently supported without an explicit CPU."); /* The selected cpu may be an architecture, so lookup tuning by core ID. */ if (!arm_selected_tune) @@ -3295,6 +3303,7 @@ arm_option_override (void) { const char *target_fpu_name; bool ok; + int fpu_index; #ifdef FPUTYPE_DEFAULT target_fpu_name = FPUTYPE_DEFAULT; @@ -3302,9 +3311,10 @@ arm_option_override (void) target_fpu_name = "vfp"; #endif - ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &arm_fpu_index, + ok = opt_enum_arg_to_value (OPT_mfpu_, target_fpu_name, &fpu_index, CL_TARGET); gcc_assert (ok); + arm_fpu_index = (enum fpu_type) fpu_index; } /* Create the default target_options structure. We need this early @@ -3448,7 +3458,11 @@ arm_option_override (void) arm_pcs_default = ARM_PCS_AAPCS_IWMMXT; else if (arm_float_abi == ARM_FLOAT_ABI_HARD && TARGET_HARD_FLOAT) - arm_pcs_default = ARM_PCS_AAPCS_VFP; + { + arm_pcs_default = ARM_PCS_AAPCS_VFP; + if (!bitmap_bit_p (arm_active_target.isa, isa_bit_VFPv2)) + error ("-mfloat-abi=hard: selected processor lacks an FPU"); + } else arm_pcs_default = ARM_PCS_AAPCS; } @@ -30210,14 +30224,17 @@ static void arm_option_print (FILE *file, int indent, struct cl_target_option *ptr) { int flags = ptr->x_target_flags; - const struct arm_fpu_desc *fpu_desc = &all_fpus[ptr->x_arm_fpu_index]; + const char *fpu_name; + + fpu_name = (ptr->x_arm_fpu_index == TARGET_FPU_auto + ? "auto" : all_fpus[ptr->x_arm_fpu_index].name); fprintf (file, "%*sselected arch %s\n", indent, "", TARGET_THUMB2_P (flags) ? "thumb2" : TARGET_THUMB_P (flags) ? "thumb1" : "arm"); - fprintf (file, "%*sselected fpu %s\n", indent, "", fpu_desc->name); + fprintf (file, "%*sselected fpu %s\n", indent, "", fpu_name); } /* Hook to determine if one function can safely inline another. */ @@ -30319,12 +30336,22 @@ arm_valid_target_attribute_rec (tree args, struct gcc_options *opts) else if (!strncmp (q, "fpu=", 4)) { + int fpu_index; if (! opt_enum_arg_to_value (OPT_mfpu_, q+4, - &opts->x_arm_fpu_index, CL_TARGET)) + &fpu_index, CL_TARGET)) { error ("invalid fpu for attribute(target(\"%s\"))", q); return false; } + if (fpu_index == TARGET_FPU_auto) + { + /* This doesn't really make sense until we support + general dynamic selection of the architecture and all + sub-features. */ + sorry ("auto fpu selection not currently permitted here"); + return false; + } + opts->x_arm_fpu_index = (enum fpu_type) fpu_index; } else { @@ -30465,6 +30492,12 @@ arm_identify_fpu_from_isa (sbitmap isa) auto_sbitmap cand_fpubits (isa_num_bits); bitmap_and (fpubits, isa, isa_all_fpubits); + + /* If there are no ISA feature bits relating to the FPU, we must be + doing soft-float. */ + if (bitmap_empty_p (fpubits)) + return "softvfp"; + for (unsigned int i = 0; i < ARRAY_SIZE (all_fpus); i++) { arm_initialize_isa (cand_fpubits, all_fpus[i].isa_bits); diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 934144d..3c877b1 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -144,7 +144,7 @@ EnumValue Enum(arm_fp16_format_type) String(alternative) Value(ARM_FP16_FORMAT_ALTERNATIVE) mfpu= -Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index) Save +Target RejectNegative Joined Enum(arm_fpu) Var(arm_fpu_index) Init(TARGET_FPU_auto) Save Specify the name of the target floating point hardware/format. mhard-float diff --git a/gcc/config/arm/genopt.sh b/gcc/config/arm/genopt.sh index 82e5436..3b75711 100755 --- a/gcc/config/arm/genopt.sh +++ b/gcc/config/arm/genopt.sh @@ -77,19 +77,22 @@ awk -F'[(, ]+' 'BEGIN { cat <